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The new optab is used in the middle end to expand to cfcmov. And simplified my patch by trying to generate the conditional faulting movcc in noce_try_cmove_arith function. All the changes passed bootstrap & regtest x86-64-pc-linux-gnu. We also tested spec with SDE and passed the runtime test. Ok for trunk? APX CFCMOV[1] feature implements conditionally faulting which means If the comparison is false, all memory faults are suppressed when load or store a memory operand. Now we could load or store a memory operand may trap or fault for conditional move. In middle-end, now we don't support a conditional move if we knew that a load from A or B could trap or fault. To enable CFCMOV, we added a new optab named cfmovcc. Conditional move suppress fault for condition mem store would not move any arithmetic calculations. For condition mem load now just support a conditional move one trap mem and one no trap and no mem cases. [1].https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gcc/ChangeLog: * doc/md.texi: Add cfmovcc insn pattern explanation. * ifcvt.cc (can_use_cmove_load_mem_notrap): New func for conditional faulting movcc for load. (can_use_cmove_store_mem_notrap): New func for conditional faulting movcc for store. (can_use_cfmovcc): New func for conditional faulting. (noce_try_cmove_arith): Try to convert to conditional faulting movcc. (noce_process_if_block): Ditto. * optabs.cc (emit_conditional_move): Handle cfmovcc. (emit_conditional_move_1): Ditto. * optabs.def (OPTAB_D): New optab. --- gcc/doc/md.texi | 10 ++++ gcc/ifcvt.cc | 119 ++++++++++++++++++++++++++++++++++++++++++++---- gcc/optabs.cc | 14 +++++- gcc/optabs.def | 1 + 4 files changed, 132 insertions(+), 12 deletions(-) -- 2.31.1 diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index a9259112251..5f563787c49 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -8591,6 +8591,16 @@ Return 1 if operand 1 is a normal floating point number and 0 otherwise. @var{m} is a scalar floating point mode. Operand 0 has mode @code{SImode}, and operand 1 has mode @var{m}. +@cindex @code{cfmov@var{mode}cc} instruction pattern +@item @samp{cfmov@var{mode}cc} +Similar to @samp{mov@var{mode}cc} but for conditional faulting, +If the comparison is false, all memory faults are suppressed +when load or store a memory operand. + +Conditionally move operand 2 or operand 3 into operand 0 according +to the comparison in operand 1. If the comparison is true, operand 2 +is moved into operand 0, otherwise operand 3 is moved. + @end table @end ifset diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 6487574c514..59845390607 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -778,6 +778,9 @@ static bool noce_try_store_flag_mask (struct noce_if_info *); static rtx noce_emit_cmove (struct noce_if_info *, rtx, enum rtx_code, rtx, rtx, rtx, rtx, rtx = NULL, rtx = NULL); static bool noce_try_cmove (struct noce_if_info *); +static bool can_use_cmove_load_mem_notrap (rtx, rtx); +static bool can_use_cmove_store_mem_notrap (rtx, rtx, rtx, bool); +static bool can_use_cfmovcc (struct noce_if_info *); static bool noce_try_cmove_arith (struct noce_if_info *); static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **); static bool noce_try_minmax (struct noce_if_info *); @@ -2132,6 +2135,69 @@ noce_emit_bb (rtx last_insn, basic_block bb, bool simple) return true; } +/* Return TRUE if we could convert "if (test) x = *a; else x = b;" + or "if (test) x = a; else x = *b;" to conditional faulting movcc, + i.e. x86 cfcmov, especially when load a or b may cause memmory faults. */ + +static bool +can_use_cmove_load_mem_notrap (rtx a, rtx b) +{ + /* Just handle a conditional move from one trap MEM + other non_trap, + non mem cases. */ + if (!(MEM_P (a) ^ MEM_P (b))) + return false; + bool a_trap = may_trap_or_fault_p (a); + bool b_trap = may_trap_or_fault_p (b); + + if (!(a_trap ^ b_trap)) + return false; + if (a_trap && !MEM_P (a)) + return false; + if (b_trap && !MEM_P (b)) + return false; + + return true; +} + +/* Return TRUE if we could convert "if (test) *x = a; else skip" to + conditional faulting movcc, i.e. x86 cfcmov, especially when store + x may cause memmory faults and in else_bb x == b. */ + +static bool +can_use_cmove_store_mem_notrap (rtx x, rtx a, rtx b, bool a_simple) +{ + gcc_assert (MEM_P (x)); + + machine_mode x_mode = GET_MODE (x); + + if (!rtx_equal_p (x, b) || !may_trap_or_fault_p (x)) + return false; + if (!a_simple || !register_operand (a, x_mode)) + return false; + + return true; +} + +/* Return TRUE if backend supports cfmovcc_optab, which suppressed memory + faults when load or store a memory operand and the condition code + evaluates to false. */ + +static bool +can_use_cfmovcc (struct noce_if_info *if_info) +{ + rtx a = if_info->a; + rtx b = if_info->b; + rtx x = if_info->x; + + if (optab_handler (cfmovcc_optab, GET_MODE (x)) == CODE_FOR_nothing) + return false; + + if (MEM_P (x)) + return can_use_cmove_store_mem_notrap (x, a, b, if_info->then_simple); + else + return can_use_cmove_load_mem_notrap (a, b); +} + /* Try more complex cases involving conditional_move. */ static bool @@ -2171,7 +2237,15 @@ noce_try_cmove_arith (struct noce_if_info *if_info) /* ??? We could handle this if we knew that a load from A or B could not trap or fault. This is also true if we've already loaded from the address along the path from ENTRY. */ - else if (may_trap_or_fault_p (a) || may_trap_or_fault_p (b)) + else if (may_trap_or_fault_p (a) && may_trap_or_fault_p (b)) + return false; + /* cfmovcc_optab implements conditionally faulting which means + that if the condition code evaluates to false, all memory faults + are suppressed when load or store a memory operand. Now we could + load or store a memory operand may trap or fault for conditional + move. */ + else if ((may_trap_or_fault_p (a) || may_trap_or_fault_p (b)) + && !can_use_cfmovcc (if_info)) return false; /* if (test) x = a + b; else x = c - d; @@ -2247,9 +2321,14 @@ noce_try_cmove_arith (struct noce_if_info *if_info) /* If either operand is complex, load it into a register first. The best way to do this is to copy the original insn. In this way we preserve any clobbers etc that the insn may have had. - This is of course not possible in the IS_MEM case. */ + This is of course not possible in the IS_MEM case. + For load or store a operands may trap or fault, should not + hoist the load or store, otherwise it unable to suppress memory + fault, it just a normal arithmetic insn insteads of conditional + faulting movcc. */ - if (! general_operand (a, GET_MODE (a)) || tmp_a) + if (! may_trap_or_fault_p (a) + && (! general_operand (a, GET_MODE (a)) || tmp_a)) { if (is_mem) @@ -2278,7 +2357,8 @@ noce_try_cmove_arith (struct noce_if_info *if_info) } } - if (! general_operand (b, GET_MODE (b)) || tmp_b) + if (! may_trap_or_fault_p (b) + && (! general_operand (b, GET_MODE (b)) || tmp_b)) { if (is_mem) { @@ -4210,12 +4290,31 @@ noce_process_if_block (struct noce_if_info *if_info) } if (!set_b && MEM_P (orig_x)) - /* We want to avoid store speculation to avoid cases like - if (pthread_mutex_trylock(mutex)) - ++global_variable; - Rather than go to much effort here, we rely on the SSA optimizers, - which do a good enough job these days. */ - return false; + { + /* When target support conditional faulting movcc, i.e. x86 cfcmov, + we could do conditonal mem store for "if (...) *x = a; else skip" + to cfmovcc_optab, which x may trap or fault. */ + if ((optab_handler (cfmovcc_optab, GET_MODE (orig_x)) + != CODE_FOR_nothing) + && HAVE_conditional_move + && may_trap_or_fault_p (orig_x) + && register_operand (a, GET_MODE (orig_x))) + { + x = orig_x; + if_info->x = x; + if (noce_try_cmove_arith (if_info)) + goto success; + else + return false; + } + /* We want to avoid store speculation to avoid cases like + if (pthread_mutex_trylock(mutex)) + ++global_variable; + Rather than go to much effort here, we rely on the SSA optimizers, + which do a good enough job these days. */ + else + return false; + } if (noce_try_move (if_info)) goto success; diff --git a/gcc/optabs.cc b/gcc/optabs.cc index 2bcb3f7b47a..181edf64f03 100644 --- a/gcc/optabs.cc +++ b/gcc/optabs.cc @@ -5034,6 +5034,7 @@ emit_conditional_move (rtx target, struct rtx_comparison comp, rtx_insn *last; enum insn_code icode; enum rtx_code reversed; + optab op = movcc_optab; /* If the two source operands are identical, that's just a move. */ @@ -5082,7 +5083,11 @@ emit_conditional_move (rtx target, struct rtx_comparison comp, if (mode == VOIDmode) mode = GET_MODE (op2); - icode = direct_optab_handler (movcc_optab, mode); + if ((may_trap_or_fault_p (op2) || may_trap_or_fault_p (op3)) + && optab_handler (cfmovcc_optab, mode) != CODE_FOR_nothing) + op = cfmovcc_optab; + + icode = direct_optab_handler (op, mode); if (icode == CODE_FOR_nothing) return NULL_RTX; @@ -5194,6 +5199,7 @@ emit_conditional_move_1 (rtx target, rtx comparison, rtx op2, rtx op3, machine_mode mode) { enum insn_code icode; + optab op = movcc_optab; if (comparison == NULL_RTX || !COMPARISON_P (comparison)) return NULL_RTX; @@ -5214,7 +5220,11 @@ emit_conditional_move_1 (rtx target, rtx comparison, if (mode == VOIDmode) mode = GET_MODE (op2); - icode = direct_optab_handler (movcc_optab, mode); + if ((may_trap_or_fault_p (op2) || may_trap_or_fault_p (op3)) + && optab_handler (cfmovcc_optab, mode) != CODE_FOR_nothing) + op = cfmovcc_optab; + + icode = direct_optab_handler (op, mode); if (icode == CODE_FOR_nothing) return NULL_RTX; diff --git a/gcc/optabs.def b/gcc/optabs.def index 58a939442bd..893e5c1c6c2 100644 --- a/gcc/optabs.def +++ b/gcc/optabs.def @@ -551,3 +551,4 @@ OPTAB_D (len_store_optab, "len_store_$a") OPTAB_D (select_vl_optab, "select_vl$a") OPTAB_D (andn_optab, "andn$a3") OPTAB_D (iorn_optab, "iorn$a3") +OPTAB_D (cfmovcc_optab, "cfmov$acc") From patchwork Fri Sep 6 06:27:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kong, Lingling" X-Patchwork-Id: 1981576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=bKz/QII9; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; 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(ix86_expand_int_cfmovcc): Expand to cfcmov pattern. * config/i386/i386-opts.h (enum apx_features): New. * config/i386/i386-protos.h (ix86_expand_int_cfmovcc): Define. * config/i386/i386.cc (ix86_rtx_costs): Add UNSPEC_APX_CFCMOV cost. * config/i386/i386.h (TARGET_APX_CFCMOV): Define. * config/i386/i386.md (cfmovcc): New define_expand. (*cfmovcc): New define_insn. (*cfmovcc_2): Ditto. (*cfmovccz): Ditto. (UNSPEC_APX_CFCMOV): New unspec for cfcmov. * config/i386/i386.opt: Add enum value for cfcmov. gcc/testsuite/ChangeLog: * gcc.target/i386/apx-cfcmov-1.c: New test. * gcc.target/i386/apx-cfcmov-2.c: Ditto. --- gcc/config/i386/i386-expand.cc | 67 ++++++++++++++++++ gcc/config/i386/i386-opts.h | 4 +- gcc/config/i386/i386-protos.h | 1 + gcc/config/i386/i386.cc | 16 +++-- gcc/config/i386/i386.h | 1 + gcc/config/i386/i386.md | 60 +++++++++++++++- gcc/config/i386/i386.opt | 3 + gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c | 73 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c | 40 +++++++++++ 9 files changed, 259 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c create mode 100644 gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c -- 2.31.1 diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 124cb976ec8..7ba445a189b 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -3368,6 +3368,73 @@ ix86_expand_int_addcc (rtx operands[]) return true; } +/* Return TRUE if we could convert "if (test) x = a; else x = b;" to cfcmov, + especially when load a or b or x store may cause memmory faults. */ + +bool +ix86_can_cfcmov_p (rtx x, rtx a, rtx b) +{ + machine_mode mode = GET_MODE (x); + /* Conditional load for cfcmov. */ + if (register_operand (x, mode) + /* "if (test) x = *a; else x = b;". */ + && ((MEM_P (a) && register_operand (b, mode)) + /* "if (test) x = *a; else x = 0;". */ + || (MEM_P (a) && b == const0_rtx) + /* "if (test) x = a; else x = *b;". */ + || (register_operand (a, mode) && MEM_P (b)))) + return true; + /* Conditional store "if (test) *x = a; else skip;". */ + else if (MEM_P (x) && x == b && register_operand (a, mode)) + return true; + return false; +} + +bool +ix86_expand_int_cfmovcc (rtx operands[]) +{ + machine_mode mode = GET_MODE (operands[0]); + if ((mode != DImode && mode != SImode && mode != HImode) + || !TARGET_APX_CFCMOV) + return false; + enum rtx_code code = GET_CODE (operands[1]); + rtx_insn *compare_seq; + rtx compare_op; + rtx op0 = XEXP (operands[1], 0); + rtx op1 = XEXP (operands[1], 1); + rtx op2 = operands[2]; + rtx op3 = operands[3]; + + start_sequence (); + compare_op = ix86_expand_compare (code, op0, op1); + compare_seq = get_insns (); + end_sequence (); + + /* Just handle a conditional move from one trap MEM + other non_trap, + non mem cases. */ + + if (may_trap_or_fault_p (op2) ^ may_trap_or_fault_p (op3)) + { + if (ix86_can_cfcmov_p (operands[0], op2, op3)) + { + if (may_trap_or_fault_p (op2)) + op2 = gen_rtx_UNSPEC (mode, gen_rtvec (1, operands[2]), + UNSPEC_APX_CFCMOV); + if (may_trap_or_fault_p (op3)) + op3 = gen_rtx_UNSPEC (mode, gen_rtvec (1, operands[3]), + UNSPEC_APX_CFCMOV); + emit_insn (compare_seq); + emit_insn (gen_rtx_SET (operands[0], + gen_rtx_IF_THEN_ELSE (mode, + compare_op, + op2, op3))); + return true; + } + return false; + } + return false; +} + bool ix86_expand_int_movcc (rtx operands[]) { diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h index c7ec0d9fd39..711519ffb53 100644 --- a/gcc/config/i386/i386-opts.h +++ b/gcc/config/i386/i386-opts.h @@ -143,8 +143,10 @@ enum apx_features { apx_nf = 1 << 4, apx_ccmp = 1 << 5, apx_zu = 1 << 6, + apx_cfcmov = 1 << 7, apx_all = apx_egpr | apx_push2pop2 | apx_ndd - | apx_ppx | apx_nf | apx_ccmp | apx_zu, + | apx_ppx | apx_nf | apx_ccmp | apx_zu + | apx_cfcmov, }; #endif diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 3a7bc949e56..5a0692c2125 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -153,6 +153,7 @@ extern bool ix86_match_ccmode (rtx, machine_mode); extern bool ix86_match_ptest_ccmode (rtx); extern void ix86_expand_branch (enum rtx_code, rtx, rtx, rtx); extern void ix86_expand_setcc (rtx, enum rtx_code, rtx, rtx); +extern bool ix86_expand_int_cfmovcc (rtx[]); extern bool ix86_expand_int_movcc (rtx[]); extern bool ix86_expand_fp_movcc (rtx[]); extern bool ix86_expand_fp_vcond (rtx[]); diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index e8744fa77ea..96ee28af078 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -22256,10 +22256,18 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, *total = COSTS_N_INSNS (1); if (!COMPARISON_P (XEXP (x, 0)) && !REG_P (XEXP (x, 0))) *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed); - if (!REG_P (XEXP (x, 1))) - *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed); - if (!REG_P (XEXP (x, 2))) - *total += rtx_cost (XEXP (x, 2), mode, code, 2, speed); + rtx op1, op2; + op1 = XEXP (x, 1); + op2 = XEXP (x, 2); + /* Handle UNSPEC_APX_CFCMOV for cfcmov. */ + if (GET_CODE (op1) == UNSPEC && XINT (op1, 1) == UNSPEC_APX_CFCMOV) + op1 = XVECEXP (op1, 0, 0); + if (GET_CODE (op2) == UNSPEC && XINT (op2, 1) == UNSPEC_APX_CFCMOV) + op2 = XVECEXP (op2, 0, 0); + if (!REG_P (op1)) + *total += rtx_cost (op1, mode, code, 1, speed); + if (!REG_P (op2)) + *total += rtx_cost (op2, mode, code, 2, speed); return true; } return false; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index c1ec92ffb15..f2c20e159d3 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -58,6 +58,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_APX_NF (ix86_apx_features & apx_nf) #define TARGET_APX_CCMP (ix86_apx_features & apx_ccmp) #define TARGET_APX_ZU (ix86_apx_features & apx_zu) +#define TARGET_APX_CFCMOV (ix86_apx_features & apx_cfcmov) #include "config/vxworks-dummy.h" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 0fae3c1eb87..f3593a32449 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -223,6 +223,9 @@ ;; For APX CCMP support ;; DFV = default flag value UNSPEC_APX_DFV + + ;; For APX CFCMOV support + UNSPEC_APX_CFCMOV ]) (define_c_enum "unspecv" [ @@ -581,7 +584,7 @@ noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni, avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,avxneconvert, avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl, - vaes_avx512vl,noapx_nf,avx10_2" + vaes_avx512vl,noapx_nf,avx10_2,apx_cfcmov" (const_string "base")) ;; The (bounding maximum) length of an instruction immediate. @@ -989,6 +992,7 @@ (eq_attr "mmx_isa" "avx") (symbol_ref "TARGET_MMX_WITH_SSE && TARGET_AVX") (eq_attr "isa" "noapx_nf") (symbol_ref "!TARGET_APX_NF") + (eq_attr "isa" "apx_cfcmov") (symbol_ref "TARGET_APX_CFCMOV") ] (const_int 1))) @@ -25774,6 +25778,15 @@ "" "if (ix86_expand_int_movcc (operands)) DONE; else FAIL;") +(define_expand "cfmovcc" + [(set (match_operand:SWIM 0 "nonimmediate_operand") + (if_then_else:SWIM (match_operand 1 "comparison_operator") + (match_operand:SWIM 2 "") + (match_operand:SWIM 3 "")))] + "TARGET_APX_CFCMOV" + "if (ix86_expand_int_cfmovcc (operands)) DONE; else FAIL;") + + ;; Data flow gets confused by our desire for `sbbl reg,reg', and clearing ;; the register first winds up with `sbbl $0,reg', which is also weird. ;; So just document what we're doing explicitly. @@ -25875,6 +25888,51 @@ (set (match_dup 0) (neg:SWI (ltu:SWI (reg:CCC FLAGS_REG) (const_int 0))))]) +(define_insn "*cfmovcc" + [(set (match_operand:SWI248 0 "register_operand" "=r,r") + (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (unspec:SWI248 + [(match_operand:SWI248 2 "memory_operand" "m,m")] + UNSPEC_APX_CFCMOV) + (match_operand:SWI248 3 "reg_or_0_operand" "C,r")))] + "TARGET_CMOVE && TARGET_APX_CFCMOV" + "@ + cfcmov%O2%C1\t{%2, %0|%0, %2} + cfcmov%O2%C1\t{%2, %3, %0|%0, %3, %2}" + [(set_attr "isa" "*,apx_ndd") + (set_attr "type" "icmov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*cfmovcc_2" + [(set (match_operand:SWI248 0 "nonimmediate_operand" "=r,m") + (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (match_operand:SWI248 2 "register_operand" "r,r") + (unspec:SWI248 + [(match_operand:SWI248 3 "memory_operand" "m,0")] + UNSPEC_APX_CFCMOV)))] + "TARGET_CMOVE && TARGET_APX_CFCMOV" + "@ + cfcmov%O2%c1\t{%3, %2, %0|%0, %2, %3} + cfcmov%O2%C1\t{%2, %0|%0, %2}" + [(set_attr "isa" "apx_ndd,*") + (set_attr "type" "icmov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*cfmovccz" + [(set (match_operand:SWI248 0 "register_operand" "=r") + (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (match_operand:SWI248 2 "register_operand" "r") + (match_operand:SWI248 3 "const0_operand" "C")))] + "TARGET_CMOVE && TARGET_APX_CFCMOV" + "cfcmov%O2%C1\t{%2, %0|%0, %2}" + [(set_attr "type" "icmov") + (set_attr "mode" "")]) + (define_insn "*movcc_noc" [(set (match_operand:SWI248 0 "register_operand" "=r,r,r,r") (if_then_else:SWI248 (match_operator 1 "ix86_comparison_operator" diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index fe16e44a4ea..c03314a0d49 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1345,6 +1345,9 @@ Enum(apx_features) String(ccmp) Value(apx_ccmp) Set(7) EnumValue Enum(apx_features) String(zu) Value(apx_zu) Set(8) +EnumValue +Enum(apx_features) String(cfcmov) Value(apx_cfcmov) Set(9) + EnumValue Enum(apx_features) String(all) Value(apx_all) Set(1) diff --git a/gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c b/gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c new file mode 100644 index 00000000000..4a1fb91b24c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-cfcmov-1.c @@ -0,0 +1,73 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -mapxf" } */ + +/* { dg-final { scan-assembler-times "cfcmovne" 1 } } */ +/* { dg-final { scan-assembler-times "cfcmovg" 2} } */ +/* { dg-final { scan-assembler-times "cfcmove" 1 } } */ +/* { dg-final { scan-assembler-times "cfcmovl" 2 } } */ +/* { dg-final { scan-assembler-times "cfcmovle" 1 } } */ + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_store (int a, int b, int c, int d, int *arr) +{ + if (a != b) + *arr = c; + return d; + +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_ndd (int a, int b, int c, int *p) +{ + if (a > b) + return *p; + return c; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_2_trap (int a, int b, int *c, int *p) +{ + if (a > b) + return *p; + return *c; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_zero (int a, int b, int c) +{ + int sum = 0; + if (a == b) + return c; + return sum; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_mem (int a, int b, int *p) +{ + int sum = 0; + if (a < b ) + sum = *p; + return sum; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_arith_1 (int a, int b, int c, int *p) +{ + int sum = 0; + if (a > b) + sum = *p; + else + sum = a + c; + return sum + 1; +} + +__attribute__((noinline, noclone, target("apxf"))) +int cfc_load_arith_2 (int a, int b, int c, int *p) +{ + int sum = 0; + if (a > b) + sum = a + c; + else + sum = *p; + return sum + 1; +} diff --git a/gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c b/gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c new file mode 100644 index 00000000000..2b1660f64fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/apx-cfcmov-2.c @@ -0,0 +1,40 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-require-effective-target apxf } */ +/* { dg-options "-mapxf -march=x86-64 -O3" } */ + +#include "apx-cfcmov-1.c" + +extern void abort (void); + +int main () +{ + if (!__builtin_cpu_supports ("apxf")) + return 0; + + int arr = 6; + int arr1 = 5; + int res = cfc_store (1, 2, 3, 4, &arr); + if (arr != 3 && res != 4) + abort (); + res = cfc_load_ndd (2, 1, 2, &arr); + if (res != 3) + abort (); + res = cfc_load_2_trap (1, 2, &arr1, &arr); + if (res != 5) + abort (); + res = cfc_load_zero (1, 2, 3); + res = cfc_load_zero (1, 2, 3); + if (res != 0) + abort (); + res = cfc_load_mem (2, 1, &arr); + if (res != 0) + abort (); + res = cfc_load_arith_1 (1, 2, 3, &arr); + if (res != 5) + abort(); + res = cfc_load_arith_2 (2, 1, 3,&arr); + if (res != 6) + abort(); + return 0; +} +