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Mon, 02 Sep 2024 13:02:05 -0700 (PDT) Received: from marvin.dc1.ventanamicro.com ([189.4.72.88]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-715e569f485sm7205182b3a.129.2024.09.02.13.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2024 13:02:05 -0700 (PDT) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jlaw@ventanamicro.com, vineetg@rivosinc.com, Raphael Moreira Zinsly Subject: [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants Date: Mon, 2 Sep 2024 17:01:55 -0300 Message-ID: <20240902200157.328705-1-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_ABUSEAT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Improve handling of constants where its upper and lower 32-bit halves are the same and have negative values. e.g. for: unsigned long f (void) { return 0xf0f0f0f0f0f0f0f0UL; } Without the patch: li a0,-252645376 addi a0,a0,240 li a5,-252645376 addi a5,a5,241 slli a5,a5,32 add a0,a5,a0 With the patch: li a5,252645376 addi a5,a5,-241 slli a0,a5,32 add a0,a0,a5 xori a0,a0,-1 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_split_integer_cost): Adjust the cost of negative repeating constants. (riscv_split_integer): Handle negative repeating constants. gcc/testsuite/ChangeLog: * gcc.target/riscv/synthesis-11.c: New test. --- gcc/config/riscv/riscv.cc | 25 +++++++++++++---- gcc/testsuite/gcc.target/riscv/synthesis-11.c | 28 +++++++++++++++++++ 2 files changed, 47 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-11.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d03e51f3a68..b963a57881e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1242,8 +1242,8 @@ static int riscv_split_integer_cost (HOST_WIDE_INT val) { int cost; - unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); - unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); + unsigned HOST_WIDE_INT loval = val & 0xffffffff; + unsigned HOST_WIDE_INT hival = (val & ~loval) >> 32; struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; /* This routine isn't used by pattern conditions, so whether or @@ -1254,6 +1254,8 @@ riscv_split_integer_cost (HOST_WIDE_INT val) cost = 2 + riscv_build_integer (codes, loval, VOIDmode, allow_new_pseudos); if (loval != hival) cost += riscv_build_integer (codes, hival, VOIDmode, allow_new_pseudos); + else if ((loval & 0x80000000) != 0) + cost = 3 + riscv_build_integer (codes, ~loval & 0xffffffff, VOIDmode, allow_new_pseudos); return cost; } @@ -1276,11 +1278,16 @@ riscv_integer_cost (HOST_WIDE_INT val, bool allow_new_pseudos) static rtx riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) { - unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); - unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); + unsigned HOST_WIDE_INT loval = val & 0xffffffff; + unsigned HOST_WIDE_INT hival = (val & ~loval) >> 32; rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); + rtx x = gen_reg_rtx (mode); + bool eq_neg = (loval == hival) && ((loval & 0x80000000) != 0); - riscv_move_integer (lo, lo, loval, mode); + if (eq_neg) + riscv_move_integer (lo, lo, ~loval & 0xffffffff, mode); + else + riscv_move_integer (lo, lo, loval, mode); if (loval == hival) hi = gen_rtx_ASHIFT (mode, lo, GEN_INT (32)); @@ -1291,7 +1298,13 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) } hi = force_reg (mode, hi); - return gen_rtx_PLUS (mode, hi, lo); + x = gen_rtx_PLUS (mode, hi, lo); + if (eq_neg) + { + x = force_reg (mode, x); + x = gen_rtx_XOR (mode, x, GEN_INT (-1)); + } + return x; } /* Return true if X is a thread-local symbol. */ diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-11.c b/gcc/testsuite/gcc.target/riscv/synthesis-11.c new file mode 100644 index 00000000000..89e48edb2d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/synthesis-11.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* We aggressively skip as we really just need to test the basic synthesis + which shouldn't vary based on the optimization level. -O1 seems to work + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv64gc" } */ + +/* Rather than test for a specific synthesis of all these constants or + having thousands of tests each testing one variant, we just test the + total number of instructions. + + This isn't expected to change much and any change is worthy of a look. */ +/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|pack|ret|sh1add|sh2add|sh3add|slli|srli|xori)" 60 } } */ + + + +unsigned long foo_0xf857f2def857f2de(void) { return 0xf857f2def857f2deUL; } +unsigned long foo_0x99660e6399660e63(void) { return 0x99660e6399660e63UL; } +unsigned long foo_0x937f1b75937f1b75(void) { return 0x937f1b75937f1b75UL; } +unsigned long foo_0xb5019fa0b5019fa0(void) { return 0xb5019fa0b5019fa0UL; } +unsigned long foo_0xb828e6c1b828e6c1(void) { return 0xb828e6c1b828e6c1UL; } +unsigned long foo_0x839d87e9839d87e9(void) { return 0x839d87e9839d87e9UL; } +unsigned long foo_0xc29617c1c29617c1(void) { return 0xc29617c1c29617c1UL; } +unsigned long foo_0xa4118119a4118119(void) { return 0xa4118119a4118119UL; } +unsigned long foo_0x8c01df7d8c01df7d(void) { return 0x8c01df7d8c01df7dUL; } +unsigned long foo_0xf0e23d6bf0e23d6b(void) { return 0xf0e23d6bf0e23d6bUL; } From patchwork Mon Sep 2 20:01:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Moreira Zinsly X-Patchwork-Id: 1979754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 02 Sep 2024 13:02:07 -0700 (PDT) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jlaw@ventanamicro.com, vineetg@rivosinc.com, Raphael Moreira Zinsly Subject: [PATCH 2/3] RISC-V: Additional large constant synthesis improvements Date: Mon, 2 Sep 2024 17:01:56 -0300 Message-ID: <20240902200157.328705-2-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240902200157.328705-1-rzinsly@ventanamicro.com> References: <20240902200157.328705-1-rzinsly@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_ABUSEAT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Improve handling of large constants in riscv_build_integer, generate better code for constants where the high half can be constructed by shifting/shiftNadding the low half or if the halves differ by less than 2k. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer): Detect new case of constants that can be improved. (riscv_move_integer): Add synthesys for concatening constants without Zbkb. gcc/testsuite/ChangeLog: * gcc.target/riscv/synthesis-12.c: New test. * gcc.target/riscv/synthesis-13.c: New test. * gcc.target/riscv/synthesis-14.c: New test. --- gcc/config/riscv/riscv.cc | 140 +++++++++++++++++- gcc/testsuite/gcc.target/riscv/synthesis-12.c | 26 ++++ gcc/testsuite/gcc.target/riscv/synthesis-13.c | 26 ++++ gcc/testsuite/gcc.target/riscv/synthesis-14.c | 28 ++++ 4 files changed, 214 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-14.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index b963a57881e..64d5611cbd2 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1231,6 +1231,124 @@ riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, } } + else if (cost > 4 && TARGET_64BIT && can_create_pseudo_p () + && allow_new_pseudos) + { + struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; + int alt_cost; + + unsigned HOST_WIDE_INT loval = value & 0xffffffff; + unsigned HOST_WIDE_INT hival = (value & ~loval) >> 32; + bool bit31 = (hival & 0x80000000) != 0; + int trailing_shift = ctz_hwi (loval) - ctz_hwi (hival); + int leading_shift = clz_hwi (loval) - clz_hwi (hival); + int shiftval = 0; + + /* Adjust the shift into the high half accordingly. */ + if ((trailing_shift > 0 && hival == (loval >> trailing_shift)) + || (trailing_shift < 0 && hival == (loval << trailing_shift))) + shiftval = 32 - trailing_shift; + else if ((leading_shift < 0 && hival == (loval >> leading_shift)) + || (leading_shift > 0 && hival == (loval << leading_shift))) + shiftval = 32 + leading_shift; + + if (shiftval && !bit31) + alt_cost = 2 + riscv_build_integer_1 (alt_codes, sext_hwi (loval, 32), + mode); + + /* For constants where the upper half is a shift of the lower half we + can do a shift followed by an or. */ + if (shiftval && alt_cost < cost && !bit31) + { + /* We need to save the first constant we build. */ + alt_codes[alt_cost - 3].save_temporary = true; + + /* Now we want to shift the previously generated constant into the + high half. */ + alt_codes[alt_cost - 2].code = ASHIFT; + alt_codes[alt_cost - 2].value = shiftval; + alt_codes[alt_cost - 2].use_uw = false; + alt_codes[alt_cost - 2].save_temporary = false; + + /* And the final step, IOR the two halves together. Since this uses + the saved temporary, use CONCAT similar to what we do for Zbkb. */ + alt_codes[alt_cost - 1].code = CONCAT; + alt_codes[alt_cost - 1].value = 0; + alt_codes[alt_cost - 1].use_uw = false; + alt_codes[alt_cost - 1].save_temporary = false; + + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } + + if (cost > 4 && !bit31 && TARGET_ZBA) + { + int value = 0; + + /* Check for a shNadd. */ + if (hival == loval * 3) + value = 3; + else if (hival == loval * 5) + value = 5; + else if (hival == loval * 9) + value = 9; + + if (value) + alt_cost = 2 + riscv_build_integer_1 (alt_codes, + sext_hwi (loval, 32), mode); + + /* For constants where the upper half is a shNadd of the lower half + we can do a similar transformation. */ + if (value && alt_cost < cost) + { + alt_codes[alt_cost - 3].save_temporary = true; + alt_codes[alt_cost - 2].code = FMA; + alt_codes[alt_cost - 2].value = value; + alt_codes[alt_cost - 2].use_uw = false; + alt_codes[alt_cost - 2].save_temporary = false; + alt_codes[alt_cost - 1].code = CONCAT; + alt_codes[alt_cost - 1].value = 0; + alt_codes[alt_cost - 1].use_uw = false; + alt_codes[alt_cost - 1].save_temporary = false; + + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } + } + + if (cost > 4 && !bit31) + { + int value = hival - loval; + + /* For constants were the halves differ by less than 2048 we can + generate the upper half by using an addi on the lower half then + using a shift 32 followed by an or. */ + if (abs (value) <= 2047) + { + alt_cost = 3 + riscv_build_integer_1 (alt_codes, + sext_hwi (loval, 32), mode); + if (alt_cost < cost) + { + alt_codes[alt_cost - 4].save_temporary = true; + alt_codes[alt_cost - 3].code = PLUS; + alt_codes[alt_cost - 3].value = value; + alt_codes[alt_cost - 3].use_uw = false; + alt_codes[alt_cost - 3].save_temporary = false; + alt_codes[alt_cost - 2].code = ASHIFT; + alt_codes[alt_cost - 2].value = 32; + alt_codes[alt_cost - 2].use_uw = false; + alt_codes[alt_cost - 2].save_temporary = false; + alt_codes[alt_cost - 1].code = CONCAT; + alt_codes[alt_cost - 1].value = 0; + alt_codes[alt_cost - 1].use_uw = false; + alt_codes[alt_cost - 1].save_temporary = false; + + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } + } + } + } return cost; } @@ -2864,12 +2982,22 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, } else if (codes[i].code == CONCAT || codes[i].code == VEC_MERGE) { - rtx t = can_create_pseudo_p () ? gen_reg_rtx (mode) : temp; - rtx t2 = codes[i].code == VEC_MERGE ? old_value : x; - gcc_assert (t2); - t2 = gen_lowpart (SImode, t2); - emit_insn (gen_riscv_xpack_di_si_2 (t, x, GEN_INT (32), t2)); - x = t; + if (codes[i].code == CONCAT && !TARGET_ZBKB) + { + /* The two values should have no bits in common, so we can + use PLUS instead of IOR which has a higher chance of + using a compressed instruction. */ + x = gen_rtx_PLUS (mode, x, old_value); + } + else + { + rtx t = can_create_pseudo_p () ? gen_reg_rtx (mode) : temp; + rtx t2 = codes[i].code == VEC_MERGE ? old_value : x; + gcc_assert (t2); + t2 = gen_lowpart (SImode, t2); + emit_insn (gen_riscv_xpack_di_si_2 (t, x, GEN_INT (32), t2)); + x = t; + } } else x = gen_rtx_fmt_ee (codes[i].code, mode, diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-12.c b/gcc/testsuite/gcc.target/riscv/synthesis-12.c new file mode 100644 index 00000000000..bf2f89042a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/synthesis-12.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* We aggressively skip as we really just need to test the basic synthesis + which shouldn't vary based on the optimization level. -O1 seems to work + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv64gc" } */ + +/* Rather than test for a specific synthesis of all these constants or + having thousands of tests each testing one variant, we just test the + total number of instructions. + + This isn't expected to change much and any change is worthy of a look. */ +/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|pack|ret|sh1add|sh2add|sh3add|slli|srli|xori|or)" 45 } } */ + + +unsigned long foo_0x7857f2de7857f2de(void) { return 0x7857f2de7857f2deUL; } +unsigned long foo_0x7fffdffe3fffefff(void) { return 0x7fffdffe3fffefffUL; } +unsigned long foo_0x1ffff7fe3fffeffc(void) { return 0x1ffff7fe3fffeffcUL; } +unsigned long foo_0x0a3fdbf0028ff6fc(void) { return 0x0a3fdbf0028ff6fcUL; } +unsigned long foo_0x014067e805019fa0(void) { return 0x014067e805019fa0UL; } +unsigned long foo_0x09d87e90009d87e9(void) { return 0x09d87e90009d87e9UL; } +unsigned long foo_0x2302320000118119(void) { return 0x2302320000118119UL; } +unsigned long foo_0x000711eb00e23d60(void) { return 0x000711eb00e23d60UL; } +unsigned long foo_0x5983800001660e00(void) { return 0x5983800001660e00UL; } diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-13.c b/gcc/testsuite/gcc.target/riscv/synthesis-13.c new file mode 100644 index 00000000000..957410acda1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/synthesis-13.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* We aggressively skip as we really just need to test the basic synthesis + which shouldn't vary based on the optimization level. -O1 seems to work + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv64gc_zba" } */ + +/* Rather than test for a specific synthesis of all these constants or + having thousands of tests each testing one variant, we just test the + total number of instructions. + + This isn't expected to change much and any change is worthy of a look. */ +/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|pack|ret|sh1add|sh2add|sh3add|slli|srli|xori|or)" 45 } } */ + + +unsigned long foo_0x7907d89a2857f2de(void) { return 0x7907d89a2857f2deUL; } +unsigned long foo_0x4fffaffb0fffefff(void) { return 0x4fffaffb0fffefffUL; } +unsigned long foo_0x23ff6fdc03ffeffc(void) { return 0x23ff6fdc03ffeffcUL; } +unsigned long foo_0x170faedc028ff6fc(void) { return 0x170faedc028ff6fcUL; } +unsigned long foo_0x5704dee01d019fa0(void) { return 0x5704dee01d019fa0UL; } +unsigned long foo_0x0589c731009d87e9(void) { return 0x0589c731009d87e9UL; } +unsigned long foo_0x0057857d00118119(void) { return 0x0057857d00118119UL; } +unsigned long foo_0x546b32e010e23d60(void) { return 0x546b32e010e23d60UL; } +unsigned long foo_0x64322a0021660e00(void) { return 0x64322a0021660e00UL; } diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-14.c b/gcc/testsuite/gcc.target/riscv/synthesis-14.c new file mode 100644 index 00000000000..bd4e4afa55a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/synthesis-14.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* We aggressively skip as we really just need to test the basic synthesis + which shouldn't vary based on the optimization level. -O1 seems to work + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv64gc" } */ + +/* Rather than test for a specific synthesis of all these constants or + having thousands of tests each testing one variant, we just test the + total number of instructions. + + This isn't expected to change much and any change is worthy of a look. */ +/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|pack|ret|sh1add|sh2add|sh3add|slli|srli|xori|or)" 65 } } */ + + +unsigned long foo_0x7857faae7857f2de(void) { return 0x7857faae7857f2deUL; } +unsigned long foo_0x0ffff7fe0fffefff(void) { return 0x0ffff7fe0fffefffUL; } +unsigned long foo_0x7857f2de7857faae(void) { return 0x7857f2de7857faaeUL; } +unsigned long foo_0x7857f2af7857faae(void) { return 0x7857f2af7857faaeUL; } +unsigned long foo_0x5fbfffff5fbffae5(void) { return 0x5fbfffff5fbffae5UL; } +unsigned long foo_0x3d3079db3d3079ac(void) { return 0x3d3079db3d3079acUL; } +unsigned long foo_0x046075fe046078a8(void) { return 0x046075fe046078a8UL; } +unsigned long foo_0x2411811a24118119(void) { return 0x2411811a24118119UL; } +unsigned long foo_0x70e23d6a70e23d6b(void) { return 0x70e23d6a70e23d6bUL; } +unsigned long foo_0x0c01df8c0c01df7d(void) { return 0x0c01df8c0c01df7dUL; } +unsigned long foo_0x7fff07d07fff0000(void) { return 0x7fff07d07fff0000UL; } From patchwork Mon Sep 2 20:01:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Raphael Moreira Zinsly X-Patchwork-Id: 1979755 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 02 Sep 2024 13:02:09 -0700 (PDT) From: Raphael Moreira Zinsly To: gcc-patches@gcc.gnu.org Cc: jlaw@ventanamicro.com, vineetg@rivosinc.com, Raphael Moreira Zinsly Subject: [PATCH 3/3] RISC-V: Constant synthesis of inverted halves Date: Mon, 2 Sep 2024 17:01:57 -0300 Message-ID: <20240902200157.328705-3-rzinsly@ventanamicro.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240902200157.328705-1-rzinsly@ventanamicro.com> References: <20240902200157.328705-1-rzinsly@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_ABUSEAT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_SBL_A autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Improve handling of constants where the high half can be constructed by inverting the lower half. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_build_integer): Detect constants were the higher half is the lower half inverted. gcc/testsuite/ChangeLog: * gcc.target/riscv/synthesis-15.c: New test. --- gcc/config/riscv/riscv.cc | 30 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/synthesis-15.c | 26 ++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/synthesis-15.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 64d5611cbd2..9eb62e34b5b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1343,6 +1343,36 @@ riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, alt_codes[alt_cost - 1].use_uw = false; alt_codes[alt_cost - 1].save_temporary = false; + memcpy (codes, alt_codes, sizeof (alt_codes)); + cost = alt_cost; + } + } + } + + if (cost > 5 && !bit31) + { + /* For constants where the upper half is the lower half inverted we can flip + it with an xor and do a shift 32 followed by an or. */ + if (hival == (~loval & 0xffffffff)) + { + alt_cost = 3 + riscv_build_integer_1 (alt_codes, + sext_hwi (loval, 32), mode); + if (alt_cost < cost) + { + alt_codes[alt_cost - 4].save_temporary = true; + alt_codes[alt_cost - 3].code = XOR; + alt_codes[alt_cost - 3].value = -1; + alt_codes[alt_cost - 3].use_uw = false; + alt_codes[alt_cost - 3].save_temporary = false; + alt_codes[alt_cost - 2].code = ASHIFT; + alt_codes[alt_cost - 2].value = 32; + alt_codes[alt_cost - 2].use_uw = false; + alt_codes[alt_cost - 2].save_temporary = false; + alt_codes[alt_cost - 1].code = CONCAT; + alt_codes[alt_cost - 1].value = 0; + alt_codes[alt_cost - 1].use_uw = false; + alt_codes[alt_cost - 1].save_temporary = false; + memcpy (codes, alt_codes, sizeof (alt_codes)); cost = alt_cost; } diff --git a/gcc/testsuite/gcc.target/riscv/synthesis-15.c b/gcc/testsuite/gcc.target/riscv/synthesis-15.c new file mode 100644 index 00000000000..eaec6119a72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/synthesis-15.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target rv64 } */ +/* We aggressively skip as we really just need to test the basic synthesis + which shouldn't vary based on the optimization level. -O1 seems to work + and eliminates the usual sources of extraneous dead code that would throw + off the counts. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O2" "-O3" "-Os" "-Oz" "-flto" } } */ +/* { dg-options "-march=rv64gc" } */ + +/* Rather than test for a specific synthesis of all these constants or + having thousands of tests each testing one variant, we just test the + total number of instructions. + + This isn't expected to change much and any change is worthy of a look. */ +/* { dg-final { scan-assembler-times "\\t(add|addi|bseti|li|pack|ret|sh1add|sh2add|sh3add|slli|srli|xori|or)" 60 } } */ + +unsigned long foo_0x4afe605fb5019fa0(void) { return 0x4afe605fb5019fa0UL; } +unsigned long foo_0x07a80d21f857f2de(void) { return 0x07a80d21f857f2deUL; } +unsigned long foo_0x6699f19c99660e63(void) { return 0x6699f19c99660e63UL; } +unsigned long foo_0x6c80e48a937f1b75(void) { return 0x6c80e48a937f1b75UL; } +unsigned long foo_0x47d7193eb828e6c1(void) { return 0x47d7193eb828e6c1UL; } +unsigned long foo_0x7c627816839d87e9(void) { return 0x7c627816839d87e9UL; } +unsigned long foo_0x3d69e83ec29617c1(void) { return 0x3d69e83ec29617c1UL; } +unsigned long foo_0x5bee7ee6a4118119(void) { return 0x5bee7ee6a4118119UL; } +unsigned long foo_0x73fe20828c01df7d(void) { return 0x73fe20828c01df7dUL; } +unsigned long foo_0x0f1dc294f0e23d6b(void) { return 0x0f1dc294f0e23d6bUL; }