From patchwork Mon Sep 2 17:53:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 1979712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=mNYl8g3Y; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WyGc63bxmz1yXY for ; Tue, 3 Sep 2024 03:54:44 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C849F385E458 for ; Mon, 2 Sep 2024 17:54:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 8D203385E82D for ; Mon, 2 Sep 2024 17:53:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8D203385E82D Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8D203385E82D Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::631 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725299633; cv=none; b=K+UPaiIYNQprz7+UQzUn1itlolEszLVUtVfz5CTCwOgrkDqj/Ryhz10+YiGuySKwiCv7wdss0YNwTwa1MfYE9wqGTalfSNYSJnvWzkykTXyw8+fsDhjbBP3wBgG86+NRTGN9nifUwkgqxLrHhvzbKQsyXKeE89Qebji71SQBTaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1725299633; c=relaxed/simple; bh=yiTXB0Uzulzz2OVt10FYTiQveK12xeEx788LuG7ndRA=; h=DKIM-Signature:Message-ID:Date:MIME-Version:To:From:Subject; b=DfZc6QbzDvH1wmUN1Na57kP6uCPCmqyhx6p1t1kqpOHzrf2rahQLBzu7T+cxraMVs0psLZ5F8NqZbMIeON5XmIaKzL/ZdB2BntLgL9aSYLj2lCv4p8MABluS7F3OMtdlaaKAxevfr4v4qKnlgXbT0s8GRVZpVy3uJ3wntErCEes= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1fee6435a34so30903405ad.0 for ; Mon, 02 Sep 2024 10:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1725299629; x=1725904429; darn=gcc.gnu.org; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=5JvpjowXikzMPfsMySkgh7YNZm/uSkwOFK2nRyodUME=; b=mNYl8g3YtJY+CeKR8N+taQyt//GV21CCubT73+J70vMSACpFePwj9SP30fBmipCmiu FoKOwbGtCOsAtS1SQvuZlkkWdxCk0TYkYJUjVRd5vHrG4SPtjFxOZ6V0pSF9ptGedNHO 6SGR723HIBM1N7uYiE1tmHNTNh6/O+bqVMZez7JE0mVUrq/2oNUpp7SazEp1uYYf5uwF kBTDf3PhAWcB+ut3YznY1evOeQJzvb0OfU5aHH0ztL93VlZBXd2b8S0Qjs373hjM+4mi xzCGH2W+96DMX9hwpCSKU9+7WBmJYMazmzjMLprRyJ7LVr9b8gwCD5AqrbEcBt8BNJev P6Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1725299629; x=1725904429; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5JvpjowXikzMPfsMySkgh7YNZm/uSkwOFK2nRyodUME=; b=TvJD+Z5ZotWxA+y9TlNA6PmcuUk33ntpM3FuybbrAxN2a4rt8CNViV5pO+zigP9TXK rEWbfRhu8ozNBSgkNW5HAf27GmbRxv66nWHW4j0sLrdK2Cyh6BvDL5N0ewO5bTSqg5md bKVyAscbiGkaDgoR3HyV11/PD4xQPaTj1oHDupU6rX8at/b5HTdAsfLJLeG+S3M0sBFf ykvcC7RDy9eZCRjaDQGA8joKmgbgok6IFXNH4pvC69WTfB7d6GVDkXcSfc+Nc16L79lF gIKriOSx6NCBzriHJLaW0AA8ErFzmeWjY/0dBCQO4RSJU20XXkgJR1kJD+CKA48NNtAN pSFA== X-Gm-Message-State: AOJu0YwiHvMJK3DUDwRgKwHm9uuS0Iz8LjG9CtKhpG8DVXTxubwEtM2n khDud/1PuaWM6v0n23KzH/ZLqexVx9TDGFnlBQNdQMeLGzmTuhxlRI3VFw== X-Google-Smtp-Source: AGHT+IFML8dfy5nFGVa0lNPLNNeo1RAcS8DQaALN2z9o1S/IU7JuZ0AJuBfpg7FoKqQae5X+YS3gbQ== X-Received: by 2002:a17:903:2301:b0:205:86f5:333d with SMTP id d9443c01a7336-20586f5376fmr20528495ad.55.1725299628889; Mon, 02 Sep 2024 10:53:48 -0700 (PDT) Received: from [172.31.0.109] ([136.36.72.243]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-205152d6a8dsm68844295ad.94.2024.09.02.10.53.46 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Sep 2024 10:53:48 -0700 (PDT) Message-ID: <7c038242-8663-4d94-9175-ea23397faae2@gmail.com> Date: Mon, 2 Sep 2024 11:53:44 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: "gcc-patches@gcc.gnu.org" From: Jeff Law Subject: [to-be-committed] [PR target/115921] Improve reassociation for rv64 X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org As Jovan pointed out in pr115921, we're not reassociating expressions like this on rv64: (x & 0x3e) << 12 It generates something like this: li a5,258048 slli a0,a0,12 and a0,a0,a5 We have a pattern that's designed to clean this up. Essentially reassociating the operations so that we don't need to load the constant resulting in something like this: andi a0,a0,63 slli a0,a0,12 That pattern wasn't working for certain constants due to its condition. The condition is trying to avoid cases where this kind of reassociation would hinder shadd generation on rv64. That condition was just written poorly. This patch tightens up that condition in a few ways. First, there's no need to worry about shadd cases if ZBA is not enabled. Second we can't use shadd if the shift value isn't 1, 2 or 3. Finally rather than open-coding one of the tests, we can use an existing operand predicate. The net is we'll start performing this transformation in more cases on rv64 while still avoiding reassociation if it would spoil shadd generation. Waiting on the pre-commit testing before taking any further action. Jeff diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3289ed2155a..58b31658e0a 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2925,7 +2925,9 @@ (define_insn_and_split "*si3_extend_mask" ;; for IOR/XOR. It probably doesn't matter for AND. ;; ;; We also don't want to do this if the immediate already fits in a simm12 -;; field. +;; field, or is a single bit operand, or when we might be able to generate +;; a shift-add sequence via the splitter in bitmanip.md +;; in bitmanip.md for masks that are a run of consecutive ones. (define_insn_and_split "_shift_reverse" [(set (match_operand:X 0 "register_operand" "=r") (any_bitwise:X (ashift:X (match_operand:X 1 "register_operand" "r") @@ -2934,9 +2936,9 @@ (define_insn_and_split "_shift_reverse" "(!SMALL_OPERAND (INTVAL (operands[3])) && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])) && popcount_hwi (INTVAL (operands[3])) > 1 - && (!TARGET_64BIT - || (exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) - == -1)) + && (!(TARGET_64BIT && TARGET_ZBA) + || !consecutive_bits_operand (operands[3], VOIDmode) + || !imm123_operand (operands[2], VOIDmode)) && (INTVAL (operands[3]) & ((1ULL << INTVAL (operands[2])) - 1)) == 0)" "#" "&& 1" diff --git a/gcc/testsuite/gcc.target/riscv/pr115921.c b/gcc/testsuite/gcc.target/riscv/pr115921.c new file mode 100644 index 00000000000..e508e7ce790 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr115921.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zba" { target { rv64 } } } */ +/* { dg-options "-O2 -march=rv32gc_zba" { target { rv32 } } } */ + +typedef unsigned long target_wide_uint_t; + +target_wide_uint_t test_ashift_and(target_wide_uint_t x) { + return (x & 0x3f) << 12; +} + +/* { dg-final { scan-assembler-times "\\sandi" 1 } } */ +/* { dg-final { scan-assembler-times "\\sslli" 1 } } */ +