From patchwork Fri Aug 30 03:04:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1978677 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=oFLj2QMP; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ww32813fMz1yZ9 for ; Fri, 30 Aug 2024 13:06:05 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B96A8385C6C8 for ; Fri, 30 Aug 2024 03:06:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id 8A5BE3858408 for ; Fri, 30 Aug 2024 03:05:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A5BE3858408 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8A5BE3858408 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724987140; cv=none; b=rZYKGkDfOzcilI3X6HaFZlerjln72BFYQG+QOHjYITYIm94r4JJUBKAo2G5n7wUOiOueU2Us+QjB6iAqEsJ6j2FiRncKsnH5Q3wc/tgsmEHfL3n5jxgdnQXRbZbx5TTnb+W9et2ZwGUaaMRdz13R0s2PjW2tdvMwpc+VrOj2hcY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724987140; c=relaxed/simple; bh=V0ysFVULtQIrW7FfkO7kBI6ghEpOhAqd7JGUIrRSp7c=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=u5BKSjGVzbbpLZsnvR1DSkLN8wkYkQm2m4TURAeNJId9pMLErQGqnwe+hlvRTG1Occ4N9FMGiYnQrFOGa+SVkO7G/XHT6XOe5rii5gvtqOgEhXFB4ITFCM1GgrWjhGBBUfnZxn014jyRotMFaat4q9zITVS4iLzQeuGLq5mekqE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724987138; x=1756523138; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=V0ysFVULtQIrW7FfkO7kBI6ghEpOhAqd7JGUIrRSp7c=; b=oFLj2QMPAZ+3yXygG25Hex/9OpXpxJFnAF4D1C3BJbLOZ/ocRW60r8xL gwVcw8zBUyYpVYKBZwGBK5EKoL0qKUPVT5eCRODsnHdOhzOqTValVG82H lnXPVq0GoabgWnttOzc8c6VNCSL4LmoGkTEDvONscaOc5yBFNef06IJU3 MRitZvtfQswUueRO5efHPGE/J3KDFnkS9PSUTKCdfMV0aP8AjFiMyaPDo HwdSG/tjKUsUrmAxvPtV+FQhbUSRKwZNiW9Spre33RKlQWst4u9Mjap3v 40udn1zfQla8Z3CVfHUTKWxvOWVQsa1frx05JHluIUDN0TmeFzqU1Xyd0 Q==; X-CSE-ConnectionGUID: dbZ3gJkXQXWjOqm6U9MkAg== X-CSE-MsgGUID: KyH2ngZXTSeQHFuA4YFfXg== X-IronPort-AV: E=McAfee;i="6700,10204,11179"; a="23132867" X-IronPort-AV: E=Sophos;i="6.10,187,1719903600"; d="scan'208";a="23132867" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2024 20:05:36 -0700 X-CSE-ConnectionGUID: YwPDJi3wTcGBmFJ3l2MspA== X-CSE-MsgGUID: bvPKfY2DQZKhO5roFGHg3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,187,1719903600"; d="scan'208";a="63725991" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa009.jf.intel.com with ESMTP; 29 Aug 2024 20:05:34 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM Date: Fri, 30 Aug 2024 11:04:54 +0800 Message-ID: <20240830030456.503727-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add test cases for the unsigned vector .SAT_ADD when one of the operand is IMM. Form 3: #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) \ T __attribute__((noinline)) \ vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \ { \ unsigned i; \ T ret; \ for (i = 0; i < limit; i++) \ { \ out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \ } \ } DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 123) The below test are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: New test. Signed-off-by: Pan Li --- .../rvv/autovec/binop/vec_sat_u_add_imm-10.c | 14 ++++++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-11.c | 14 ++++++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-12.c | 14 ++++++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-9.c | 14 ++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-10.c | 28 +++++++++++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-11.c | 28 +++++++++++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-12.c | 28 +++++++++++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-9.c | 28 +++++++++++++++++++ 8 files changed, 168 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c new file mode 100644 index 00000000000..b6b605ac615 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm15_uint16_t_fmt_3: +** ... +** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15 +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c new file mode 100644 index 00000000000..6da86a1abe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm33u_uint32_t_fmt_3: +** ... +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c new file mode 100644 index 00000000000..b6ff5a6d5d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm129ull_uint64_t_fmt_3: +** ... +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c new file mode 100644 index 00000000000..15e0a0567d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm9u_uint8_t_fmt_3: +** ... +** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9 +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c new file mode 100644 index 00000000000..a96fd757f15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 0u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 1u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 65534u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 65535u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0u, N); + RUN (T, out, d[1][0], d[1][1], 1u, N); + RUN (T, out, d[2][0], d[2][1], 65534u, N); + RUN (T, out, d[3][0], d[3][1], 65535u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c new file mode 100644 index 00000000000..bdfe5e8f7d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 0u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 1u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 4294967295u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 4294967294u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0u, N); + RUN (T, out, d[1][0], d[1][1], 1u, N); + RUN (T, out, d[2][0], d[2][1], 4294967294u, N); + RUN (T, out, d[3][0], d[3][1], 4294967295u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c new file mode 100644 index 00000000000..bf89c358243 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 0ull) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 1ull) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 18446744073709551614ull) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 18446744073709551615ull) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0ull, N); + RUN (T, out, d[1][0], d[1][1], 1ull, N); + RUN (T, out, d[2][0], d[2][1], 18446744073709551614ull, N); + RUN (T, out, d[3][0], d[3][1], 18446744073709551615ull, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c new file mode 100644 index 00000000000..e218779829a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 0u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 1u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 254u) +DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 255u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0u, N); + RUN (T, out, d[1][0], d[1][1], 1u, N); + RUN (T, out, d[2][0], d[2][1], 254u, N); + RUN (T, out, d[3][0], d[3][1], 255u, N); + + return 0; +} From patchwork Fri Aug 30 03:04:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1978678 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=mPBG+QhF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Ww3283Fdyz1ygJ for ; Fri, 30 Aug 2024 13:06:08 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 80C7E3861825 for ; Fri, 30 Aug 2024 03:06:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id 3EE3D385840F for ; Fri, 30 Aug 2024 03:05:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3EE3D385840F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3EE3D385840F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724987143; cv=none; b=QLxm2NUtZLz47NrzzWjeKgbZYo5MqoViTDdLrvTKoR9AsZvOMH6yNP4/wT+ANOFoLCPQACsoU3vRSmujrrzrKYUNFFFLyUrof2wC7cnMs2tfj+jEHRel5OSsmzNIR3+BncTmIX6+dYwIua8RAk9uJOA656shK5BkZQWa6sbo9tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724987143; c=relaxed/simple; bh=pHB7tKU6hXszoWUxeh1QocguRaUVcMUIDMce4Azhkw8=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=jlh22VMYqRejDAg2bRj02ZSKnfOR4F9DA31lcHbQNPMSpUfeGzNtg5lT6nF+rU1yI2FtosUOvNJH4Jstlt6H5WeNmHc7rZTqCf0Qgm/NcqU7FZQlpscNn8RIAURixGJHCb5AZLcNwKcV/OokT5cvSrvf63hGUQHO/kOVznDQAOI= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724987140; x=1756523140; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pHB7tKU6hXszoWUxeh1QocguRaUVcMUIDMce4Azhkw8=; b=mPBG+QhFtuSUBGT7rzghz+7uotcAnzyPyMJaU9NQfF/2VaVT0wBm7yUP 2W8qpUaVNsIIYU2M8wlVCbNovopk7Ti3XJ3TZshCNvnvFWjBBtjw0ikqx k3dwvt2cO39aGnuLAFZPWmDfKXYD9m4Hv0FxB1bA9XfURgMN55KLlZ6JF RAJdehsoUMG1F66icHzE4QayEn2hXYHy3cl/igT9gykU+fL3mAiAACWCT mrXoi0pj+LC4MheRB0m8JfB4c3bJZzBob/luUZtxptZqsJd5OJ9mCNQKV 37vUv8uAp++/7SVYkJvkzurNkZmkiDBR+rM3/IjOhJpY8YcpmPV4O0j9p A==; X-CSE-ConnectionGUID: TKNKJXJ4RAam/ZqSC25HlQ== X-CSE-MsgGUID: +KV/8WRcTQWuvLRd6tgjnA== X-IronPort-AV: E=McAfee;i="6700,10204,11179"; a="23132870" X-IronPort-AV: E=Sophos;i="6.10,187,1719903600"; d="scan'208";a="23132870" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2024 20:05:38 -0700 X-CSE-ConnectionGUID: jPIOtPXtTYapyVFKXHK3XA== X-CSE-MsgGUID: 0ituNiNcQV2m+0YRt4jWpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,187,1719903600"; d="scan'208";a="63725997" Received: from panli.sh.intel.com ([10.239.154.73]) by orviesa009.jf.intel.com with ESMTP; 29 Aug 2024 20:05:36 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 2/2] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM Date: Fri, 30 Aug 2024 11:04:55 +0800 Message-ID: <20240830030456.503727-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240830030456.503727-1-pan2.li@intel.com> References: <20240830030456.503727-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add test cases for the unsigned vector .SAT_ADD when one of the operand is IMM. Form 4: #define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) \ T __attribute__((noinline)) \ vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \ { \ unsigned i; \ T ret; \ for (i = 0; i < limit; i++) \ { \ out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \ } \ } DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 123) The below test are passed for this patch. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c: New test. Signed-off-by: Pan Li --- .../rvv/autovec/binop/vec_sat_u_add_imm-13.c | 14 ++++++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-14.c | 14 ++++++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-15.c | 14 ++++++++++ .../rvv/autovec/binop/vec_sat_u_add_imm-16.c | 14 ++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-13.c | 28 +++++++++++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-14.c | 28 +++++++++++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-15.c | 28 +++++++++++++++++++ .../autovec/binop/vec_sat_u_add_imm-run-16.c | 28 +++++++++++++++++++ .../riscv/rvv/autovec/vec_sat_arith.h | 20 +++++++++++++ 9 files changed, 188 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c new file mode 100644 index 00000000000..a9439dff39f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm9u_uint8_t_fmt_4: +** ... +** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9 +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c new file mode 100644 index 00000000000..dbe47497599 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm15_uint16_t_fmt_4: +** ... +** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15 +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c new file mode 100644 index 00000000000..0ac2e1b2942 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm33u_uint32_t_fmt_4: +** ... +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c new file mode 100644 index 00000000000..9574966401a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "../vec_sat_arith.h" + +/* +** vec_sat_u_add_imm129ull_uint64_t_fmt_4: +** ... +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c new file mode 100644 index 00000000000..612638c7276 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-13.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 254u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 255u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0u, N); + RUN (T, out, d[1][0], d[1][1], 1u, N); + RUN (T, out, d[2][0], d[2][1], 254u, N); + RUN (T, out, d[3][0], d[3][1], 255u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c new file mode 100644 index 00000000000..c5fb4d16b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-14.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 65534u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 65535u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0u, N); + RUN (T, out, d[1][0], d[1][1], 1u, N); + RUN (T, out, d[2][0], d[2][1], 65534u, N); + RUN (T, out, d[3][0], d[3][1], 65535u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c new file mode 100644 index 00000000000..e45beef7c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-15.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 4294967295u) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 4294967294u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0u, N); + RUN (T, out, d[1][0], d[1][1], 1u, N); + RUN (T, out, d[2][0], d[2][1], 4294967294u, N); + RUN (T, out, d[3][0], d[3][1], 4294967295u, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c new file mode 100644 index 00000000000..f0a82f31d4f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-16.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "../vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 0ull) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 1ull) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 18446744073709551614ull) +DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP (T, 18446744073709551615ull) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0ull, N); + RUN (T, out, d[1][0], d[1][1], 1ull, N); + RUN (T, out, d[2][0], d[2][1], 18446744073709551614ull, N); + RUN (T, out, d[3][0], d[3][1], 18446744073709551615ull, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h index deb6bb82eba..23edc48d5bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h @@ -183,6 +183,20 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \ #define DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, IMM) \ DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM) +#define DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) \ +T __attribute__((noinline)) \ +vec_sat_u_add_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit) \ +{ \ + unsigned i; \ + T ret; \ + for (i = 0; i < limit; i++) \ + { \ + out[i] = __builtin_add_overflow (in[i], IMM, &ret) == 0 ? ret : -1; \ + } \ +} +#define DEF_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, IMM) \ + DEF_VEC_SAT_U_ADD_IMM_FMT_4(T, IMM) + #define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \ vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \ VALIDATE_RESULT (out, expect, N) @@ -201,6 +215,12 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \ #define RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP(T, out, op_1, expect, IMM, N) \ RUN_VEC_SAT_U_ADD_IMM_FMT_3(T, out, op_1, expect, IMM, N) +#define RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) \ + vec_sat_u_add_imm##IMM##_##T##_fmt_4(out, op_1, N); \ + VALIDATE_RESULT (out, expect, N) +#define RUN_VEC_SAT_U_ADD_IMM_FMT_4_WRAP(T, out, op_1, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_4(T, out, op_1, expect, IMM, N) + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/