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Thu, 29 Aug 2024 08:29:08 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47T8T6mC007468 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 08:29:06 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 01:28:59 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan Thirumoorthy , Krzysztof Kozlowski , Varadarajan Narayanan Subject: [PATCH v5 1/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock Date: Thu, 29 Aug 2024 13:58:23 +0530 Message-ID: <20240829082830.56959-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829082830.56959-1-quic_varada@quicinc.com> References: <20240829082830.56959-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IEUGW5powLH7yPgBduX067O0XmJqwwSq X-Proofpoint-ORIG-GUID: IEUGW5powLH7yPgBduX067O0XmJqwwSq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_02,2024-08-29_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 mlxscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290062 From: Kathiravan Thirumoorthy Add the definition for GPLL0_OUT_AUX clock. This acts as the parent for the certain networking subsystem (NSS) clocks. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy Signed-off-by: Varadarajan Narayanan --- v5: Update commit message to include why this clock is needed --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 8a405a0a96d0..24486eb47ed8 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -179,6 +179,7 @@ #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 #define GCC_USB0_PIPE_CLK_SRC 172 +#define GPLL0_OUT_AUX 173 #define GCC_ADSS_BCR 0 #define GCC_ADSS_PWM_CLK_ARES 1 From patchwork Thu Aug 29 08:28:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 1978309 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 29 Aug 2024 08:29:21 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 01:29:14 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , CC: Kathiravan Thirumoorthy , Varadarajan Narayanan Subject: [PATCH v5 3/8] dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions Date: Thu, 29 Aug 2024 13:58:25 +0530 Message-ID: <20240829082830.56959-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829082830.56959-1-quic_varada@quicinc.com> References: <20240829082830.56959-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1C7cHWsIzs2dK3lrOyCWFuWtWDi0R0a- X-Proofpoint-ORIG-GUID: 1C7cHWsIzs2dK3lrOyCWFuWtWDi0R0a- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_02,2024-08-29_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290062 From: Kathiravan Thirumoorthy Add NSSCC clock and reset definitions for Qualcomm IPQ5332. Enable interconnect provider ability for use by the ethernet driver. Signed-off-by: Kathiravan Thirumoorthy Signed-off-by: Varadarajan Narayanan --- v5: Marked #power-domain-cells as false Included #interconnect-cells Removed 'Reviewed-by: Krzysztof' due to above changes --- .../bindings/clock/qcom,ipq5332-nsscc.yaml | 64 ++++++++++++++ .../dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 +++++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq5332-nsscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml new file mode 100644 index 000000000000..8a26635e9b19 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ5332 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets and power domains on IPQ5332 + + See also:: + include/dt-bindings/clock/qcom,ipq5332-nsscc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-nsscc + + clocks: + items: + - description: Common PLL nss clock 200M source + - description: Common PLL nss clock 300M source + - description: GCC GPLL0 out aux clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Board XO source + + '#power-domain-cells': false + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@39b00000 { + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&bias_pll_cc_clk>, + <&bias_pll_nss_noc_clk>, + <&gcc_gpll0_out_aux>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&xo_board_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #interconnect-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-nsscc.h b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h new file mode 100644 index 000000000000..c077cde7f57d --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PPE_CLK_SRC 28 +#define NSS_CC_PPE_EDMA_CFG_CLK 29 +#define NSS_CC_PPE_EDMA_CLK 30 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 31 +#define NSS_CC_PPE_SWITCH_CFG_CLK 32 +#define NSS_CC_PPE_SWITCH_CLK 33 +#define NSS_CC_PPE_SWITCH_IPE_CLK 34 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 35 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 36 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 37 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 38 +#define NSS_CC_XGMAC0_PTP_REF_CLK 39 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 40 +#define NSS_CC_XGMAC1_PTP_REF_CLK 41 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 42 + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PPE_BCR 17 +#define NSS_CC_PPE_EDMA_CLK_ARES 18 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 19 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 20 +#define NSS_CC_PPE_SWITCH_CLK_ARES 21 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 23 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 24 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 25 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 27 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 28 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 29 + +#endif From patchwork Thu Aug 29 08:28:26 2024 Content-Type: text/plain; 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Thu, 29 Aug 2024 08:29:28 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47T8TSWY024527 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 29 Aug 2024 08:29:28 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 29 Aug 2024 01:29:21 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v5 4/8] dt-bindings: interconnect: Update master/slave id list Date: Thu, 29 Aug 2024 13:58:26 +0530 Message-ID: <20240829082830.56959-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829082830.56959-1-quic_varada@quicinc.com> References: <20240829082830.56959-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1_dYHAZUSB528sPaioSvAnQpIYD5o0O4 X-Proofpoint-GUID: 1_dYHAZUSB528sPaioSvAnQpIYD5o0O4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-29_02,2024-08-29_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 clxscore=1015 mlxscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408290062 Update the GCC master/slave list to include couple of more interfaces needed by the Network Subsystem Clock Controller (NSSCC) Signed-off-by: Varadarajan Narayanan Acked-by: Krzysztof Kozlowski Acked-by: Georgi Djakov --- include/dt-bindings/interconnect/qcom,ipq5332.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/interconnect/qcom,ipq5332.h b/include/dt-bindings/interconnect/qcom,ipq5332.h index 16475bb07a48..5c08dd3c4f47 100644 --- a/include/dt-bindings/interconnect/qcom,ipq5332.h +++ b/include/dt-bindings/interconnect/qcom,ipq5332.h @@ -28,6 +28,10 @@ #define SLAVE_NSSNOC_TIMEOUT_REF 23 #define MASTER_NSSNOC_XO_DCD 24 #define SLAVE_NSSNOC_XO_DCD 25 +#define MASTER_SNOC_NSSNOC_1_CLK 26 +#define SLAVE_SNOC_NSSNOC_1_CLK 27 +#define MASTER_SNOC_NSSNOC_CLK 28 +#define SLAVE_SNOC_NSSNOC_CLK 29 #define MASTER_NSSNOC_PPE 0 #define SLAVE_NSSNOC_PPE 1