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Wed, 28 Aug 2024 04:33:42 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47S4XfdF026084 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 28 Aug 2024 04:33:41 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 27 Aug 2024 21:33:41 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 1/3] expand: Add debug dump on the cost for `popcount==1` expand Date: Tue, 27 Aug 2024 21:33:29 -0700 Message-ID: <20240828043331.3359171-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 422th5vRFQx3RZ-7QLSGAwgU_xxEJNMX X-Proofpoint-ORIG-GUID: 422th5vRFQx3RZ-7QLSGAwgU_xxEJNMX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-28_02,2024-08-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 bulkscore=0 mlxlogscore=486 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408280029 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org While working on PR 114224, I found it would be useful to dump the different costs of the expansion to make easier to understand why one was chosen over the other. Bootstrapped and tested on x86_64-linux-gnu. Build and tested for aarch64-linux-gnu. gcc/ChangeLog: * internal-fn.cc (expand_POPCOUNT): Dump the costs for the two choices. --- gcc/internal-fn.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc index 89da13b38ce..91210976a0a 100644 --- a/gcc/internal-fn.cc +++ b/gcc/internal-fn.cc @@ -5351,6 +5351,14 @@ expand_POPCOUNT (internal_fn fn, gcall *stmt) unsigned popcount_cost = (seq_cost (popcount_insns, speed_p) + seq_cost (popcount_cmp_insns, speed_p)); unsigned cmp_cost = seq_cost (cmp_insns, speed_p); + + if (dump_file && (dump_flags & TDF_DETAILS)) + { + fprintf(dump_file, "popcount == 1, cost\n"); + fprintf(dump_file, "popcount: %u\n", popcount_cost); + fprintf(dump_file, "cmp: %u\n\n", cmp_cost); + } + if (popcount_cost <= cmp_cost) emit_insn (popcount_insns); else From patchwork Wed Aug 28 04:33:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 1977584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Wed, 28 Aug 2024 04:33:42 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47S4Xfkv008767 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 28 Aug 2024 04:33:41 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 27 Aug 2024 21:33:41 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 2/3] aarch64: Handle cost for vector add reduction Date: Tue, 27 Aug 2024 21:33:30 -0700 Message-ID: <20240828043331.3359171-2-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240828043331.3359171-1-quic_apinski@quicinc.com> References: <20240828043331.3359171-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: OnrSG44ePfv8MLC7uPZKLz7XmWP5JaDq X-Proofpoint-GUID: OnrSG44ePfv8MLC7uPZKLz7XmWP5JaDq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-28_02,2024-08-27_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 mlxlogscore=859 spamscore=0 priorityscore=1501 bulkscore=0 mlxscore=0 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408280028 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org While working on PR 114224 (popcount costs is not modeled), I noticed that addv (vector reduction add) was not handled either. This adds the handling there. Some of the extends are part of the instructions so we need to handle those too. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_rtx_addv_costs): New function. (aarch64_rtx_costs): For unspec_addv, call aarch64_rtx_addv_costs. For unspec_addv under a zero_extend, call aarch64_rtx_addv_costs. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.cc | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 40dacfcf2e7..7607b85e3cf 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -14097,6 +14097,31 @@ aarch64_abd_rtx_p (rtx x) return rtx_equal_p (maxop0, minop0) && rtx_equal_p (maxop1, minop1); } +/* Handle the cost for unspec ADDV (reduction add). + Result is true if the total cost of the operation + has now been calculated. */ +static bool +aarch64_rtx_addv_costs (rtx op0, int *cost, bool speed) +{ + const struct cpu_cost_table *extra_cost + = aarch64_tune_params.insn_extra_cost; + + if (speed) + *cost += extra_cost->vect.alu; + + /* The zero/sign extend part of the reduction is part of the instruction. */ + if (GET_CODE (op0) == ZERO_EXTEND + || GET_CODE (op0) == SIGN_EXTEND) + { + *cost += rtx_cost (XEXP (op0, 0), GET_MODE (XEXP (op0, 0)), + UNSPEC, 0, speed); + return true; + } + + *cost += rtx_cost (op0, GET_MODE (op0), UNSPEC, 0, speed); + return true; +} + /* Calculate the cost of calculating X, storing it in *COST. Result is true if the total cost of the operation has now been calculated. */ static bool @@ -14912,6 +14937,11 @@ cost_plus: case ZERO_EXTEND: op0 = XEXP (x, 0); + /* Addv with an implicit zero extend. */ + if (GET_CODE (op0) == UNSPEC + && XINT (op0, 1) == UNSPEC_ADDV) + return aarch64_rtx_addv_costs (XVECEXP (op0, 0, 0), + cost, speed); /* If a value is written in SI mode, then zero extended to DI mode, the operation will in general be free as a write to a 'w' register implicitly zeroes the upper bits of an 'x' @@ -15378,6 +15408,11 @@ cost_plus: return false; } + /* The vector integer/floating point add reduction instructions. */ + if (XINT (x, 1) == UNSPEC_ADDV + || XINT (x, 1) == UNSPEC_FADDV) + return aarch64_rtx_addv_costs (XVECEXP (x, 0, 0), cost, speed); + break; case TRUNCATE: