From patchwork Tue Aug 27 00:36:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=IptefmF+; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7v13rcnz1yYl for ; Tue, 27 Aug 2024 10:38:21 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5BAC5385E45C for ; Tue, 27 Aug 2024 00:38:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-il1-x132.google.com (mail-il1-x132.google.com [IPv6:2607:f8b0:4864:20::132]) by sourceware.org (Postfix) with ESMTPS id CA9F73858C52 for ; Tue, 27 Aug 2024 00:37:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CA9F73858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CA9F73858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::132 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719063; cv=none; b=wIL0J7OCqvQyZU4FcFe0YzsVd4lW+rVfvGFBLI5elhlfvd2BkQ//WlggTxIWst5KifYzmbgztsldEcNN3iLAmuqB0a5zM8TZgRIJao4QNCPD05rdETKq8rNEaqFhxqSJV6OBt1qSrXtu/prZ3NdzTTq1Tsu1F3IPtOAtgP52DRY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719063; c=relaxed/simple; bh=xwDYAiDIJaBemJZGsCwMkjwIQO/tGOj1sePFj59Ebvg=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=niaaVAdcv4ubrCsgdqiGEKxvUNdNOEZO3dDi5CCYSKTAeuatjYtQ3cyY3ORtmAxcCDBR8je1v1Y7Hza5HvCbfGe3oEeI670lsIvuqxgGTOGeQ6zgngiiIaFuNXHtG7Kmzh5bjFOnMvWxf418R6mBh4m/YJmBVV1ssc/dzuM2t3M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-il1-x132.google.com with SMTP id e9e14a558f8ab-39d3636e955so15780595ab.3 for ; Mon, 26 Aug 2024 17:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719061; x=1725323861; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7knKu+NssPvS2l8mdddz+ZzJgqvvJRyU/WJ0FUX/2OE=; b=IptefmF+cri1l1eCTwYJX1pzgfGHKRAu+DfXD+SJ6BXio2i5FTJK+/OofErGprIuAR Lz29z32c9PnIKj0I7U9bRTtj/KIB0t79OJrOmLVBpvv1Ck7ZFGOucqL9XU6UiImhy3Xq 3c8hjgmkjVyCFBmdiJmBPcROQ6JdEB5Wuogm06nhxvhqQu7EH1xMZ6XGWf7Sn7Uaw+wr aOeqo7XnZTrYw8n9krjOQx42CA93dvwoUFkrR32be0YJ3Yq6+/elLvY6Wk3yltLgdhuy tR3R9a4KKBCsNCD1HwnE/MFO0NmqVuVG4E2ccOctYfcQTCUqzrhGz2h2Tfawr/FiBMPl WEJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719061; x=1725323861; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7knKu+NssPvS2l8mdddz+ZzJgqvvJRyU/WJ0FUX/2OE=; b=XhrYPzRfBNAEmjRPhv58FfN6yMTCjQGN1mYxgqBLPo/NAvYZ0hT+Zx8409adW0soKd eA4H6lt6yS783qisL6Fgs1NSmdAWJto/C/gs8vYlu3kzR/RweQgVrQ9X/n/9kF0xy8Kn l+vmboqrsU2glTGxuKg3FG7yZgUAQvvahlv+oT1cKLBbV3GL/oCBrda7OKTXAHrjgdoP vfX8wJ2uw3vH4Q6QuBB/DW1eDer6TSXY852HpwhuTMg4rxaHJ4jnSHgxLXuGnQXk5JTn sXwzDf573HRLc4AcAEZq+McBuDmKcoQHrQ+ZwpShoT6TXp+jDCMPc0WQfe28VEDmJT2t UVuQ== X-Gm-Message-State: AOJu0YxNFqZ/NZP57G6Qt4s7/Ad1sL7XZofeFV3JrHLdcGEDq7kX8LfE 02z7ej0/8wuNcfqi4pOGC/d6oGEyo0CBHd6LCWOMwqms2u955HTpZNn0ae9+sxG2tNYN79cujdL X X-Google-Smtp-Source: AGHT+IG0iZpodmJM19KXvSfTIA+UdnLRefJfeuwFNPCjrN0v7rvjopNUAWLP6MLz8pcq2/1tpJo9nA== X-Received: by 2002:a05:6e02:2198:b0:398:36c0:7968 with SMTP id e9e14a558f8ab-39e3c9737e7mr137364355ab.6.1724719060622; Mon, 26 Aug 2024 17:37:40 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:40 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 1/9] RISC-V: Fix vid const vector expander for non-npatterns size steps Date: Mon, 26 Aug 2024 17:36:55 -0700 Message-ID: <20240827003710.1513605-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Prior to this patch the expander would emit vectors like: { 0, 0, 5, 5, 10, 10, ...} as: { 0, 0, 2, 2, 4, 4, ...} This patch sets the step size to the requested value. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Fix STEP size in expander. Signed-off-by: Patrick O'Neill --- Detected with the existing testsuite after patch 8/9 is applied: FAIL: gcc.dg/torture/vshuf-v16qi.c -O2 execution test FAIL: gcc.dg/torture/vshuf-v8hi.c -O2 execution test FAIL: gcc.dg/torture/vshuf-v8qi.c -O2 execution test --- gcc/config/riscv/riscv-v.cc | 48 ++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 6 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c89603669e3..a3039a2cb19 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1312,25 +1312,61 @@ expand_const_vector (rtx target, rtx src) /* Generate the variable-length vector following this rule: { a, a, a + step, a + step, a + step * 2, a + step * 2, ...} E.g. { 0, 0, 8, 8, 16, 16, ... } */ - /* We want to create a pattern where value[ix] = floor (ix / + + /* We want to create a pattern where value[idx] = floor (idx / NPATTERNS). As NPATTERNS is always a power of two we can - rewrite this as = ix & -NPATTERNS. */ + rewrite this as = idx & -NPATTERNS. */ /* Step 2: VID AND -NPATTERNS: { 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... } */ rtx imm = gen_int_mode (-builder.npatterns (), builder.inner_mode ()); - rtx tmp = gen_reg_rtx (builder.mode ()); - rtx and_ops[] = {tmp, vid, imm}; + rtx tmp1 = gen_reg_rtx (builder.mode ()); + rtx and_ops[] = {tmp1, vid, imm}; icode = code_for_pred_scalar (AND, builder.mode ()); emit_vlmax_insn (icode, BINARY_OP, and_ops); + + /* Step 3: Convert to step size 1. */ + rtx tmp2 = gen_reg_rtx (builder.mode ()); + /* log2 (npatterns) to get the shift amount to convert + Eg. { 0, 0, 0, 0, 4, 4, ... } + into { 0, 0, 0, 0, 1, 1, ... }. */ + HOST_WIDE_INT shift_amt = exact_log2 (builder.npatterns ()) ; + rtx shift = gen_int_mode (shift_amt, builder.inner_mode ()); + rtx shift_ops[] = {tmp2, tmp1, shift}; + icode = code_for_pred_scalar (ASHIFTRT, builder.mode ()); + emit_vlmax_insn (icode, BINARY_OP, shift_ops); + + /* Step 4: Multiply to step size n. */ + HOST_WIDE_INT step_size = + INTVAL (builder.elt (builder.npatterns ())) + - INTVAL (builder.elt (0)); + rtx tmp3 = gen_reg_rtx (builder.mode ()); + if (pow2p_hwi (step_size)) + { + /* Power of 2 can be handled with a left shift. */ + HOST_WIDE_INT shift = exact_log2 (step_size); + rtx shift_amount = gen_int_mode (shift, Pmode); + insn_code icode = code_for_pred_scalar (ASHIFT, mode); + rtx ops[] = {tmp3, tmp2, shift_amount}; + emit_vlmax_insn (icode, BINARY_OP, ops); + } + else + { + rtx mult_amt = gen_int_mode (step_size, builder.inner_mode ()); + insn_code icode = code_for_pred_scalar (MULT, builder.mode ()); + rtx ops[] = {tmp3, tmp2, mult_amt}; + emit_vlmax_insn (icode, BINARY_OP, ops); + } + + /* Step 5: Add starting value to all elements. */ HOST_WIDE_INT init_val = INTVAL (builder.elt (0)); if (init_val == 0) - emit_move_insn (target, tmp); + emit_move_insn (target, tmp3); else { rtx dup = gen_const_vector_dup (builder.mode (), init_val); - rtx add_ops[] = {target, tmp, dup}; + rtx add_ops[] = {target, tmp3, dup}; icode = code_for_pred (PLUS, builder.mode ()); emit_vlmax_insn (icode, BINARY_OP, add_ops); } From patchwork Tue Aug 27 00:36:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=guJtjC19; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7wq4vH9z1yh3 for ; Tue, 27 Aug 2024 10:39:55 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7C64F385DDFF for ; Tue, 27 Aug 2024 00:39:53 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x32f.google.com (mail-ot1-x32f.google.com [IPv6:2607:f8b0:4864:20::32f]) by sourceware.org (Postfix) with ESMTPS id DD2753858C56 for ; Tue, 27 Aug 2024 00:37:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DD2753858C56 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DD2753858C56 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::32f ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719064; cv=none; b=rlW5cN4jNEO8+peEfa4OfqEC/Sjz4U6qpRXNnZUawrLf7WF0jXKZHurgXIOzWWjCwJMLx6o6guoXFet05DWTTk4GQ68yeoXRSxlImC7j2OO3hjnJVSMu3jb+wWKoc3WU18II5YRPSN0X6SOWidZyYYompRVnidMj64G60lUTFZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719064; c=relaxed/simple; bh=OcHaP9EeizDA+Z5wUrovHX3/o8EcD6C43YFxkuMlDjs=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=cm2ajG3NWiuTyUKjHWJ5ZqEULJaaXsJa8SV7bba6H95g830V+Hv9d9UCmBw9J29a/KiRSCskqWhhlldGv7W+ifoKkrwtyCLDAwBqqjoz/DcwtN0lggzADhVrpJe5j4ScSJAR2fIB1u8lfai76KmJgMSXobCkiaWmmhkBKy8xjHM= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-70e07c1ab31so3936611a34.0 for ; Mon, 26 Aug 2024 17:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719062; x=1725323862; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hCX4M6G+uqRnmXUjmeW8t6JAC1eUsoyECUkz6u9WLS8=; b=guJtjC19vIjU1R4/VxKoFv6sHIEtoBD3j+82se52Bri3cmONyjkyncy3NqzOD32Dhk Bbvqu+GYTyi4lMgutZn3BRq/JdOL/vdh/LvIk514a+7UYvePn2pvKdsIhi5MMHZL++gt UaiSt5xgEqDIwIr18zidPrrHxsWNyJsh3GYd495QAuliERJ7d1UT/8rbFRHyUiwdKEoI s72wBVTB0bVPGevvVfVVvyMLkniaSKfVV4z2EfYF9SXMytIFBWpNZ9O0mFgPvK63ov5B FY4C6i+O48bmpUTRKh9AgZegMm1dYGyEhJkbW2PO+X9LewhOy1f7oz2Spm/BsWvrNE9t UG4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719062; x=1725323862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hCX4M6G+uqRnmXUjmeW8t6JAC1eUsoyECUkz6u9WLS8=; b=YLejQ6eVwisV+DDqMiKCin5XvZUBnoyVMOaFyhAFeR7G4Vd6xDpSJMWzjP5m4wTDIx vOCh7l6Y2lbXeWMT6m5XtIw6pEpIrOt3EuZjcwCULobcsCszPAGbW5kb324gnzBHt0Ub 0JsLxrYivxQ/7dS5gGTqqoVfGHPJOsqM1gdWwro+USJ6QEfn/8Tci59LPivUyuun/lKo UfvaU5OxJUVm8yioqavehp0O9bPcEhEjlLzYU5ahfA7aKuhArKyf++mAkATpEjZwyxAF EB1MkqBGTpdycOhmxnbM+QBL1o4gVyLX6tS9o1pWrjmsA49KdhRQcqxWSKM7a0VfMMP6 IZfQ== X-Gm-Message-State: AOJu0YzYya1Ikz8oaZfgJJEQ0ZprgsidkZCqdA8qfCzm3Rws0mfss3Zz m3Nqw3T0SYpPcbW7mtWWUU8JYGKniCEc7K3pehuqSH3CUqPxb0bGA44l8MMYjzh1Fby590h4gDN Q X-Google-Smtp-Source: AGHT+IGSGRmL4bKDiJUL2W56i4CXfeC69t72F/z1oUbJd9RtYlVLll/1tQ+lmMDZ5zfC0aFBjTVsWg== X-Received: by 2002:a05:6830:4493:b0:704:470d:638a with SMTP id 46e09a7af769-70f482ef0acmr1142576a34.3.1724719061795; Mon, 26 Aug 2024 17:37:41 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:41 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 2/9] RISC-V: Reorder insn cost match order to match corresponding expander match order Date: Mon, 26 Aug 2024 17:36:56 -0700 Message-ID: <20240827003710.1513605-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The corresponding expander (riscv-v.cc:expand_const_vector) matches const_vec_duplicate_p before const_vec_series_p. Reorder to match this behavior when calculating costs. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Relocate. Signed-off-by: Patrick O'Neill --- Ack'd here: https://inbox.sourceware.org/gcc-patches/3a97eb17-32fe-4cf4-874e-5c4a707b2c27@gmail.com/ --- gcc/config/riscv/riscv.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8538d405f50..640394e0cb8 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2142,15 +2142,6 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) ...etc. */ if (riscv_v_ext_mode_p (GET_MODE (x))) { - /* const series vector. */ - rtx base, step; - if (const_vec_series_p (x, &base, &step)) - { - /* This is not accurate, we will need to adapt the COST - * accurately according to BASE && STEP. */ - return 1; - } - rtx elt; if (const_vec_duplicate_p (x, &elt)) { @@ -2186,6 +2177,15 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) return 1 + 4; /*vmv.v.x + memory access. */ } } + + /* const series vector. */ + rtx base, step; + if (const_vec_series_p (x, &base, &step)) + { + /* This cost is not accurate, we will need to adapt the COST + accurately according to BASE && STEP. */ + return 1; + } } /* TODO: We may support more const vector in the future. */ From patchwork Tue Aug 27 00:36:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=mSHPI3kZ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7wq4s3zz1yYl for ; Tue, 27 Aug 2024 10:39:55 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7CEBA385EC31 for ; Tue, 27 Aug 2024 00:39:53 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-oo1-xc2b.google.com (mail-oo1-xc2b.google.com [IPv6:2607:f8b0:4864:20::c2b]) by sourceware.org (Postfix) with ESMTPS id 6A95E3858CDA for ; Tue, 27 Aug 2024 00:37:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6A95E3858CDA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6A95E3858CDA Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::c2b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719067; cv=none; b=X3ASJ05GZN5bFnhZn21uMW1+YfZzgvNsahGgB/ohlGPaZS2GChC2bYX2g7c7DP4V0/O/isc46h7cX0BaJMkOarTKB+fNX+yEZyBVs9Aly8hH9MFIjwM8Uy9YwHdDwYa0GEVX0tQS5b1DEgzMNeZw2zpf81kazTUvGD/q+/35Txg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719067; c=relaxed/simple; bh=ItJfFjY8pag/9uRMgU5aOe9Poyg+8RwDiviIOBMd3Nc=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=PQKu0f2rrmnAjOqIwRHYKiNn4YFaUFj9fMpXnEDfzzJKO6iLGuGfFwm3gspX7Ep9bqZSHyv4E0ND/ISHQUKe0CCKkIcbolbKeqawzdFDLXiJdLVUZZlPXB0YaOJeQJ/yWu5MCiE8jQoHc14sFFYav58WSLRTvmzZ04s0/IBYn7Q= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-oo1-xc2b.google.com with SMTP id 006d021491bc7-5d5b22f97b7so5403234eaf.2 for ; Mon, 26 Aug 2024 17:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719063; x=1725323863; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jQCM6M8BXtAOPvh4ZmaNvTWVteFs9PWNKonsVG0HCIo=; b=mSHPI3kZMeiumUUbtcG7aulDm7U1CInhWBLeAu075SQlkCkX22dBzKeZ6K1Qa2JsFg ttTcWvEaPhsQd7UHdaNXTRF9DiT8mR2t6QZtw95kSdQpQ8vosb7kJtUiA1kOFBLlgEkw ar1otw6RUCJXqySaWRDkWPgfGor2J2zwzgoXFPkkHoUq6iFVORZoZQ1UZ0gv8l9AiSpx YjcOfjHU1oKpcDjTE21hOT/gmE9lIPXxri7fpvkz44ExsTOkoiu47AQ6Hi7mGmPP1+Q0 2l+RKt4QMc/9ObG226MJLkxRSF7jCtw985hpYXjXLiwtPw3o2h7I8d6nN+12TZxYp2cw Ypnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719063; x=1725323863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jQCM6M8BXtAOPvh4ZmaNvTWVteFs9PWNKonsVG0HCIo=; b=Ew0Do6gA/mYbrPX34zTPQaxuePCcJ8yoNNb/A9IMBOTF52+iqGa4fO+aphoDpsz+Ix sAdpJt/BArhhxb5E9plie/QN9AoydMPTtKV2kDUoLvNi/eALHHSRZCsyFZzSlsN9vXKf 7Ha30tMwr/oBoVjrUx9d9eBzPb83a3HerrJXxTHtkvPix6w8uxmlT+TfM3oX5vieeSGo +uyhbom1GlUycpUqZ8pwrD7pRD8PIiD9sd5/QPXE6QSYe3RCCZFTnzcRDsWeRxkHDBwe 4u6ro1z3F+b5K3R0TZTtK7AIbDDms6ICRNmN4suSu71e2G+rfhfnOUEwvPGP76dduL8d 50pw== X-Gm-Message-State: AOJu0Yy0tTWuKqgcG/CbP/41BdxACbhQKJSM6fnfMWt20/mDypTXsxWb Piz0ZoeaZKcbGvrTXL3JYUGTkdfyN9w+Dbgu8i7l+NvwrIQFTeAlpyHV3+euxLJxaIFofzB0mnW 4 X-Google-Smtp-Source: AGHT+IEbwD96cH4n1r8zKc7AFtrF1G6am+J0GJnE1p9AgEA4xZtfAtuni9g9VdkDephfOp69aDCtzg== X-Received: by 2002:a05:6808:4486:b0:3db:2afc:ad6 with SMTP id 5614622812f47-3de2a8d49fcmr16450597b6e.38.1724719063006; Mon, 26 Aug 2024 17:37:43 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:42 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 3/9] RISC-V: Handle case when constant vector construction target rtx is not a register Date: Mon, 26 Aug 2024 17:36:57 -0700 Message-ID: <20240827003710.1513605-4-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This manifests in RTL that is optimized away which causes runtime failures in the testsuite. Update all patterns to use a temp result register if required. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if needed. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 73 +++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 32 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a3039a2cb19..aea4b9b872b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1150,26 +1150,29 @@ static void expand_const_vector (rtx target, rtx src) { machine_mode mode = GET_MODE (target); + rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode); if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) { rtx elt; gcc_assert ( const_vec_duplicate_p (src, &elt) && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[] = {target, src}; + rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops); + + if (result != target) + emit_move_insn (target, result); return; } rtx elt; if (const_vec_duplicate_p (src, &elt)) { - rtx tmp = register_operand (target, mode) ? target : gen_reg_rtx (mode); /* Element in range -16 ~ 15 integer or 0.0 floating-point, we use vmv.v.i instruction. */ if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) { - rtx ops[] = {tmp, src}; + rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops); } else @@ -1186,7 +1189,7 @@ expand_const_vector (rtx target, rtx src) instruction (vsetvl a5, zero). */ if (lra_in_progress) { - rtx ops[] = {tmp, elt}; + rtx ops[] = {result, elt}; emit_vlmax_insn (code_for_pred_broadcast (mode), UNARY_OP, ops); } else @@ -1194,15 +1197,15 @@ expand_const_vector (rtx target, rtx src) struct expand_operand ops[2]; enum insn_code icode = optab_handler (vec_duplicate_optab, mode); gcc_assert (icode != CODE_FOR_nothing); - create_output_operand (&ops[0], tmp, mode); + create_output_operand (&ops[0], result, mode); create_input_operand (&ops[1], elt, GET_MODE_INNER (mode)); expand_insn (icode, 2, ops); - tmp = ops[0].value; + result = ops[0].value; } } - if (tmp != target) - emit_move_insn (target, tmp); + if (result != target) + emit_move_insn (target, result); return; } @@ -1210,7 +1213,10 @@ expand_const_vector (rtx target, rtx src) rtx base, step; if (const_vec_series_p (src, &base, &step)) { - expand_vec_series (target, base, step); + expand_vec_series (result, base, step); + + if (result != target) + emit_move_insn (target, result); return; } @@ -1243,7 +1249,7 @@ expand_const_vector (rtx target, rtx src) all element equal to 0x0706050403020100. */ rtx ele = builder.get_merged_repeating_sequence (); rtx dup = expand_vector_broadcast (builder.new_mode (), ele); - emit_move_insn (target, gen_lowpart (mode, dup)); + emit_move_insn (result, gen_lowpart (mode, dup)); } else { @@ -1272,8 +1278,8 @@ expand_const_vector (rtx target, rtx src) emit_vlmax_insn (code_for_pred_scalar (AND, builder.int_mode ()), BINARY_OP, and_ops); - rtx tmp = gen_reg_rtx (builder.mode ()); - rtx dup_ops[] = {tmp, builder.elt (0)}; + rtx tmp1 = gen_reg_rtx (builder.mode ()); + rtx dup_ops[] = {tmp1, builder.elt (0)}; emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP, dup_ops); for (unsigned int i = 1; i < builder.npatterns (); i++) @@ -1285,12 +1291,12 @@ expand_const_vector (rtx target, rtx src) /* Merge scalar to each i. */ rtx tmp2 = gen_reg_rtx (builder.mode ()); - rtx merge_ops[] = {tmp2, tmp, builder.elt (i), mask}; + rtx merge_ops[] = {tmp2, tmp1, builder.elt (i), mask}; insn_code icode = code_for_pred_merge_scalar (builder.mode ()); emit_vlmax_insn (icode, MERGE_OP, merge_ops); - tmp = tmp2; + tmp1 = tmp2; } - emit_move_insn (target, tmp); + emit_move_insn (result, tmp1); } } else if (CONST_VECTOR_STEPPED_P (src)) @@ -1362,11 +1368,11 @@ expand_const_vector (rtx target, rtx src) /* Step 5: Add starting value to all elements. */ HOST_WIDE_INT init_val = INTVAL (builder.elt (0)); if (init_val == 0) - emit_move_insn (target, tmp3); + emit_move_insn (result, tmp3); else { rtx dup = gen_const_vector_dup (builder.mode (), init_val); - rtx add_ops[] = {target, tmp3, dup}; + rtx add_ops[] = {result, tmp3, dup}; icode = code_for_pred (PLUS, builder.mode ()); emit_vlmax_insn (icode, BINARY_OP, add_ops); } @@ -1396,7 +1402,7 @@ expand_const_vector (rtx target, rtx src) /* Step 2: Generate result = VID + diff. */ rtx vec = v.build (); - rtx add_ops[] = {target, vid, vec}; + rtx add_ops[] = {result, vid, vec}; emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), BINARY_OP, add_ops); } @@ -1412,24 +1418,24 @@ expand_const_vector (rtx target, rtx src) v.quick_push (builder.elt (i)); rtx new_base = v.build (); - /* Step 2: Generate tmp = VID >> LOG2 (NPATTERNS).  */ + /* Step 2: Generate tmp1 = VID >> LOG2 (NPATTERNS).  */ rtx shift_count = gen_int_mode (exact_log2 (builder.npatterns ()), builder.inner_mode ()); - rtx tmp = expand_simple_binop (builder.mode (), LSHIFTRT, + rtx tmp1 = expand_simple_binop (builder.mode (), LSHIFTRT, vid, shift_count, NULL_RTX, false, OPTAB_DIRECT); - /* Step 3: Generate tmp2 = tmp * step.  */ + /* Step 3: Generate tmp2 = tmp1 * step.  */ rtx tmp2 = gen_reg_rtx (builder.mode ()); rtx step = simplify_binary_operation (MINUS, builder.inner_mode (), builder.elt (v.npatterns()), builder.elt (0)); - expand_vec_series (tmp2, const0_rtx, step, tmp); + expand_vec_series (tmp2, const0_rtx, step, tmp1); - /* Step 4: Generate target = tmp2 + new_base.  */ - rtx add_ops[] = {target, tmp2, new_base}; + /* Step 4: Generate result = tmp2 + new_base.  */ + rtx add_ops[] = {result, tmp2, new_base}; emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), BINARY_OP, add_ops); } @@ -1462,13 +1468,13 @@ expand_const_vector (rtx target, rtx src) if (int_mode_for_size (new_smode_bitsize, 0).exists (&new_smode) && get_vector_mode (new_smode, new_nunits).exists (&new_mode)) { - rtx tmp = gen_reg_rtx (new_mode); + rtx tmp1 = gen_reg_rtx (new_mode); base1 = gen_int_mode (rtx_to_poly_int64 (base1), new_smode); - expand_vec_series (tmp, base1, gen_int_mode (step1, new_smode)); + expand_vec_series (tmp1, base1, gen_int_mode (step1, new_smode)); if (rtx_equal_p (base2, const0_rtx) && known_eq (step2, 0)) /* { 1, 0, 2, 0, ... }. */ - emit_move_insn (target, gen_lowpart (mode, tmp)); + emit_move_insn (result, gen_lowpart (mode, tmp1)); else if (known_eq (step2, 0)) { /* { 1, 1, 2, 1, ... }. */ @@ -1478,10 +1484,10 @@ expand_const_vector (rtx target, rtx src) gen_int_mode (builder.inner_bits_size (), new_smode), NULL_RTX, false, OPTAB_DIRECT); rtx tmp2 = gen_reg_rtx (new_mode); - rtx and_ops[] = {tmp2, tmp, scalar}; + rtx and_ops[] = {tmp2, tmp1, scalar}; emit_vlmax_insn (code_for_pred_scalar (AND, new_mode), BINARY_OP, and_ops); - emit_move_insn (target, gen_lowpart (mode, tmp2)); + emit_move_insn (result, gen_lowpart (mode, tmp2)); } else { @@ -1495,10 +1501,10 @@ expand_const_vector (rtx target, rtx src) gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX, false, OPTAB_DIRECT); rtx tmp3 = gen_reg_rtx (new_mode); - rtx ior_ops[] = {tmp3, tmp, shifted_tmp2}; + rtx ior_ops[] = {tmp3, tmp1, shifted_tmp2}; emit_vlmax_insn (code_for_pred (IOR, new_mode), BINARY_OP, ior_ops); - emit_move_insn (target, gen_lowpart (mode, tmp3)); + emit_move_insn (result, gen_lowpart (mode, tmp3)); } } else @@ -1526,7 +1532,7 @@ expand_const_vector (rtx target, rtx src) rtx mask = gen_reg_rtx (builder.mask_mode ()); expand_vec_cmp (mask, EQ, and_vid, CONST1_RTX (mode)); - rtx ops[] = {target, tmp1, tmp2, mask}; + rtx ops[] = {result, tmp1, tmp2, mask}; emit_vlmax_insn (code_for_pred_merge (mode), MERGE_OP, ops); } } @@ -1536,6 +1542,9 @@ expand_const_vector (rtx target, rtx src) } else gcc_unreachable (); + + if (result != target) + emit_move_insn (target, result); } /* Get the frm mode with given CONST_INT rtx, the default mode is From patchwork Tue Aug 27 00:36:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=ADtVAdmk; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7vG410mz1yYl for ; Tue, 27 Aug 2024 10:38:34 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 23E01385E45B for ; Tue, 27 Aug 2024 00:38:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x32c.google.com (mail-ot1-x32c.google.com [IPv6:2607:f8b0:4864:20::32c]) by sourceware.org (Postfix) with ESMTPS id 79D34385DDE3 for ; Tue, 27 Aug 2024 00:37:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 79D34385DDE3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 79D34385DDE3 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::32c ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719068; cv=none; b=wxRfwVVfvF1pdRruGPYhXr8CaXAzVbI8ArYQsRI7zRpQjs54eZtsoQc8YySZDyKfC/svMHBBXO4jWZ8a+dFTornpf0CheExMLcBPJ5K3zcOQuR44zyBUzezUu6L2ygcvmltboR8HAXlyGwBm5DEViP8DQ8F/nXzQW/Ote860qLA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719068; c=relaxed/simple; bh=nj3RcGg1vrfVS8Ak+iTU8SmAqC3i5hJx20g07nTSTNA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Kd5l8fjB1wz/x8LtBaq3hDgVOjqYv0Y6fZEyHEZ+sDPUnj+pYy/MrmfwuKQ0cJeXdOv7e8Z8kU2hUuBu3ONaqH6+D5c6kojN7nkVqXHZHDOjXu1jsZ13TvNwzPFjPBeMY3zxwkgAFqZZwPTJPVG5BoxVaacDKXgLuHZBpjrI/7M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x32c.google.com with SMTP id 46e09a7af769-70e00cb1ee7so3589912a34.1 for ; Mon, 26 Aug 2024 17:37:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719064; x=1725323864; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J6adLVnktY8X2vztQ6ZcAQi5KDpyuNV6ORscGEyTArc=; b=ADtVAdmk856WpTcBNbUrThxmtcWGD6wNoIV6abCBuiOjRfTqjrdxQy1oIiulrFTR3h cwixLkYAQ4RN5ighbdwHTF1hmKHjK4n4KQ/Dh0z7bNoEUUDnrWbZFOyeEOlfe08BvL+T b/8I15MWbB1yNcDd9ewFllyNAAupPnJsrc1q8E8ao8VBBPPaXvJDsnj/X8i3OZzzY/o1 cfdmWUyQ1VzDVlDenvcWIn0UnpqzHboSUsHdgQwhtWCC5RHMy7vhlUbVSiram8shxKOq EhTShY9i19b+w3PuDOA0YzzqWP8zEqhrIycvDmWFqJbfGGgaAaUeE932pjM1maK1wxfB YVRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719064; x=1725323864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J6adLVnktY8X2vztQ6ZcAQi5KDpyuNV6ORscGEyTArc=; b=J2EbVRw68ut0ejhoXUUUit28BunSLuYIgAamAZASVSZdlVB5a+ChfoJy2QXKDoufBD tntzYiuGlu1ffWktSi9v92y7iHLxktDkPUUpmz6mFWqaPopN/MLElA2gMIlB0OTNA9/8 ppt3p+5tcpqyZVxTNEoCmFFBXlQYngmV1fBnXsv1L5CmqW8uyqILq1j9JDZpSJSmGsoL vIqT/ooeOKNWhznJPhxfPZwjIL+/5CLJY6OiHHENNnAH01ybLB9Xe+4/PC0E987EvF1B fbPPf4gSJNnBFlMsFOIdksn/G/Rx01C+97hvhVVvxYRiCM+6xTtk/nQ5gj7We0Lt/E2m rpHQ== X-Gm-Message-State: AOJu0YxTg0rV6TDhEo/eQeIjoP8lBewJo1BlAEJEB+OGUVNcAMJ9j1FF fUNxppiWmekQcqgmMawI+rKWTKFCv8TZdrNUvVWIAftLg2rlvPyM3e2A/OGiSDvHe5ICjgpOAip v X-Google-Smtp-Source: AGHT+IGj6V+4PCg/beBacf1bfDvghcMHAbcS3mJ3q0Xbh+2v5TWf4fbP6+I7yp6IXAkQ5fATr7CMIw== X-Received: by 2002:a05:6808:ec1:b0:3da:a0a5:a26a with SMTP id 5614622812f47-3de2a86ef63mr13986284b6e.20.1724719064225; Mon, 26 Aug 2024 17:37:44 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:43 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 4/9] RISC-V: Emit costs for bool and stepped const vectors Date: Mon, 26 Aug 2024 17:36:58 -0700 Message-ID: <20240827003710.1513605-5-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org These cases are handled in the expander (riscv-v.cc:expand_const_vector). We need the vector builder to detect these cases so extract that out into a new riscv-v.h header file. gcc/ChangeLog: * config/riscv/riscv-v.cc (class rvv_builder): Move to riscv-v.h. * config/riscv/riscv.cc (riscv_const_insns): Emit placeholder costs for bool/stepped const vectors. * config/riscv/riscv-v.h: New file. Signed-off-by: Patrick O'Neill --- Ack'd here: https://inbox.sourceware.org/gcc-patches/cd634c30-caf0-4375-a623-d9cd8649803d@gmail.com/ --- gcc/config/riscv/riscv-v.cc | 53 +--------------------- gcc/config/riscv/riscv-v.h | 88 +++++++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 42 ++++++++++++++++++ 3 files changed, 131 insertions(+), 52 deletions(-) create mode 100644 gcc/config/riscv/riscv-v.h -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index aea4b9b872b..897b31c069e 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -51,6 +51,7 @@ #include "targhooks.h" #include "predict.h" #include "errors.h" +#include "riscv-v.h" using namespace riscv_vector; @@ -436,58 +437,6 @@ emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) e.emit_insn ((enum insn_code) icode, ops); } -class rvv_builder : public rtx_vector_builder -{ -public: - rvv_builder () : rtx_vector_builder () {} - rvv_builder (machine_mode mode, unsigned int npatterns, - unsigned int nelts_per_pattern) - : rtx_vector_builder (mode, npatterns, nelts_per_pattern) - { - m_inner_mode = GET_MODE_INNER (mode); - m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode); - m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode); - m_mask_mode = get_mask_mode (mode); - - gcc_assert ( - int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode)); - m_int_mode - = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require (); - } - - bool can_duplicate_repeating_sequence_p (); - bool is_repeating_sequence (); - rtx get_merged_repeating_sequence (); - - bool repeating_sequence_use_merge_profitable_p (); - bool combine_sequence_use_slideup_profitable_p (); - bool combine_sequence_use_merge_profitable_p (); - rtx get_merge_scalar_mask (unsigned int, machine_mode) const; - - bool single_step_npatterns_p () const; - bool npatterns_all_equal_p () const; - bool interleaved_stepped_npatterns_p () const; - bool npatterns_vid_diff_repeated_p () const; - - machine_mode new_mode () const { return m_new_mode; } - scalar_mode inner_mode () const { return m_inner_mode; } - scalar_int_mode inner_int_mode () const { return m_inner_int_mode; } - machine_mode mask_mode () const { return m_mask_mode; } - machine_mode int_mode () const { return m_int_mode; } - unsigned int inner_bits_size () const { return m_inner_bits_size; } - unsigned int inner_bytes_size () const { return m_inner_bytes_size; } - -private: - scalar_mode m_inner_mode; - scalar_int_mode m_inner_int_mode; - machine_mode m_new_mode; - scalar_int_mode m_new_inner_mode; - machine_mode m_mask_mode; - machine_mode m_int_mode; - unsigned int m_inner_bits_size; - unsigned int m_inner_bytes_size; -}; - /* Return true if the vector duplicated by a super element which is the fusion of consecutive elements. diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h new file mode 100644 index 00000000000..4635b5415c7 --- /dev/null +++ b/gcc/config/riscv/riscv-v.h @@ -0,0 +1,88 @@ +/* Subroutines used for code generation for RISC-V 'V' Extension for + GNU compiler. + Copyright (C) 2022-2024 Free Software Foundation, Inc. + Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_RISCV_V_H +#define GCC_RISCV_V_H + +#include "rtx-vector-builder.h" + +using namespace riscv_vector; + +namespace riscv_vector { + +extern machine_mode get_mask_mode (machine_mode); +extern opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); + +class rvv_builder : public rtx_vector_builder +{ +public: + rvv_builder () : rtx_vector_builder () {} + rvv_builder (machine_mode mode, unsigned int npatterns, + unsigned int nelts_per_pattern) + : rtx_vector_builder (mode, npatterns, nelts_per_pattern) + { + m_inner_mode = GET_MODE_INNER (mode); + m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode); + m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode); + m_mask_mode = get_mask_mode (mode); + + gcc_assert ( + int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode)); + m_int_mode + = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require (); + } + + bool can_duplicate_repeating_sequence_p (); + bool is_repeating_sequence (); + rtx get_merged_repeating_sequence (); + + bool repeating_sequence_use_merge_profitable_p (); + bool combine_sequence_use_slideup_profitable_p (); + bool combine_sequence_use_merge_profitable_p (); + rtx get_merge_scalar_mask (unsigned int, machine_mode) const; + + bool single_step_npatterns_p () const; + bool npatterns_all_equal_p () const; + bool interleaved_stepped_npatterns_p () const; + bool npatterns_vid_diff_repeated_p () const; + + machine_mode new_mode () const { return m_new_mode; } + scalar_mode inner_mode () const { return m_inner_mode; } + scalar_int_mode inner_int_mode () const { return m_inner_int_mode; } + machine_mode mask_mode () const { return m_mask_mode; } + machine_mode int_mode () const { return m_int_mode; } + unsigned int inner_bits_size () const { return m_inner_bits_size; } + unsigned int inner_bytes_size () const { return m_inner_bytes_size; } + +private: + scalar_mode m_inner_mode; + scalar_int_mode m_inner_int_mode; + machine_mode m_new_mode; + scalar_int_mode m_new_inner_mode; + machine_mode m_mask_mode; + machine_mode m_int_mode; + unsigned int m_inner_bits_size; + unsigned int m_inner_bytes_size; +}; + +} // namespace riscv_vector + +#endif // GCC_RISCV_V_H diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 640394e0cb8..e2718c9eb6e 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -75,6 +75,7 @@ along with GCC; see the file COPYING3. If not see #include "gcse.h" #include "tree-dfa.h" #include "target-globals.h" +#include "riscv-v.h" /* This file should be included last. */ #include "target-def.h" @@ -2145,6 +2146,10 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) rtx elt; if (const_vec_duplicate_p (x, &elt)) { + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_BOOL) + /* Duplicate values of 0/1 can be emitted using vmv.v.i. */ + return 1; + /* We don't allow CONST_VECTOR for DI vector on RV32 system since the ELT constant value can not held within a single register to disable reload a DI @@ -2186,6 +2191,43 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) accurately according to BASE && STEP. */ return 1; } + + if (CONST_VECTOR_STEPPED_P (x)) + { + /* Some cases are unhandled so we need construct a builder to + detect/allow those cases to be handled by the fallthrough + handler. */ + unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (x); + unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); + rvv_builder builder (GET_MODE(x), npatterns, nelts_per_pattern); + for (unsigned int i = 0; i < nelts_per_pattern; i++) + { + for (unsigned int j = 0; j < npatterns; j++) + builder.quick_push (CONST_VECTOR_ELT (x, i * npatterns + j)); + } + builder.finalize (); + + if (builder.single_step_npatterns_p ()) + { + if (builder.npatterns_all_equal_p ()) + { + /* TODO: This cost is not accurate. */ + return 1; + } + else + { + /* TODO: This cost is not accurate. */ + return 1; + } + } + else if (builder.interleaved_stepped_npatterns_p ()) + { + /* TODO: This cost is not accurate. */ + return 1; + } + + /* Fallthrough. */ + } } /* TODO: We may support more const vector in the future. */ From patchwork Tue Aug 27 00:36:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977066 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=leaLMXzd; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7yZ3Dmzz1yXd for ; Tue, 27 Aug 2024 10:41:26 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30BE0385EC32 for ; Tue, 27 Aug 2024 00:41:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by sourceware.org (Postfix) with ESMTPS id 5DA97385DDD9 for ; Tue, 27 Aug 2024 00:37:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5DA97385DDD9 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5DA97385DDD9 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::432 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719069; cv=none; b=XGxCV+irybABx1k1MyaeLB8rWHYILw2UtaBELJA/djBxXs/7JBBvmtwC8p5A5YlMBsSz8LiopEHboRoi/2zhF27HR+pJg79F+epVANZbh+e4JTg6kWfxnvg2q+xsxAK3GfWE7jfMeibNtXGL91Klo1+VAzKhgtqr0V3KO7WVI6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719069; c=relaxed/simple; bh=wFh46venEh/jNKCX8aipTFQ42kmQJcO3yCosPKnTpos=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ssDs5GtVmsRfiH/unrQHVO9TNYrT8V6R0SVairltRabE6bqeMqu8DnyktGi8PXFTqbZ687/ToGVbSpOKtHCAetnqvxk295HOYyQpuhjuokmxr3u+4qyXknQQJZjPA9jJXJz/FiOqStKLoem1muEZrBxg+LjlEEPlVk9VcqSfRek= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-7142a30e3bdso4416420b3a.0 for ; Mon, 26 Aug 2024 17:37:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719066; x=1725323866; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=87cYP4xTLfsiD3MicSO7tP8M/aYsXP2Za92mCemQngY=; b=leaLMXzdPHJ79PS8e5CyJCQDEJ42N5AbYfMXUUL44tSGIbbFWJ5syMlY0HiZ6vZ2fE bsp0g9MLxTkcsiRDHxAMIbstiZyFWhRNvxz1P0gFpc8RGYTwWJ2MqtjIDWMl0m4aXUe/ gZT6ellM8kfU/STsQF4nI+I9P92Nynsk+FZ+taKkNK/vBjuprmYIuKrtICzV4a/eN0JQ Y7kzht+rPPn45gL3973SEtWfBlX6pUeCQTwXq1CFtSMbKtM3Cw2cJg/WRyfsJ8PIjJPv 0r/LwXjZqhNoTqO5I9D9zugrNJqIyU5R437+lLKAvakHJ8sh9LLXUHkdquwtUXhqhL7F trvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719066; x=1725323866; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=87cYP4xTLfsiD3MicSO7tP8M/aYsXP2Za92mCemQngY=; b=FBS2om5+Qn5hwdu2biKF/NPkODueTHXHl5Ssa53cOpX8qA/TuHEEyGnGnN+R5J/2QZ rozY60XtcPit0s9oRGQ22fYkOUforjbde5cCIKLJr9V54tZTUod+t2ROs0BY+l8ToywX bDLaqwKb5gD6niORtPj7wLO51OS1S+A+uVSf9Mw2NbMMBEj/Ix6xhglw65JJmYgutGQ3 cr+XTvMaCJMbKgGUY5yF1KymGEQfrkJys+cjNAL+Qv8Zupj0xd0UkrQP+KJUgT+395AV pwZlOv6J+GdyBU32QmUvKRo8WThRu8mJpJJ2TYAF5bnCpWQHupFC7PI1S9luVvCnFfHE PF8Q== X-Gm-Message-State: AOJu0YwtyMXJPUdTfGs38fG2lxRfUKtcLN37Q0aMwrGKaqCGcuBYUgnf Au8iypepAVKxa5XjKkRA4kJPplAjKFxUY0TJnSdrZEuaPVtYKh4HUy3Ih/FkRyszdawCbeMI4Gv I X-Google-Smtp-Source: AGHT+IE/bDLF35isblTSaYz/cQVywwv7Bs55CzhFi6GxbkGazwmksQRqM8/5tSXBn6zoQvOolUyyoQ== X-Received: by 2002:a05:6a21:6da3:b0:1c4:6bcc:12c9 with SMTP id adf61e73a8af0-1ccc0379b22mr2064764637.20.1724719065452; Mon, 26 Aug 2024 17:37:45 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:45 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 5/9] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander Date: Mon, 26 Aug 2024 17:36:59 -0700 Message-ID: <20240827003710.1513605-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The comment previously here stated that the Wc0/Wc1 cases are handled by the vi constraint but that is not true for the 0.0 Wc0 case. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point case. Signed-off-by: Patrick O'Neill --- Ack'd here: https://inbox.sourceware.org/gcc-patches/D3MQFLKXZ4CQ.3GAKRYQYOPMW@gmail.com/ --- gcc/config/riscv/riscv-v.cc | 11 ++++++++++- gcc/config/riscv/riscv-v.h | 2 ++ gcc/config/riscv/riscv.cc | 8 +++----- 3 files changed, 15 insertions(+), 6 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 897b31c069e..32349677dc2 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -794,6 +794,15 @@ const_vec_all_in_range_p (rtx vec, poly_int64 minval, poly_int64 maxval) return true; } +/* Returns true if the vector's elements are all duplicates in + range -16 ~ 15 integer or 0.0 floating-point. */ + +bool +valid_vec_immediate_p (rtx x) +{ + return (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x)); +} + /* Return a const vector of VAL. The VAL can be either const_int or const_poly_int. */ @@ -1119,7 +1128,7 @@ expand_const_vector (rtx target, rtx src) { /* Element in range -16 ~ 15 integer or 0.0 floating-point, we use vmv.v.i instruction. */ - if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) + if (valid_vec_immediate_p (src)) { rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops); diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h index 4635b5415c7..e7b095f094e 100644 --- a/gcc/config/riscv/riscv-v.h +++ b/gcc/config/riscv/riscv-v.h @@ -83,6 +83,8 @@ private: unsigned int m_inner_bytes_size; }; +extern bool valid_vec_immediate_p(rtx); + } // namespace riscv_vector #endif // GCC_RISCV_V_H diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e2718c9eb6e..400b1059666 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2158,11 +2158,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) && !immediate_operand (elt, Pmode)) return 0; - /* Constants from -16 to 15 can be loaded with vmv.v.i. - The Wc0, Wc1 constraints are already covered by the - vi constraint so we do not need to check them here - separately. */ - if (satisfies_constraint_vi (x)) + /* Constants in range -16 ~ 15 integer or 0.0 floating-point + can be emitted using vmv.v.i. */ + if (valid_vec_immediate_p (x)) return 1; /* Any int/FP constants can always be broadcast from a From patchwork Tue Aug 27 00:37:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=H1EWQU0/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7vh45rdz1yYl for ; Tue, 27 Aug 2024 10:38:56 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 61E2A385EC36 for ; Tue, 27 Aug 2024 00:38:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by sourceware.org (Postfix) with ESMTPS id 6B643385E45F for ; Tue, 27 Aug 2024 00:37:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6B643385E45F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6B643385E45F Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::431 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719073; cv=none; b=XzCMN8ilRA/f74CSf46ucdhv+Od0y48vBy6mz0YsTT7kBwxCQ7GfzWXU8lEQYmdpguZrihRBxa7vnRiPPysIKpYFOY7DxGJU6ndv5l3Z+khZSnyIbJpPx+mYfh3EY9l44oCWYMHlHAKnQJBeNhe2oeLn47FDkxr8z2OxBAgQP+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719073; c=relaxed/simple; bh=gYu2acDmF3bgloeV6rVtqstMAi2vXfWIV98sOXiBJ+E=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=bpt9qFFnKPk/8MQd1ftaFwo0eB4r2aCaW9RAtQVo0D6TWmKM02yozNLQkJM/BsiXNfrZ2TBy10JMx6r7VEtsamdSNaqFqBKilyp3o5ZWxnprFmvM/1ui/xHhTctXFK7OdBIlWkCWyRMMOSPFlPHa4LCoXC+XHYNLLdFm5eWte0A= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-714187df604so3417707b3a.1 for ; Mon, 26 Aug 2024 17:37:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719067; x=1725323867; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lwgNEUTkqizSlYS7D5iiQRDhOc8i88A77pcdukyava4=; b=H1EWQU0/KPreWylVTCcPfcrPHxSJlLDORgY40ktgcWkuuMAuXI+JvdoqsW5VmWWshy Bwve5SkBUsN5HR/g66/vC/e+1Hru9W7T7502hjZ38fySK/dVbB44sJ7Q+cHHxl8RdB8t HxrsQ9cVnZAjCA5knAm+Runs3LQzVX1Vn9DVorW/S29bEhg7afY2umz7YU7q4PlWNtqe K5S4NwX991HdFCQkq2qF0GkBqRJFEHBFj1bAJOmI6CfEL/7DZgq0zcm+1HMtIcvW6Z/g Y1u3CNnHARM9C1iLaadkHiS9010TrWYlreAi2DtRsoCM42OpDpM+yhC94cM5un6zQtB5 jHpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719067; x=1725323867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lwgNEUTkqizSlYS7D5iiQRDhOc8i88A77pcdukyava4=; b=Hp9xS+VTiYR+MNmCx2IbgnW1IU7E+dlLQlNGcN+XqDLi0RBs05txlyhG+iZud6I0Xl KDSNnG9XYsfnqcV1MOwTiU6/0UOzceW55wrpcerTDJ5r7xfArJHcG6BOx8fRVgEJ4UMh d/dehbG9fCSblVW6xy2Aydp6bzvwBuPkMpcMVbRyBxwm4ovY6nNrWDtLhkeXFRd0xF0R h+MC0qpRcy6mGwPkd5znQF5sKMZZtjl+w+GamH1SdDNu2chTxaRZ2Cm5yA5KtiK88wE3 KTRnDhWpCdgwowlRoMsExnqAAzEsSvDDgOVqEV256vJLdT2ofOltAiTtNG3j/4CzK6gx hTUw== X-Gm-Message-State: AOJu0YzU0RDIemk8VKE+/daRXwhp/0RlTXlC0WMfqMr1mYSRpWk+bxHg LIslgSVzmNmQbq/2kpnJ65P2M3VKxLZ4KYxGQUVKJrTfTKl//GbHtbQ95fjf4b+b8e3s+DbXjxU d X-Google-Smtp-Source: AGHT+IEWgy9/ad8TP0GMyPi0vt5pNLvPr6JTjJOpYxyXM9bHI3KkJC9nsZjFjtU7owWaKAGZT5O2Aw== X-Received: by 2002:a05:6a20:4324:b0:1c6:8c89:88c9 with SMTP id adf61e73a8af0-1ccc0379b08mr1927245637.18.1724719066679; Mon, 26 Aug 2024 17:37:46 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:46 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 6/9] RISC-V: Allow non-duplicate bool patterns in expand_const_vector Date: Mon, 26 Aug 2024 17:37:00 -0700 Message-ID: <20240827003710.1513605-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Currently we assert when encountering a non-duplicate boolean vector. This patch allows non-duplicate vectors to fall through to the gcc_unreachable and assert there. This will be useful when adding a catch-all pattern to emit costs and handle arbitary vectors. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Allow non-duplicate to fall through other patterns before asserting. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 32349677dc2..cb2380ad664 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1109,26 +1109,19 @@ expand_const_vector (rtx target, rtx src) { machine_mode mode = GET_MODE (target); rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode); - if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) - { - rtx elt; - gcc_assert ( - const_vec_duplicate_p (src, &elt) - && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[] = {result, src}; - emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops); - - if (result != target) - emit_move_insn (target, result); - return; - } - rtx elt; if (const_vec_duplicate_p (src, &elt)) { + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + { + gcc_assert (rtx_equal_p (elt, const0_rtx) + || rtx_equal_p (elt, const1_rtx)); + rtx ops[] = {result, src}; + emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops); + } /* Element in range -16 ~ 15 integer or 0.0 floating-point, we use vmv.v.i instruction. */ - if (valid_vec_immediate_p (src)) + else if (valid_vec_immediate_p (src)) { rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops); From patchwork Tue Aug 27 00:37:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=SS0cbEqM; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7z06fjfz1yXd for ; Tue, 27 Aug 2024 10:41:48 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 22572385DDF2 for ; Tue, 27 Aug 2024 00:41:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by sourceware.org (Postfix) with ESMTPS id 441E0385E027 for ; Tue, 27 Aug 2024 00:37:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 441E0385E027 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 441E0385E027 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::32a ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719073; cv=none; b=XUs8wcfFwilLnnkEwp5YRvxpSqqeWU8sqeP0qXRV5DZQ0EetTfrf8lo8k3/Y8dhEpJ0cURgkPHzmVfc3CatG5625VvRw690UkybUOzH5+E8NX3ODQx3njE00aknik3VWsdBqj3kkMEwxwYCP4XCFjyLmYa9UZcj+GGVSOqSACB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719073; c=relaxed/simple; bh=X96EtzIc+9SVA1BrNZ9cIOnYOAsmqi6lto4kSKKG3lY=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=lG45ivM41dgeJA5VBFyYCFEKwon49COoQ9Yx4IVhyn6+SXGDNikopjYWhCrwSQPMeAMOdAF6Fcwli3hfVFE6anl+QMMh01zbReBA5s2DUtfUMXuHeLDW9J58Di7+wY2mggGYl+dX4ha87EhDS5S5uby+vOp0XtNYuFCElqL1A2s= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-7093b53f315so3183197a34.2 for ; Mon, 26 Aug 2024 17:37:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719068; x=1725323868; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y2TI9D81GJY3BaRPvBheqtP571NlycIZgmgav0jcjqs=; b=SS0cbEqM7o4Rlc5rN0pbC5Z/CvHrU3XWS1niQaTi3OhD9vPsqFBFdEKulfEqrpjyfC z6GBXUtbKum9maPUJ9H+2AYzuZrFXpnYOAXP0D7j6goF0chW1wcLi+9Wcuiv2lBR2vyB oHdTnPAFMpqVdldLIG+5vzKnj9ZxeJeEVsczCX/WKsjlTQ2inzksTdJDhSzUbIWZTQr7 XNe3kHKCGdPHJQudFh6mcrLhPydSxhcGoQM2fefPlpuUQUyn8P6S9r9B/fPvR9lOxD99 Bbv4VaS/5qEqj8w8iNEhDdyocHgBu60n3TfqbQTkjIioLK5nRO6r09/UcYcSGOoo2Z4D rxvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719068; x=1725323868; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y2TI9D81GJY3BaRPvBheqtP571NlycIZgmgav0jcjqs=; b=XYsmQRgFDS4jgPWgeflZOhj8X3nXRvU95Cl5xWcD5ARZB/KxZTMl+qIXD2a6mqMbeN Po0THDsot7KGaEkwy44sFMbjalWRzATfccmIzw/72o7Eoo+DbH8X1Xo4LlARsmfDLkIF JerF/iuf8MBbJ33R5/NypYLskCMDpzwYBiQDbx3J55EXAu5fKwTbTnUuhIXEEhzZPYBI tadqtBXjnt9Jcw660E/zQXAKiH9FGKH1dlcQx40j7YB9r+1Y+G+65rBbpbFOLPxdwJir ZrvYvx6dJmehwjHPUxiy8uNvowU3jlJoDlctgSkIssxbubEGR1buTjhyDS2rwgz8Uhyz dqTg== X-Gm-Message-State: AOJu0Yy2PBiISU0LMg2sHII4yxMK+ry935t7ppo9ObhQY+5lUdFFGPKk 5lB0f7rsv9V+v1sY3vT6kcPnsH9uiOoegqL9sdUrIDradFgFtbyEFOEL4k52C4C4TbkeaBGeyVN u X-Google-Smtp-Source: AGHT+IFP9S6xeUtedpnzE1zWE/aY0TuROb0ewGYnrjFAR4vjx6ed2zdP349YeL8i9kFTRrsgkD9yiA== X-Received: by 2002:a05:6808:2118:b0:3db:27e6:8be5 with SMTP id 5614622812f47-3de2a8ec2damr15534747b6e.42.1724719067995; Mon, 26 Aug 2024 17:37:47 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:47 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 7/9] RISC-V: Move helper functions above expand_const_vector Date: Mon, 26 Aug 2024 17:37:01 -0700 Message-ID: <20240827003710.1513605-8-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org These subroutines will be used in expand_const_vector in a future patch. Relocate so expand_const_vector can use them. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vector_init_insert_elems): Relocate. (expand_vector_init_trailing_same_elem): Ditto. Signed-off-by: Patrick O'Neill --- Ack'd here: https://inbox.sourceware.org/gcc-patches/0a08cbce-1568-4197-8df3-33966e440870@gmail.com/ --- gcc/config/riscv/riscv-v.cc | 132 ++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 66 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index cb2380ad664..9b6c3a21e2d 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1104,6 +1104,72 @@ expand_vec_series (rtx dest, rtx base, rtx step, rtx vid) emit_move_insn (dest, result); } +/* Subroutine of riscv_vector_expand_vector_init. + Works as follows: + (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER. + (b) Skip leading elements from BUILDER, which are the same as + element NELTS_REQD - 1. + (c) Insert earlier elements in reverse order in TARGET using vslide1down. */ + +static void +expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, + int nelts_reqd) +{ + machine_mode mode = GET_MODE (target); + rtx dup = expand_vector_broadcast (mode, builder.elt (0)); + emit_move_insn (target, dup); + int ndups = builder.count_dups (0, nelts_reqd - 1, 1); + for (int i = ndups; i < nelts_reqd; i++) + { + unsigned int unspec + = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN; + insn_code icode = code_for_pred_slide (unspec, mode); + rtx ops[] = {target, target, builder.elt (i)}; + emit_vlmax_insn (icode, BINARY_OP, ops); + } +} + +/* Subroutine of expand_vec_init to handle case + when all trailing elements of builder are same. + This works as follows: + (a) Use expand_insn interface to broadcast last vector element in TARGET. + (b) Insert remaining elements in TARGET using insr. + + ??? The heuristic used is to do above if number of same trailing elements + is greater than leading_ndups, loosely based on + heuristic from mostly_zeros_p. May need fine-tuning. */ + +static bool +expand_vector_init_trailing_same_elem (rtx target, + const rtx_vector_builder &builder, + int nelts_reqd) +{ + int leading_ndups = builder.count_dups (0, nelts_reqd - 1, 1); + int trailing_ndups = builder.count_dups (nelts_reqd - 1, -1, -1); + machine_mode mode = GET_MODE (target); + + if (trailing_ndups > leading_ndups) + { + rtx dup = expand_vector_broadcast (mode, builder.elt (nelts_reqd - 1)); + for (int i = nelts_reqd - trailing_ndups - 1; i >= 0; i--) + { + unsigned int unspec + = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1UP : UNSPEC_VSLIDE1UP; + insn_code icode = code_for_pred_slide (unspec, mode); + rtx tmp = gen_reg_rtx (mode); + rtx ops[] = {tmp, dup, builder.elt (i)}; + emit_vlmax_insn (icode, BINARY_OP, ops); + /* slide1up need source and dest to be different REG. */ + dup = tmp; + } + + emit_move_insn (target, dup); + return true; + } + + return false; +} + static void expand_const_vector (rtx target, rtx src) { @@ -2338,31 +2404,6 @@ preferred_simd_mode (scalar_mode mode) return word_mode; } -/* Subroutine of riscv_vector_expand_vector_init. - Works as follows: - (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER. - (b) Skip leading elements from BUILDER, which are the same as - element NELTS_REQD - 1. - (c) Insert earlier elements in reverse order in TARGET using vslide1down. */ - -static void -expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, - int nelts_reqd) -{ - machine_mode mode = GET_MODE (target); - rtx dup = expand_vector_broadcast (mode, builder.elt (0)); - emit_move_insn (target, dup); - int ndups = builder.count_dups (0, nelts_reqd - 1, 1); - for (int i = ndups; i < nelts_reqd; i++) - { - unsigned int unspec - = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN; - insn_code icode = code_for_pred_slide (unspec, mode); - rtx ops[] = {target, target, builder.elt (i)}; - emit_vlmax_insn (icode, BINARY_OP, ops); - } -} - /* Use merge approach to initialize the vector with repeating sequence. v = {a, b, a, b, a, b, a, b}. @@ -2487,47 +2528,6 @@ expand_vector_init_merge_combine_sequence (rtx target, emit_vlmax_insn (icode, MERGE_OP, merge_ops); } -/* Subroutine of expand_vec_init to handle case - when all trailing elements of builder are same. - This works as follows: - (a) Use expand_insn interface to broadcast last vector element in TARGET. - (b) Insert remaining elements in TARGET using insr. - - ??? The heuristic used is to do above if number of same trailing elements - is greater than leading_ndups, loosely based on - heuristic from mostly_zeros_p. May need fine-tuning. */ - -static bool -expand_vector_init_trailing_same_elem (rtx target, - const rtx_vector_builder &builder, - int nelts_reqd) -{ - int leading_ndups = builder.count_dups (0, nelts_reqd - 1, 1); - int trailing_ndups = builder.count_dups (nelts_reqd - 1, -1, -1); - machine_mode mode = GET_MODE (target); - - if (trailing_ndups > leading_ndups) - { - rtx dup = expand_vector_broadcast (mode, builder.elt (nelts_reqd - 1)); - for (int i = nelts_reqd - trailing_ndups - 1; i >= 0; i--) - { - unsigned int unspec - = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1UP : UNSPEC_VSLIDE1UP; - insn_code icode = code_for_pred_slide (unspec, mode); - rtx tmp = gen_reg_rtx (mode); - rtx ops[] = {tmp, dup, builder.elt (i)}; - emit_vlmax_insn (icode, BINARY_OP, ops); - /* slide1up need source and dest to be different REG. */ - dup = tmp; - } - - emit_move_insn (target, dup); - return true; - } - - return false; -} - /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */ void From patchwork Tue Aug 27 00:37:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=j09dluit; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7vw6KfHz1yYl for ; Tue, 27 Aug 2024 10:39:08 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B0DE4385EC23 for ; Tue, 27 Aug 2024 00:39:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by sourceware.org (Postfix) with ESMTPS id 9EFC5385DDEF for ; Tue, 27 Aug 2024 00:37:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9EFC5385DDEF Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9EFC5385DDEF Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::32b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719074; cv=none; b=ahdHwfO+X87veJsEMzB0m8OS0ahrclUQ2sSuc29WkvDptrX/r/s+v9ePvm2zoA4oOZDUi/+uewcr93xwF69y3ghA6sBUKZH4g+SNAQKALO5ZG9rXsx3JdmZsLf3RyapZFysJOCcYynDmSb2BSW7GHX5MDYsBKBdpZPJyl/btkfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719074; c=relaxed/simple; bh=dMfbfEeBEIUuiTw9MoMEB91YJ4/LC6HrRYUwNfbmPbA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=MrpLHIwKHGWh0rdcfkMlyQSWF/HWz5AXZr9zO2paiwJge9kKxL+KSB+kcoDkEjKAk1JXCU3ICUwFr/tpjD5FJpmR81iu0oQ2z4HSSAglvwyac+PR0qRrY8gzGAnce8JchLNOKIlm9BwjhhmIpihsq8Ytv/3I7PnhN4J0U2d7jLI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-70942ebcc29so4552123a34.0 for ; Mon, 26 Aug 2024 17:37:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719069; x=1725323869; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rAxgNBpnU4PSAFDGXU7EHDFUw8IYf3ObPNz3Q9mtsDc=; b=j09dluithEMPiopcD6QuY0yPLHVebqT5xkXmgdodIGLHNogq4lIYjuzdp0H+kDYey5 jVvS7XHQ0NBEb6ZIrvU/Os43eCzXTVHGn1DbiJVq92/1DWwR9VbEIXetvwdqWDjZToyx dn0o6KQRCAqZ/oGWKTkB8AtpKYOfzhS8tkulA0KnrMRthXEJ7FIZfkabRX8KHgHM439J rs+2jzMKJfmo5yWI7x8Rn2XNABm9aa0z+l5T8mk1Dn0zkr3rvWQk1AaoKmRF6ptop5F+ 59v1H7t9h0hiRNYvCj5EhAkDl2IL4N4RqWyDTxjfgeLhEDmsVgb4bt2zW3I98hWXX686 euNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719069; x=1725323869; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rAxgNBpnU4PSAFDGXU7EHDFUw8IYf3ObPNz3Q9mtsDc=; b=ckW0jX37EUEJEOG3oY/1W2+R3MeNGasXgRgAdWfLaED4yA2qwYfOIybQzpMSVrpN29 lZwAUGOINAbyUwT9zlcZJ4XSO+mZskJxgh+jyt596A2POmKkePXcatYGj+99uTvjgJTJ wBn19cPf9QiQupUfQM2+hBAqVJfWUIvlBMjt/XBqFK5oagLLsBjl+IeXx0PZnVUnhxSj K8/Va5GdOw3RrhlH4AW9l6HFdYhcGzXMF7/0/SJfdTsKEnQnR04+VYEiHxpHQgg6P3Np 0qNkGqODz63VrAEfmbHf7EKagq6OvkgcRdFKLfQvPbRuc139sxBHBHLDC50fAzdUVicd qiag== X-Gm-Message-State: AOJu0YwhM/hEwo4EykK9w1XpvYRV4Ge2VdKaGwaaqk3cwaCGvOIZyjh3 Ut+YKkWIIfj1bvjopgfS8IpKR66jOJ9BQKdoalG+eLmcbTqaJexMWcgPCqzio1eowqiRwP85y57 i X-Google-Smtp-Source: AGHT+IFX5JHqAC0XwYfnOZ3iZD+Md81pvRBCQLojtF1Z5aM8UOOkJth+C+slfX93EbgAE/AFoOW92w== X-Received: by 2002:a05:6830:6f47:b0:703:68e5:725b with SMTP id 46e09a7af769-70e0ebd06c8mr13847992a34.24.1724719069407; Mon, 26 Aug 2024 17:37:49 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:48 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 8/9] RISC-V: Add vslide1up/down pattern to expand_const_vector Date: Mon, 26 Aug 2024 17:37:02 -0700 Message-ID: <20240827003710.1513605-9-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Also explicitly disallow CONST_VECTOR_DUPLICATE_P for now. CONST_VECTOR_DUPLICATE_P was previously disallowed implicitly. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vec_series): Update comment. (expand_vector_init_insert_elems): Ditto. (expand_const_vector): Add catch-all pattern. * config/riscv/riscv.cc (riscv_const_insns): Add costing for catch-all pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/materialize-1.c: New test. * gcc.target/riscv/rvv/autovec/materialize-2.c: New test. * gcc.target/riscv/rvv/autovec/materialize-3.c: New test. * gcc.target/riscv/rvv/autovec/materialize-4.c: New test. * gcc.target/riscv/rvv/autovec/materialize-5.c: New test. * gcc.target/riscv/rvv/autovec/materialize-6.c: New test. Signed-off-by: Patrick O'Neill --- This causes 4 new regressions on glibc rv64gcv: Appears to be spilling due to the increased register pressure from materializing constants for vslide1down: FAIL: gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c scan-assembler-not jr FAIL: gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c scan-assembler-not sp Caused due to vle32/64 being replaced with splat & vslide1down: FAIL: gcc.target/riscv/rvv/autovec/vls/init-5.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times vle32\\.v 7 FAIL: gcc.target/riscv/rvv/autovec/vls/init-7.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times vle64\\.v 7 I'm not sure if it's profitable to replace a lmul8 load with 127 vslide1down.vx ops but we're being honest with the middle end when returning the # of insns we'll be emitting when costing... --- gcc/config/riscv/riscv-v.cc | 24 +++- gcc/config/riscv/riscv.cc | 108 ++++++++++++++++-- .../riscv/rvv/autovec/materialize-1.c | 13 +++ .../riscv/rvv/autovec/materialize-2.c | 13 +++ .../riscv/rvv/autovec/materialize-3.c | 13 +++ .../riscv/rvv/autovec/materialize-4.c | 13 +++ .../riscv/rvv/autovec/materialize-5.c | 13 +++ .../riscv/rvv/autovec/materialize-6.c | 13 +++ 8 files changed, 199 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 9b6c3a21e2d..a31766f3662 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1104,7 +1104,7 @@ expand_vec_series (rtx dest, rtx base, rtx step, rtx vid) emit_move_insn (dest, result); } -/* Subroutine of riscv_vector_expand_vector_init. +/* Subroutine of riscv_vector_expand_vector_init and expand_const_vector. Works as follows: (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER. (b) Skip leading elements from BUILDER, which are the same as @@ -1129,7 +1129,7 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, } } -/* Subroutine of expand_vec_init to handle case +/* Subroutine of expand_vec_init and expand_const_vector to handle case when all trailing elements of builder are same. This works as follows: (a) Use expand_insn interface to broadcast last vector element in TARGET. @@ -1248,6 +1248,8 @@ expand_const_vector (rtx target, rtx src) } builder.finalize (); + bool emit_catch_all_pattern = false; + if (CONST_VECTOR_DUPLICATE_P (src)) { /* Handle the case with repeating sequence that NELTS_PER_PATTERN = 1 @@ -1555,10 +1557,24 @@ expand_const_vector (rtx target, rtx src) } else /* TODO: We will enable more variable-length vector in the future. */ - gcc_unreachable (); + emit_catch_all_pattern = true; } else - gcc_unreachable (); + emit_catch_all_pattern = true; + + if (emit_catch_all_pattern) + { + int nelts = XVECLEN (src, 0); + + /* Optimize trailing same elements sequence: + v = {y, y2, y3, y4, y5, x, x, x, x, x, x, x, x, x, x, x}; */ + if (!expand_vector_init_trailing_same_elem (result, builder, nelts)) + /* Handle common situation with vslide1down. This function can handle + any case of vec_init. Only the cases that are not optimized + above will fall through here. This prevents us from dumping + to/reading from the stack to initialize vectors. */ + expand_vector_init_insert_elems (result, builder, nelts); + } if (result != target) emit_move_insn (target, result); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 400b1059666..ac7fdbf71af 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2141,12 +2141,13 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) out range of [-16, 15]. - 3. const series vector. ...etc. */ - if (riscv_v_ext_mode_p (GET_MODE (x))) + machine_mode mode = GET_MODE (x); + if (riscv_v_ext_mode_p (mode)) { rtx elt; if (const_vec_duplicate_p (x, &elt)) { - if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_BOOL) + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) /* Duplicate values of 0/1 can be emitted using vmv.v.i. */ return 1; @@ -2154,7 +2155,7 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) system since the ELT constant value can not held within a single register to disable reload a DI register vec_duplicate into vmv.v.x. */ - scalar_mode smode = GET_MODE_INNER (GET_MODE (x)); + scalar_mode smode = GET_MODE_INNER (mode); if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) && !immediate_operand (elt, Pmode)) return 0; @@ -2190,14 +2191,22 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) return 1; } - if (CONST_VECTOR_STEPPED_P (x)) + if (CONST_VECTOR_DUPLICATE_P (x)) + { + /* TODO: Cost cases of CONST_VECTOR_DUPLICATE_P. + We get ICEs with could not split insn from an + expand_vector_broadcast emitted during LRA when this op is + costed. For now disallow all cases. */ + return 0; + } + else if (CONST_VECTOR_STEPPED_P (x)) { /* Some cases are unhandled so we need construct a builder to detect/allow those cases to be handled by the fallthrough handler. */ unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (x); unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); - rvv_builder builder (GET_MODE(x), npatterns, nelts_per_pattern); + rvv_builder builder (mode, npatterns, nelts_per_pattern); for (unsigned int i = 0; i < nelts_per_pattern; i++) { for (unsigned int j = 0; j < npatterns; j++) @@ -2224,12 +2233,97 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) return 1; } - /* Fallthrough. */ + /* Fallthrough to catch all pattern. */ + } + + int nelts = const_vector_encoded_nelts (x); + if (nelts == 0) + return 0; + + /* Most arbitrary vectors can be constructed with a splat and + vslide1up/down. */ + + /* The arbitrary vector's elements must be supported by the + vslide1up/down operation. */ + scalar_mode smode = GET_MODE_INNER (mode); + if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)) + /* vslide1up/down does not handle elts larger than a register. */ + return 0; + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + /* vslide1up/down does not handle BImode elts. */ + return 0; + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + && maybe_lt (GET_MODE_SIZE (smode), 4)) + /* Our vslide1up/down insn def does not handle HF. */ + return 0; + + /* We already checked for a fully const vector above. Calculate + the number of leading/trailing elements covered by the splat. */ + int leading_ndups = 1; + rtx first_elt = CONST_VECTOR_ENCODED_ELT (x, 0); + for (int i = 1; i < nelts; i++) + { + if (first_elt == CONST_VECTOR_ENCODED_ELT (x, i)) + leading_ndups += 1; + else + break; + } + int trailing_ndups = 1; + if (leading_ndups >= nelts / 2) + /* We already know leading_ndups >= trailing_ndups so just use + leading ndups. */ + trailing_ndups = 0; + else + { + rtx last_elt = CONST_VECTOR_ENCODED_ELT (x, nelts - 1); + for (int i = nelts - 2; i > 0; i--) + { + if (last_elt == CONST_VECTOR_ENCODED_ELT (x, i)) + trailing_ndups += 1; + else + break; + } } + + /* We always splat the leading/trailing elt with the most contigious + duplicates. */ + int splatted_leading = 0; + int splatted_trailing = 0; + int splat_materialize = 0; + if (leading_ndups > trailing_ndups) + { + splatted_leading = leading_ndups; + splat_materialize = riscv_const_insns (CONST_VECTOR_ELT (x, 0), + allow_new_pseudos); + } + else + { + splatted_trailing = trailing_ndups; + splat_materialize = + riscv_const_insns (CONST_VECTOR_ELT (x, nelts - 1), + allow_new_pseudos); + } + + /* Splat leading/trailing elt. */ + int total_insns = splat_materialize + 1; + + /* TODO: There's room for improvement here. eg. duplicate + constants won't require another materialization. */ + for (int i = splatted_leading; i < nelts - splatted_trailing; i++) + { + rtx elt = CONST_VECTOR_ELT (x, i); + int n = riscv_const_insns (elt, allow_new_pseudos); + if (n == 0) + n = 4; /* memory access. */ + /* materialize + vslide1{up|down}. */ + total_insns += n + 1; + } + + return total_insns; } /* TODO: We may support more const vector in the future. */ - return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; + return x == CONST0_RTX (mode) ? 1 : 0; } case CONST: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c new file mode 100644 index 00000000000..2d7e1cf1556 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1up. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[4] = {1, 10, 10, 10}; + for (int j = 0; j < 4; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1up.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c new file mode 100644 index 00000000000..22d8365814c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1up. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[8] = {1, 1, 1, 10, 10, 10, 10, 10}; + for (int j = 0; j < 8; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1up.vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c new file mode 100644 index 00000000000..928e3d5fc74 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1down. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[4] = {1, 1, 1, 10}; + for (int j = 0; j < 4; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1down.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c new file mode 100644 index 00000000000..ba1b880e901 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1down. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[8] = {1, 1, 1, 1, 1, 10, 10, 10}; + for (int j = 0; j < 8; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1down.vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c new file mode 100644 index 00000000000..6fd68ec4a55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c @@ -0,0 +1,13 @@ +/* Arbitrary vector constants can be constructed using splat + vslide1{up|down}. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -O3" } */ + +void slide1down_arbitrary(int a, int *b) { + int c[4] = {100, 12, 324, 1}; + for (int j = 0; j < 4; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.x} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1(up|down).vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c new file mode 100644 index 00000000000..0de98bf26b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c @@ -0,0 +1,13 @@ +/* Arbitrary vector constants can be constructed using splat + vslide1{up|down}. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +void slide1down_arbitrary(int a, int *b) { + int c[8] = {100, 12, 324, 1, 57, 16, 98, 60}; + for (int j = 0; j < 8; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.x} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1(up|down).vx} 7 } } */ From patchwork Tue Aug 27 00:37:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1977065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=dqTpMDSa; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wt7xR6Hl6z1yXd for ; Tue, 27 Aug 2024 10:40:27 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 502283858C56 for ; Tue, 27 Aug 2024 00:40:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-il1-x12d.google.com (mail-il1-x12d.google.com [IPv6:2607:f8b0:4864:20::12d]) by sourceware.org (Postfix) with ESMTPS id 67A603858C52 for ; Tue, 27 Aug 2024 00:37:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 67A603858C52 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 67A603858C52 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::12d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719079; cv=none; b=bcU/eR9thfzEmDa7a5xhNwoIMiBq5LUg6UPgVC4BRT6cdNb+hRO39xzek9UHNR7y9IJ1ZSt8iocjDB5TaI2PzJuUqGFH5XXq07Mv9BSmcPK7QVKHk4ZxMLb0cevjLMAt/5tpBHorzKUtuxbR6sh5FquuVDaRuqbHlYVbD8DRyPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724719079; c=relaxed/simple; bh=R/BXOG6mB89sovmhJTWdHh6JsHiDA4PrlYhob1w6uAU=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=NLFbkXQRDGaFJUKRTzPEVERmJqNyW6cFlunvLVGBPxi+/3Y3zTPDGxgGYdlDh76hYbJxAeh3C7VYLVdaaxGiLvx8PgGBli/lwusxLPC4l89xTIhz618/iIh3Uchoc/cTCt4oRANHTD7B8FHWGTRgimumOuioUrzzcQ5hRtLTm20= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-il1-x12d.google.com with SMTP id e9e14a558f8ab-39d2cea1239so18366635ab.3 for ; Mon, 26 Aug 2024 17:37:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1724719071; x=1725323871; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KOg3ahfXvEPc6R9rNK2eqHdFkYlfOUSX80+7xqZORJM=; b=dqTpMDSayOVRe2ORkipfwfx+28xTs+0nezxSBLLetUlTSWZzMP/dE3r3jNXUCBCnZ6 1XZj9y5/TlPl7JSv5BWLoj4pJNfLrdrJ4PTwvx69y0LQkvl/e/KPoIScePjT5jakoiDy zs/uAsbtpgbEZYaWy2Bkhk+2OdbZ5cMVqGSGuDTUAIdVfL6ldRE9HCupACs+EVm5hXWX ibM5agTnQJn2pfTc/vtaIOJ5vAoNR5WLJ0G0dyqa+850vLboVtn5XG35ijHxBOp9+rsT xxIaNZe0T6jze0MMmW2IWh7WnBXZnzrspedEEsDULJx+AxTuPq/ypnD2j2zSeR5gzwTQ Kp4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724719071; x=1725323871; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KOg3ahfXvEPc6R9rNK2eqHdFkYlfOUSX80+7xqZORJM=; b=uGmxOLzKwgGhfhKZqIXcr1B2kQMMWIgpFuQUAH1Y0SwjnJrRYek/+sBLVaOcZ02OJP FQqmGzqVgag+t7EQdgaiqeaVbHzMF7vyvGSZv4G0mzXoiEr6iS4IF1AaIDo0Whqnukhf 5nbwo/vYu34VayVOZFvbfg0aE6ZuwTkInHGe7rvNG1Afx7mF6O1aefJYhcu9KwT3n351 BJPOHeUPIWDgL9VcndFuXv5zS6oCHtJgUgkG/RitHK1CrwXUEnpyqsC2RK62j+TcndGU u1cuT9appMFU8irY9d+XM06lMp59o48IWGkzTBhFl+nEToHM2FUQ+SLmsbUMt8CZKvuM BIiQ== X-Gm-Message-State: AOJu0YxsvEBmFnkEAxe4gEvHFO12APL5Hr5NR4NAHGS0gjGr0HawcmPw ayv1geWtc2YRC9fG1NW6tbpNWElLcKvNAn+xT+09WyYAB0CJbPVu6nQi/YLGT5ULl365j7UdiY6 X X-Google-Smtp-Source: AGHT+IFmlBq2+reQPZOp1Nb/X3rT5LBImimn9sTtec1VfDnHvXcI9pUO9IMrOY/o3Heb084FQQdhYQ== X-Received: by 2002:a92:c569:0:b0:39d:47cf:2c7f with SMTP id e9e14a558f8ab-39e3c9e9965mr135580385ab.24.1724719070635; Mon, 26 Aug 2024 17:37:50 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7cd9ac982dasm6941173a12.17.2024.08.26.17.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 17:37:50 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH v2 9/9] RISC-V: Add cost model asserts Date: Mon, 26 Aug 2024 17:37:03 -0700 Message-ID: <20240827003710.1513605-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240827003710.1513605-1-patrick@rivosinc.com> References: <20240827003710.1513605-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds some advanced checking to assert that the emitted costs match emitted patterns for const_vecs. Flow: Costing: Insert into hashmap> Expand: Check for membership in hashmap -> Not in hashmap: ignore, this wasn't costed -> In hashmap: Iterate over vec -> if RTX not in hashmap: Ignore, this wasn't costed (hash collision) -> if RTX in hashmap: Assert enum is expected There are no false positive asserts with this flow. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Add RTL_CHECKING gated asserts. * config/riscv/riscv.cc (riscv_const_insns): Ditto. * config/riscv/riscv-v.h (insert_expected_pattern): Add helper function to insert hash collisions into hash map vec key. (get_expected_costed_type): Add helper function to get the expected cost type for a given rtx pattern. Signed-off-by: Patrick O'Neill --- Was rfc: https://inbox.sourceware.org/gcc-patches/054f4f37-9615-4e01-940e-0cf4d188fcdb@gmail.com/T/#t While I think it's extremely valuable I'd be open to dropping it if there's strong opposition to it. I'm not sure how often people run with checking enabled but this seems likely to bitrot if the answer is not often. Maybe a sign to set up some weekly rtl-checking postcommit runs? With this patch (without the ifdefs) the riscv rv64gcv testsuite on a 32 core machine took: 36689.15s user 7398.57s system 2751% cpu 26:42.05 total max memory: 844 MB Without this patch: 35510.99s user 7157.93s system 2772% cpu 25:39.21 total max memory: 844 MB The hash map is never explicitly freed by GCC. --- gcc/config/riscv/riscv-v.cc | 47 +++++++++++++++++++++++++ gcc/config/riscv/riscv-v.h | 68 +++++++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 45 ++++++++++++++++++++++-- 3 files changed, 157 insertions(+), 3 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a31766f3662..3236ff728a6 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1173,6 +1173,12 @@ expand_vector_init_trailing_same_elem (rtx target, static void expand_const_vector (rtx target, rtx src) { +#ifdef ENABLE_RTL_CHECKING + riscv_const_expect_p* expected_pattern = NULL; + if (EXPECTED_CONST_PATTERN) + expected_pattern = get_expected_costed_type (EXPECTED_CONST_PATTERN, src); +#endif + machine_mode mode = GET_MODE (target); rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode); rtx elt; @@ -1180,6 +1186,10 @@ expand_const_vector (rtx target, rtx src) { if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) { +#ifdef ENABLE_RTL_CHECKING + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_DUPLICATE_BOOL); +#endif gcc_assert (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx)); rtx ops[] = {result, src}; @@ -1189,11 +1199,20 @@ expand_const_vector (rtx target, rtx src) we use vmv.v.i instruction. */ else if (valid_vec_immediate_p (src)) { +#ifdef ENABLE_RTL_CHECKING + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_DUPLICATE_VMV_VI); +#endif rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops); } else { +#ifdef ENABLE_RTL_CHECKING + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_DUPLICATE_INT_FP); +#endif + /* Emit vec_duplicate split pattern before RA so that we could have a better optimization opportunity in LICM which will hoist vmv.v.x outside the loop and in fwprop && combine @@ -1230,6 +1249,10 @@ expand_const_vector (rtx target, rtx src) rtx base, step; if (const_vec_series_p (src, &base, &step)) { +#ifdef ENABLE_RTL_CHECKING + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_SERIES); +#endif expand_vec_series (result, base, step); if (result != target) @@ -1323,6 +1346,10 @@ expand_const_vector (rtx target, rtx src) gcc_assert (GET_MODE_CLASS (mode) == MODE_VECTOR_INT); if (builder.single_step_npatterns_p ()) { +#ifdef ENABLE_RTL_CHECKING + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_PATTERN_SINGLE_STEP); +#endif /* Describe the case by choosing NPATTERNS = 4 as an example. */ insn_code icode; @@ -1462,6 +1489,10 @@ expand_const_vector (rtx target, rtx src) } else if (builder.interleaved_stepped_npatterns_p ()) { +#ifdef ENABLE_RTL_CHECKING + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_PATTERN_INTERLEAVED); +#endif rtx base1 = builder.elt (0); rtx base2 = builder.elt (1); poly_int64 step1 @@ -1564,6 +1595,13 @@ expand_const_vector (rtx target, rtx src) if (emit_catch_all_pattern) { +#ifdef ENABLE_RTL_CHECKING + /* Ensure the vector cost emitted by riscv_const_insns expected this + pattern to be handled by the catch all pattern. */ + if (expected_pattern) + gcc_assert (*expected_pattern == RVV_CATCH_ALL); +#endif + int nelts = XVECLEN (src, 0); /* Optimize trailing same elements sequence: @@ -1575,6 +1613,15 @@ expand_const_vector (rtx target, rtx src) to/reading from the stack to initialize vectors. */ expand_vector_init_insert_elems (result, builder, nelts); } + else + { +#ifdef ENABLE_RTL_CHECKING + /* Ensure the vector cost emitted by riscv_const_insns expected this + pattern to be handled by an optimized pattern. */ + if (expected_pattern) + gcc_assert (*expected_pattern != RVV_CATCH_ALL); +#endif + } if (result != target) emit_move_insn (target, result); diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h index e7b095f094e..0a28657d3ac 100644 --- a/gcc/config/riscv/riscv-v.h +++ b/gcc/config/riscv/riscv-v.h @@ -24,6 +24,74 @@ #include "rtx-vector-builder.h" +#ifdef ENABLE_RTL_CHECKING +#include "hash-map.h" + +typedef enum +{ + RVV_DUPLICATE_BOOL, + RVV_DUPLICATE_VMV_VI, + RVV_DUPLICATE_INT_FP, + RVV_SERIES, + RVV_PATTERN_SINGLE_STEP, + RVV_PATTERN_INTERLEAVED, + RVV_CATCH_ALL, +} riscv_const_expect_p; + +extern hash_map>> *EXPECTED_CONST_PATTERN; + +static bool insert_expected_pattern (hash_map>> *map, + rtx x, riscv_const_expect_p pattern) +{ + if (!map) + return false; + + vec>* expected_patterns = map->get (x); + + if (expected_patterns) + { + // We already have an entry for this hash + for (std::pair expected : *expected_patterns) + if (expected.first == x) + // Duplicate costing, ignore. + return true; + + expected_patterns->safe_push (std::make_pair(x, pattern)); + } + else + { + // Create a vec to hold the entry + vec> new_expected_patterns = vNULL; + new_expected_patterns.safe_push (std::make_pair(x, pattern)); + + // Update map's vec to non-null value + map->put (x, new_expected_patterns); + } + + return true; +} + +static riscv_const_expect_p* get_expected_costed_type(hash_map>> *map, + rtx x) +{ + if (!map) + return NULL; + + vec>* expected_patterns = map->get (x); + if (!expected_patterns) + return NULL; + + // Iterate over all hash collisions + for (std::pair expected : *expected_patterns) + { + if (expected.first == x) + return &expected.second; + } + + return NULL; +} +#endif /* ENABLE_RTL_CHECKING */ + using namespace riscv_vector; namespace riscv_vector { diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ac7fdbf71af..bc89913386d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -681,6 +681,12 @@ static const struct riscv_tune_info riscv_tune_info_table[] = { function. */ static bool riscv_save_frame_pointer; +#ifdef ENABLE_RTL_CHECKING +/* Global variable used in riscv-v.cc to ensure accurate costs are emitted + for constant vectors. */ +hash_map>> *EXPECTED_CONST_PATTERN = NULL; +#endif + typedef enum { PUSH_IDX = 0, @@ -2131,6 +2137,13 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; case CONST_VECTOR: { +#ifdef ENABLE_RTL_CHECKING + /* Used to assert we aren't mislabeling optimized/fallthrough + patterns and are emitting accurate costs. */ + if (!EXPECTED_CONST_PATTERN) + EXPECTED_CONST_PATTERN = new hash_map>>; +#endif + /* TODO: This is not accurate, we will need to adapt the COST of CONST_VECTOR in the future for the following cases: @@ -2148,8 +2161,13 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) if (const_vec_duplicate_p (x, &elt)) { if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) - /* Duplicate values of 0/1 can be emitted using vmv.v.i. */ - return 1; + { +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_DUPLICATE_BOOL); +#endif + /* Duplicate values of 0/1 can be emitted using vmv.v.i. */ + return 1; + } /* We don't allow CONST_VECTOR for DI vector on RV32 system since the ELT constant value can not held @@ -2162,13 +2180,21 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) /* Constants in range -16 ~ 15 integer or 0.0 floating-point can be emitted using vmv.v.i. */ if (valid_vec_immediate_p (x)) - return 1; + { +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_DUPLICATE_VMV_VI); +#endif + return 1; + } /* Any int/FP constants can always be broadcast from a scalar register. Loading of a floating-point constant incurs a literal-pool access. Allow this in order to increase vectorization possibilities. */ int n = riscv_const_insns (elt, allow_new_pseudos); +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_DUPLICATE_INT_FP); +#endif if (CONST_DOUBLE_P (elt)) return 1 + 4; /* vfmv.v.f + memory access. */ else @@ -2186,6 +2212,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) rtx base, step; if (const_vec_series_p (x, &base, &step)) { +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_SERIES); +#endif /* This cost is not accurate, we will need to adapt the COST accurately according to BASE && STEP. */ return 1; @@ -2216,6 +2245,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) if (builder.single_step_npatterns_p ()) { +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_PATTERN_SINGLE_STEP); +#endif if (builder.npatterns_all_equal_p ()) { /* TODO: This cost is not accurate. */ @@ -2229,6 +2261,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) } else if (builder.interleaved_stepped_npatterns_p ()) { +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_PATTERN_INTERLEAVED); +#endif /* TODO: This cost is not accurate. */ return 1; } @@ -2257,6 +2292,10 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) /* Our vslide1up/down insn def does not handle HF. */ return 0; +#ifdef ENABLE_RTL_CHECKING + insert_expected_pattern (EXPECTED_CONST_PATTERN, x, RVV_CATCH_ALL); +#endif + /* We already checked for a fully const vector above. Calculate the number of leading/trailing elements covered by the splat. */ int leading_ndups = 1;