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Thu, 22 Aug 2024 12:48:09 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-203855e1609sm16250925ad.160.2024.08.22.12.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 12:48:09 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 1/9] RISC-V: Use encoded nelts when calling repeating_sequence_p Date: Thu, 22 Aug 2024 12:46:24 -0700 Message-ID: <20240822194705.2789364-2-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org repeating_sequence_p operates directly on the encoded pattern and does not derive elements using the .elt() accessor. Passing in the length of the unencoded vector can cause an out-of-bounds read of the encoded pattern. gcc/ChangeLog: * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p): Use encoded_nelts when calling repeating_sequence_p. (rvv_builder::is_repeating_sequence): Ditto. (rvv_builder::repeating_sequence_use_merge_profitable_p): Ditto. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 0db5c7591ef..c89603669e3 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -502,9 +502,7 @@ rvv_builder::can_duplicate_repeating_sequence_p () || GET_MODE_SIZE (m_new_inner_mode) > UNITS_PER_WORD || !get_vector_mode (m_new_inner_mode, new_size).exists (&m_new_mode)) return false; - if (full_nelts ().is_constant ()) - return repeating_sequence_p (0, full_nelts ().to_constant (), npatterns ()); - return nelts_per_pattern () == 1; + return repeating_sequence_p (0, encoded_nelts (), npatterns ()); } /* Return true if the vector is a simple sequence with one pattern and all @@ -514,9 +512,7 @@ rvv_builder::is_repeating_sequence () { if (npatterns () > 1) return false; - if (full_nelts ().is_constant ()) - return repeating_sequence_p (0, full_nelts ().to_constant (), 1); - return nelts_per_pattern () == 1; + return repeating_sequence_p (0, encoded_nelts (), 1); } /* Return true if it is a repeating sequence that using @@ -564,7 +560,7 @@ rvv_builder::repeating_sequence_use_merge_profitable_p () unsigned int nelts = full_nelts ().to_constant (); - if (!repeating_sequence_p (0, nelts, npatterns ())) + if (!repeating_sequence_p (0, encoded_nelts (), npatterns ())) return false; unsigned int merge_cost = 1; From patchwork Thu Aug 22 19:46:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975730 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=O5U3jTd/; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Aug 2024 12:48:10 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 2/9] RISC-V: Fix vid const vector expander for non-npatterns size steps Date: Thu, 22 Aug 2024 12:46:25 -0700 Message-ID: <20240822194705.2789364-3-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Prior to this patch the expander would emit vectors like: { 0, 0, 5, 5, 10, 10, ...} as: { 0, 0, 2, 2, 4, 4, ...} This patch sets the step size to the requested value. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Fix STEP size in expander. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 48 ++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c89603669e3..a3039a2cb19 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1312,25 +1312,61 @@ expand_const_vector (rtx target, rtx src) /* Generate the variable-length vector following this rule: { a, a, a + step, a + step, a + step * 2, a + step * 2, ...} E.g. { 0, 0, 8, 8, 16, 16, ... } */ - /* We want to create a pattern where value[ix] = floor (ix / + + /* We want to create a pattern where value[idx] = floor (idx / NPATTERNS). As NPATTERNS is always a power of two we can - rewrite this as = ix & -NPATTERNS. */ + rewrite this as = idx & -NPATTERNS. */ /* Step 2: VID AND -NPATTERNS: { 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... } */ rtx imm = gen_int_mode (-builder.npatterns (), builder.inner_mode ()); - rtx tmp = gen_reg_rtx (builder.mode ()); - rtx and_ops[] = {tmp, vid, imm}; + rtx tmp1 = gen_reg_rtx (builder.mode ()); + rtx and_ops[] = {tmp1, vid, imm}; icode = code_for_pred_scalar (AND, builder.mode ()); emit_vlmax_insn (icode, BINARY_OP, and_ops); + + /* Step 3: Convert to step size 1. */ + rtx tmp2 = gen_reg_rtx (builder.mode ()); + /* log2 (npatterns) to get the shift amount to convert + Eg. { 0, 0, 0, 0, 4, 4, ... } + into { 0, 0, 0, 0, 1, 1, ... }. */ + HOST_WIDE_INT shift_amt = exact_log2 (builder.npatterns ()) ; + rtx shift = gen_int_mode (shift_amt, builder.inner_mode ()); + rtx shift_ops[] = {tmp2, tmp1, shift}; + icode = code_for_pred_scalar (ASHIFTRT, builder.mode ()); + emit_vlmax_insn (icode, BINARY_OP, shift_ops); + + /* Step 4: Multiply to step size n. */ + HOST_WIDE_INT step_size = + INTVAL (builder.elt (builder.npatterns ())) + - INTVAL (builder.elt (0)); + rtx tmp3 = gen_reg_rtx (builder.mode ()); + if (pow2p_hwi (step_size)) + { + /* Power of 2 can be handled with a left shift. */ + HOST_WIDE_INT shift = exact_log2 (step_size); + rtx shift_amount = gen_int_mode (shift, Pmode); + insn_code icode = code_for_pred_scalar (ASHIFT, mode); + rtx ops[] = {tmp3, tmp2, shift_amount}; + emit_vlmax_insn (icode, BINARY_OP, ops); + } + else + { + rtx mult_amt = gen_int_mode (step_size, builder.inner_mode ()); + insn_code icode = code_for_pred_scalar (MULT, builder.mode ()); + rtx ops[] = {tmp3, tmp2, mult_amt}; + emit_vlmax_insn (icode, BINARY_OP, ops); + } + + /* Step 5: Add starting value to all elements. */ HOST_WIDE_INT init_val = INTVAL (builder.elt (0)); if (init_val == 0) - emit_move_insn (target, tmp); + emit_move_insn (target, tmp3); else { rtx dup = gen_const_vector_dup (builder.mode (), init_val); - rtx add_ops[] = {target, tmp, dup}; + rtx add_ops[] = {target, tmp3, dup}; icode = code_for_pred (PLUS, builder.mode ()); emit_vlmax_insn (icode, BINARY_OP, add_ops); } From patchwork Thu Aug 22 19:46:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975732 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=QKqpsdM2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WqYfq2bb4z1yYZ for ; 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Thu, 22 Aug 2024 12:48:12 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-203855e1609sm16250925ad.160.2024.08.22.12.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 12:48:11 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 3/9] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander Date: Thu, 22 Aug 2024 12:46:26 -0700 Message-ID: <20240822194705.2789364-4-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The comment previously here stated that the Wc0/Wc1 cases are handled by the vi constraint but that is not true for the 0.0 Wc0 case. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Handle 0.0 floating-point case. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index c3877008d05..dc9e9280c8c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2162,11 +2162,9 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) && !immediate_operand (elt, Pmode)) return 0; - /* Constants from -16 to 15 can be loaded with vmv.v.i. - The Wc0, Wc1 constraints are already covered by the - vi constraint so we do not need to check them here - separately. */ - if (satisfies_constraint_vi (x)) + /* Constants in range -16 ~ 15 integer or 0.0 floating-point + can be emitted using vmv.v.i. */ + if (satisfies_constraint_vi (x) || satisfies_constraint_Wc0 (x)) return 1; /* Any int/FP constants can always be broadcast from a From patchwork Thu Aug 22 19:46:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975737 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Aug 2024 12:48:13 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 4/9] RISC-V: Reorder insn cost match order to match corresponding expander match order Date: Thu, 22 Aug 2024 12:46:27 -0700 Message-ID: <20240822194705.2789364-5-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The corresponding expander (riscv-v.cc:expand_const_vector) matches const_vec_duplicate_p before const_vec_series_p. Reorder to match this behavior when calculating costs. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Relocate. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index dc9e9280c8c..eb1c172d1ce 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2142,15 +2142,6 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) ...etc. */ if (riscv_v_ext_mode_p (GET_MODE (x))) { - /* const series vector. */ - rtx base, step; - if (const_vec_series_p (x, &base, &step)) - { - /* This is not accurate, we will need to adapt the COST - * accurately according to BASE && STEP. */ - return 1; - } - rtx elt; if (const_vec_duplicate_p (x, &elt)) { @@ -2184,6 +2175,15 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) return 1 + 4; /*vmv.v.x + memory access. */ } } + + /* const series vector. */ + rtx base, step; + if (const_vec_series_p (x, &base, &step)) + { + /* This cost is not accurate, we will need to adapt the COST + accurately according to BASE && STEP. */ + return 1; + } } /* TODO: We may support more const vector in the future. */ From patchwork Thu Aug 22 19:46:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975738 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=obK7yyYj; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WqYh52sXBz1yYZ for ; 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Thu, 22 Aug 2024 12:48:14 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-203855e1609sm16250925ad.160.2024.08.22.12.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 12:48:14 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 5/9] RISC-V: Handle case when constant vector construction target rtx is not a register Date: Thu, 22 Aug 2024 12:46:28 -0700 Message-ID: <20240822194705.2789364-6-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This manifests in RTL that is optimized away which causes runtime failures in the testsuite. Update all patterns to use a temp result register if required. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Use tmp register if needed. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 73 +++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 32 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a3039a2cb19..aea4b9b872b 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1150,26 +1150,29 @@ static void expand_const_vector (rtx target, rtx src) { machine_mode mode = GET_MODE (target); + rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode); if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) { rtx elt; gcc_assert ( const_vec_duplicate_p (src, &elt) && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[] = {target, src}; + rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops); + + if (result != target) + emit_move_insn (target, result); return; } rtx elt; if (const_vec_duplicate_p (src, &elt)) { - rtx tmp = register_operand (target, mode) ? target : gen_reg_rtx (mode); /* Element in range -16 ~ 15 integer or 0.0 floating-point, we use vmv.v.i instruction. */ if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) { - rtx ops[] = {tmp, src}; + rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops); } else @@ -1186,7 +1189,7 @@ expand_const_vector (rtx target, rtx src) instruction (vsetvl a5, zero). */ if (lra_in_progress) { - rtx ops[] = {tmp, elt}; + rtx ops[] = {result, elt}; emit_vlmax_insn (code_for_pred_broadcast (mode), UNARY_OP, ops); } else @@ -1194,15 +1197,15 @@ expand_const_vector (rtx target, rtx src) struct expand_operand ops[2]; enum insn_code icode = optab_handler (vec_duplicate_optab, mode); gcc_assert (icode != CODE_FOR_nothing); - create_output_operand (&ops[0], tmp, mode); + create_output_operand (&ops[0], result, mode); create_input_operand (&ops[1], elt, GET_MODE_INNER (mode)); expand_insn (icode, 2, ops); - tmp = ops[0].value; + result = ops[0].value; } } - if (tmp != target) - emit_move_insn (target, tmp); + if (result != target) + emit_move_insn (target, result); return; } @@ -1210,7 +1213,10 @@ expand_const_vector (rtx target, rtx src) rtx base, step; if (const_vec_series_p (src, &base, &step)) { - expand_vec_series (target, base, step); + expand_vec_series (result, base, step); + + if (result != target) + emit_move_insn (target, result); return; } @@ -1243,7 +1249,7 @@ expand_const_vector (rtx target, rtx src) all element equal to 0x0706050403020100. */ rtx ele = builder.get_merged_repeating_sequence (); rtx dup = expand_vector_broadcast (builder.new_mode (), ele); - emit_move_insn (target, gen_lowpart (mode, dup)); + emit_move_insn (result, gen_lowpart (mode, dup)); } else { @@ -1272,8 +1278,8 @@ expand_const_vector (rtx target, rtx src) emit_vlmax_insn (code_for_pred_scalar (AND, builder.int_mode ()), BINARY_OP, and_ops); - rtx tmp = gen_reg_rtx (builder.mode ()); - rtx dup_ops[] = {tmp, builder.elt (0)}; + rtx tmp1 = gen_reg_rtx (builder.mode ()); + rtx dup_ops[] = {tmp1, builder.elt (0)}; emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP, dup_ops); for (unsigned int i = 1; i < builder.npatterns (); i++) @@ -1285,12 +1291,12 @@ expand_const_vector (rtx target, rtx src) /* Merge scalar to each i. */ rtx tmp2 = gen_reg_rtx (builder.mode ()); - rtx merge_ops[] = {tmp2, tmp, builder.elt (i), mask}; + rtx merge_ops[] = {tmp2, tmp1, builder.elt (i), mask}; insn_code icode = code_for_pred_merge_scalar (builder.mode ()); emit_vlmax_insn (icode, MERGE_OP, merge_ops); - tmp = tmp2; + tmp1 = tmp2; } - emit_move_insn (target, tmp); + emit_move_insn (result, tmp1); } } else if (CONST_VECTOR_STEPPED_P (src)) @@ -1362,11 +1368,11 @@ expand_const_vector (rtx target, rtx src) /* Step 5: Add starting value to all elements. */ HOST_WIDE_INT init_val = INTVAL (builder.elt (0)); if (init_val == 0) - emit_move_insn (target, tmp3); + emit_move_insn (result, tmp3); else { rtx dup = gen_const_vector_dup (builder.mode (), init_val); - rtx add_ops[] = {target, tmp3, dup}; + rtx add_ops[] = {result, tmp3, dup}; icode = code_for_pred (PLUS, builder.mode ()); emit_vlmax_insn (icode, BINARY_OP, add_ops); } @@ -1396,7 +1402,7 @@ expand_const_vector (rtx target, rtx src) /* Step 2: Generate result = VID + diff. */ rtx vec = v.build (); - rtx add_ops[] = {target, vid, vec}; + rtx add_ops[] = {result, vid, vec}; emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), BINARY_OP, add_ops); } @@ -1412,24 +1418,24 @@ expand_const_vector (rtx target, rtx src) v.quick_push (builder.elt (i)); rtx new_base = v.build (); - /* Step 2: Generate tmp = VID >> LOG2 (NPATTERNS).  */ + /* Step 2: Generate tmp1 = VID >> LOG2 (NPATTERNS).  */ rtx shift_count = gen_int_mode (exact_log2 (builder.npatterns ()), builder.inner_mode ()); - rtx tmp = expand_simple_binop (builder.mode (), LSHIFTRT, + rtx tmp1 = expand_simple_binop (builder.mode (), LSHIFTRT, vid, shift_count, NULL_RTX, false, OPTAB_DIRECT); - /* Step 3: Generate tmp2 = tmp * step.  */ + /* Step 3: Generate tmp2 = tmp1 * step.  */ rtx tmp2 = gen_reg_rtx (builder.mode ()); rtx step = simplify_binary_operation (MINUS, builder.inner_mode (), builder.elt (v.npatterns()), builder.elt (0)); - expand_vec_series (tmp2, const0_rtx, step, tmp); + expand_vec_series (tmp2, const0_rtx, step, tmp1); - /* Step 4: Generate target = tmp2 + new_base.  */ - rtx add_ops[] = {target, tmp2, new_base}; + /* Step 4: Generate result = tmp2 + new_base.  */ + rtx add_ops[] = {result, tmp2, new_base}; emit_vlmax_insn (code_for_pred (PLUS, builder.mode ()), BINARY_OP, add_ops); } @@ -1462,13 +1468,13 @@ expand_const_vector (rtx target, rtx src) if (int_mode_for_size (new_smode_bitsize, 0).exists (&new_smode) && get_vector_mode (new_smode, new_nunits).exists (&new_mode)) { - rtx tmp = gen_reg_rtx (new_mode); + rtx tmp1 = gen_reg_rtx (new_mode); base1 = gen_int_mode (rtx_to_poly_int64 (base1), new_smode); - expand_vec_series (tmp, base1, gen_int_mode (step1, new_smode)); + expand_vec_series (tmp1, base1, gen_int_mode (step1, new_smode)); if (rtx_equal_p (base2, const0_rtx) && known_eq (step2, 0)) /* { 1, 0, 2, 0, ... }. */ - emit_move_insn (target, gen_lowpart (mode, tmp)); + emit_move_insn (result, gen_lowpart (mode, tmp1)); else if (known_eq (step2, 0)) { /* { 1, 1, 2, 1, ... }. */ @@ -1478,10 +1484,10 @@ expand_const_vector (rtx target, rtx src) gen_int_mode (builder.inner_bits_size (), new_smode), NULL_RTX, false, OPTAB_DIRECT); rtx tmp2 = gen_reg_rtx (new_mode); - rtx and_ops[] = {tmp2, tmp, scalar}; + rtx and_ops[] = {tmp2, tmp1, scalar}; emit_vlmax_insn (code_for_pred_scalar (AND, new_mode), BINARY_OP, and_ops); - emit_move_insn (target, gen_lowpart (mode, tmp2)); + emit_move_insn (result, gen_lowpart (mode, tmp2)); } else { @@ -1495,10 +1501,10 @@ expand_const_vector (rtx target, rtx src) gen_int_mode (builder.inner_bits_size (), Pmode), NULL_RTX, false, OPTAB_DIRECT); rtx tmp3 = gen_reg_rtx (new_mode); - rtx ior_ops[] = {tmp3, tmp, shifted_tmp2}; + rtx ior_ops[] = {tmp3, tmp1, shifted_tmp2}; emit_vlmax_insn (code_for_pred (IOR, new_mode), BINARY_OP, ior_ops); - emit_move_insn (target, gen_lowpart (mode, tmp3)); + emit_move_insn (result, gen_lowpart (mode, tmp3)); } } else @@ -1526,7 +1532,7 @@ expand_const_vector (rtx target, rtx src) rtx mask = gen_reg_rtx (builder.mask_mode ()); expand_vec_cmp (mask, EQ, and_vid, CONST1_RTX (mode)); - rtx ops[] = {target, tmp1, tmp2, mask}; + rtx ops[] = {result, tmp1, tmp2, mask}; emit_vlmax_insn (code_for_pred_merge (mode), MERGE_OP, ops); } } @@ -1536,6 +1542,9 @@ expand_const_vector (rtx target, rtx src) } else gcc_unreachable (); + + if (result != target) + emit_move_insn (target, result); } /* Get the frm mode with given CONST_INT rtx, the default mode is From patchwork Thu Aug 22 19:46:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975739 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=UKrjsWgf; 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Thu, 22 Aug 2024 12:48:15 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 6/9] RISC-V: Emit costs for bool and stepped const vectors Date: Thu, 22 Aug 2024 12:46:29 -0700 Message-ID: <20240822194705.2789364-7-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org These cases are handled in the expander (riscv-v.cc:expand_const_vector). We need the vector builder to detect these cases so extract that out into a new riscv-v.h header file. gcc/ChangeLog: * config/riscv/riscv-v.cc (class rvv_builder): Move to riscv-v.h. * config/riscv/riscv.cc (riscv_const_insns): Emit placeholder costs for bool/stepped const vectors. * config/riscv/riscv-v.h: New file. Signed-off-by: Patrick O'Neill Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 53 +--------------------- gcc/config/riscv/riscv-v.h | 88 +++++++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 42 ++++++++++++++++++ 3 files changed, 131 insertions(+), 52 deletions(-) create mode 100644 gcc/config/riscv/riscv-v.h diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index aea4b9b872b..897b31c069e 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -51,6 +51,7 @@ #include "targhooks.h" #include "predict.h" #include "errors.h" +#include "riscv-v.h" using namespace riscv_vector; @@ -436,58 +437,6 @@ emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) e.emit_insn ((enum insn_code) icode, ops); } -class rvv_builder : public rtx_vector_builder -{ -public: - rvv_builder () : rtx_vector_builder () {} - rvv_builder (machine_mode mode, unsigned int npatterns, - unsigned int nelts_per_pattern) - : rtx_vector_builder (mode, npatterns, nelts_per_pattern) - { - m_inner_mode = GET_MODE_INNER (mode); - m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode); - m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode); - m_mask_mode = get_mask_mode (mode); - - gcc_assert ( - int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode)); - m_int_mode - = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require (); - } - - bool can_duplicate_repeating_sequence_p (); - bool is_repeating_sequence (); - rtx get_merged_repeating_sequence (); - - bool repeating_sequence_use_merge_profitable_p (); - bool combine_sequence_use_slideup_profitable_p (); - bool combine_sequence_use_merge_profitable_p (); - rtx get_merge_scalar_mask (unsigned int, machine_mode) const; - - bool single_step_npatterns_p () const; - bool npatterns_all_equal_p () const; - bool interleaved_stepped_npatterns_p () const; - bool npatterns_vid_diff_repeated_p () const; - - machine_mode new_mode () const { return m_new_mode; } - scalar_mode inner_mode () const { return m_inner_mode; } - scalar_int_mode inner_int_mode () const { return m_inner_int_mode; } - machine_mode mask_mode () const { return m_mask_mode; } - machine_mode int_mode () const { return m_int_mode; } - unsigned int inner_bits_size () const { return m_inner_bits_size; } - unsigned int inner_bytes_size () const { return m_inner_bytes_size; } - -private: - scalar_mode m_inner_mode; - scalar_int_mode m_inner_int_mode; - machine_mode m_new_mode; - scalar_int_mode m_new_inner_mode; - machine_mode m_mask_mode; - machine_mode m_int_mode; - unsigned int m_inner_bits_size; - unsigned int m_inner_bytes_size; -}; - /* Return true if the vector duplicated by a super element which is the fusion of consecutive elements. diff --git a/gcc/config/riscv/riscv-v.h b/gcc/config/riscv/riscv-v.h new file mode 100644 index 00000000000..4635b5415c7 --- /dev/null +++ b/gcc/config/riscv/riscv-v.h @@ -0,0 +1,88 @@ +/* Subroutines used for code generation for RISC-V 'V' Extension for + GNU compiler. + Copyright (C) 2022-2024 Free Software Foundation, Inc. + Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_RISCV_V_H +#define GCC_RISCV_V_H + +#include "rtx-vector-builder.h" + +using namespace riscv_vector; + +namespace riscv_vector { + +extern machine_mode get_mask_mode (machine_mode); +extern opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); + +class rvv_builder : public rtx_vector_builder +{ +public: + rvv_builder () : rtx_vector_builder () {} + rvv_builder (machine_mode mode, unsigned int npatterns, + unsigned int nelts_per_pattern) + : rtx_vector_builder (mode, npatterns, nelts_per_pattern) + { + m_inner_mode = GET_MODE_INNER (mode); + m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode); + m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode); + m_mask_mode = get_mask_mode (mode); + + gcc_assert ( + int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode)); + m_int_mode + = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require (); + } + + bool can_duplicate_repeating_sequence_p (); + bool is_repeating_sequence (); + rtx get_merged_repeating_sequence (); + + bool repeating_sequence_use_merge_profitable_p (); + bool combine_sequence_use_slideup_profitable_p (); + bool combine_sequence_use_merge_profitable_p (); + rtx get_merge_scalar_mask (unsigned int, machine_mode) const; + + bool single_step_npatterns_p () const; + bool npatterns_all_equal_p () const; + bool interleaved_stepped_npatterns_p () const; + bool npatterns_vid_diff_repeated_p () const; + + machine_mode new_mode () const { return m_new_mode; } + scalar_mode inner_mode () const { return m_inner_mode; } + scalar_int_mode inner_int_mode () const { return m_inner_int_mode; } + machine_mode mask_mode () const { return m_mask_mode; } + machine_mode int_mode () const { return m_int_mode; } + unsigned int inner_bits_size () const { return m_inner_bits_size; } + unsigned int inner_bytes_size () const { return m_inner_bytes_size; } + +private: + scalar_mode m_inner_mode; + scalar_int_mode m_inner_int_mode; + machine_mode m_new_mode; + scalar_int_mode m_new_inner_mode; + machine_mode m_mask_mode; + machine_mode m_int_mode; + unsigned int m_inner_bits_size; + unsigned int m_inner_bytes_size; +}; + +} // namespace riscv_vector + +#endif // GCC_RISCV_V_H diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index eb1c172d1ce..a820cadd205 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -75,6 +75,7 @@ along with GCC; see the file COPYING3. If not see #include "gcse.h" #include "tree-dfa.h" #include "target-globals.h" +#include "riscv-v.h" /* This file should be included last. */ #include "target-def.h" @@ -2145,6 +2146,10 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) rtx elt; if (const_vec_duplicate_p (x, &elt)) { + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_BOOL) + /* Duplicate values of 0/1 can be emitted using vmv.v.i. */ + return 1; + /* We don't allow CONST_VECTOR for DI vector on RV32 system since the ELT constant value can not held within a single register to disable reload a DI @@ -2184,6 +2189,43 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) accurately according to BASE && STEP. */ return 1; } + + if (CONST_VECTOR_STEPPED_P (x)) + { + /* Some cases are unhandled so we need construct a builder to + detect/allow those cases to be handled by the fallthrough + handler. */ + unsigned int nelts_per_pattern = CONST_VECTOR_NELTS_PER_PATTERN (x); + unsigned int npatterns = CONST_VECTOR_NPATTERNS (x); + rvv_builder builder (mode, npatterns, nelts_per_pattern); + for (unsigned int i = 0; i < nelts_per_pattern; i++) + { + for (unsigned int j = 0; j < npatterns; j++) + builder.quick_push (CONST_VECTOR_ELT (x, i * npatterns + j)); + } + builder.finalize (); + + if (builder.single_step_npatterns_p ()) + { + if (builder.npatterns_all_equal_p ()) + { + /* TODO: This cost is not accurate. */ + return 1; + } + else + { + /* TODO: This cost is not accurate. */ + return 1; + } + } + else if (builder.interleaved_stepped_npatterns_p ()) + { + /* TODO: This cost is not accurate. */ + return 1; + } + + /* Fallthrough to catch all pattern. */ + } } /* TODO: We may support more const vector in the future. */ From patchwork Thu Aug 22 19:46:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975742 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Aug 2024 12:48:17 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 7/9] RISC-V: Allow non-duplicate bool patterns in expand_const_vector Date: Thu, 22 Aug 2024 12:46:30 -0700 Message-ID: <20240822194705.2789364-8-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Currently we assert when encountering a non-duplicate boolean vector. This patch allows non-duplicate vectors to fall through to the gcc_unreachable and assert there. This will be useful when adding a catch-all pattern to emit costs and handle arbitary vectors. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_const_vector): Allow non-duplicate to fall through other patterns before asserting. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 897b31c069e..8a5b154fc47 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1100,26 +1100,19 @@ expand_const_vector (rtx target, rtx src) { machine_mode mode = GET_MODE (target); rtx result = register_operand (target, mode) ? target : gen_reg_rtx (mode); - if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) - { - rtx elt; - gcc_assert ( - const_vec_duplicate_p (src, &elt) - && (rtx_equal_p (elt, const0_rtx) || rtx_equal_p (elt, const1_rtx))); - rtx ops[] = {result, src}; - emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops); - - if (result != target) - emit_move_insn (target, result); - return; - } - rtx elt; if (const_vec_duplicate_p (src, &elt)) { + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + { + gcc_assert (rtx_equal_p (elt, const0_rtx) + || rtx_equal_p (elt, const1_rtx)); + rtx ops[] = {result, src}; + emit_vlmax_insn (code_for_pred_mov (mode), UNARY_MASK_OP, ops); + } /* Element in range -16 ~ 15 integer or 0.0 floating-point, we use vmv.v.i instruction. */ - if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) + else if (satisfies_constraint_vi (src) || satisfies_constraint_Wc0 (src)) { rtx ops[] = {result, src}; emit_vlmax_insn (code_for_pred_mov (mode), UNARY_OP, ops); From patchwork Thu Aug 22 19:46:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=St4FNM8E; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Aug 2024 12:48:18 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 8/9] RISC-V: Move helper functions above expand_const_vector Date: Thu, 22 Aug 2024 12:46:31 -0700 Message-ID: <20240822194705.2789364-9-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org These subroutines will be used in expand_const_vector in a future patch. Relocate so expand_const_vector can use them. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vector_init_insert_elems): Relocate. (expand_vector_init_trailing_same_elem): Ditto. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/riscv-v.cc | 132 ++++++++++++++++++------------------ 1 file changed, 66 insertions(+), 66 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 8a5b154fc47..2b0dc57a021 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1095,6 +1095,72 @@ expand_vec_series (rtx dest, rtx base, rtx step, rtx vid) emit_move_insn (dest, result); } +/* Subroutine of riscv_vector_expand_vector_init. + Works as follows: + (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER. + (b) Skip leading elements from BUILDER, which are the same as + element NELTS_REQD - 1. + (c) Insert earlier elements in reverse order in TARGET using vslide1down. */ + +static void +expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, + int nelts_reqd) +{ + machine_mode mode = GET_MODE (target); + rtx dup = expand_vector_broadcast (mode, builder.elt (0)); + emit_move_insn (target, dup); + int ndups = builder.count_dups (0, nelts_reqd - 1, 1); + for (int i = ndups; i < nelts_reqd; i++) + { + unsigned int unspec + = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN; + insn_code icode = code_for_pred_slide (unspec, mode); + rtx ops[] = {target, target, builder.elt (i)}; + emit_vlmax_insn (icode, BINARY_OP, ops); + } +} + +/* Subroutine of expand_vec_init to handle case + when all trailing elements of builder are same. + This works as follows: + (a) Use expand_insn interface to broadcast last vector element in TARGET. + (b) Insert remaining elements in TARGET using insr. + + ??? The heuristic used is to do above if number of same trailing elements + is greater than leading_ndups, loosely based on + heuristic from mostly_zeros_p. May need fine-tuning. */ + +static bool +expand_vector_init_trailing_same_elem (rtx target, + const rtx_vector_builder &builder, + int nelts_reqd) +{ + int leading_ndups = builder.count_dups (0, nelts_reqd - 1, 1); + int trailing_ndups = builder.count_dups (nelts_reqd - 1, -1, -1); + machine_mode mode = GET_MODE (target); + + if (trailing_ndups > leading_ndups) + { + rtx dup = expand_vector_broadcast (mode, builder.elt (nelts_reqd - 1)); + for (int i = nelts_reqd - trailing_ndups - 1; i >= 0; i--) + { + unsigned int unspec + = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1UP : UNSPEC_VSLIDE1UP; + insn_code icode = code_for_pred_slide (unspec, mode); + rtx tmp = gen_reg_rtx (mode); + rtx ops[] = {tmp, dup, builder.elt (i)}; + emit_vlmax_insn (icode, BINARY_OP, ops); + /* slide1up need source and dest to be different REG. */ + dup = tmp; + } + + emit_move_insn (target, dup); + return true; + } + + return false; +} + static void expand_const_vector (rtx target, rtx src) { @@ -2329,31 +2395,6 @@ preferred_simd_mode (scalar_mode mode) return word_mode; } -/* Subroutine of riscv_vector_expand_vector_init. - Works as follows: - (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER. - (b) Skip leading elements from BUILDER, which are the same as - element NELTS_REQD - 1. - (c) Insert earlier elements in reverse order in TARGET using vslide1down. */ - -static void -expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, - int nelts_reqd) -{ - machine_mode mode = GET_MODE (target); - rtx dup = expand_vector_broadcast (mode, builder.elt (0)); - emit_move_insn (target, dup); - int ndups = builder.count_dups (0, nelts_reqd - 1, 1); - for (int i = ndups; i < nelts_reqd; i++) - { - unsigned int unspec - = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN; - insn_code icode = code_for_pred_slide (unspec, mode); - rtx ops[] = {target, target, builder.elt (i)}; - emit_vlmax_insn (icode, BINARY_OP, ops); - } -} - /* Use merge approach to initialize the vector with repeating sequence. v = {a, b, a, b, a, b, a, b}. @@ -2478,47 +2519,6 @@ expand_vector_init_merge_combine_sequence (rtx target, emit_vlmax_insn (icode, MERGE_OP, merge_ops); } -/* Subroutine of expand_vec_init to handle case - when all trailing elements of builder are same. - This works as follows: - (a) Use expand_insn interface to broadcast last vector element in TARGET. - (b) Insert remaining elements in TARGET using insr. - - ??? The heuristic used is to do above if number of same trailing elements - is greater than leading_ndups, loosely based on - heuristic from mostly_zeros_p. May need fine-tuning. */ - -static bool -expand_vector_init_trailing_same_elem (rtx target, - const rtx_vector_builder &builder, - int nelts_reqd) -{ - int leading_ndups = builder.count_dups (0, nelts_reqd - 1, 1); - int trailing_ndups = builder.count_dups (nelts_reqd - 1, -1, -1); - machine_mode mode = GET_MODE (target); - - if (trailing_ndups > leading_ndups) - { - rtx dup = expand_vector_broadcast (mode, builder.elt (nelts_reqd - 1)); - for (int i = nelts_reqd - trailing_ndups - 1; i >= 0; i--) - { - unsigned int unspec - = FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1UP : UNSPEC_VSLIDE1UP; - insn_code icode = code_for_pred_slide (unspec, mode); - rtx tmp = gen_reg_rtx (mode); - rtx ops[] = {tmp, dup, builder.elt (i)}; - emit_vlmax_insn (icode, BINARY_OP, ops); - /* slide1up need source and dest to be different REG. */ - dup = tmp; - } - - emit_move_insn (target, dup); - return true; - } - - return false; -} - /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */ void From patchwork Thu Aug 22 19:46:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 1975734 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.a=rsa-sha256 header.s=20230601 header.b=y9Mh1B++; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; 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Thu, 22 Aug 2024 12:48:19 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, gnu-toolchain@rivosinc.com, Patrick O'Neill Subject: [PATCH 9/9] RISC-V: Add vslide1up/down pattern to expand_const_vector Date: Thu, 22 Aug 2024 12:46:32 -0700 Message-ID: <20240822194705.2789364-10-patrick@rivosinc.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240822194705.2789364-1-patrick@rivosinc.com> References: <20240822194705.2789364-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Also explicitly disallow CONST_VECTOR_DUPLICATE_P for now. CONST_VECTOR_DUPLICATE_P was previously disallowed implicitly. gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vec_series): Update comment. (expand_vector_init_insert_elems): Ditto. (expand_const_vector): Add catch-all pattern. * config/riscv/riscv.cc (riscv_const_insns): Add costing for catch-all pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/materialize-1.c: New test. * gcc.target/riscv/rvv/autovec/materialize-2.c: New test. * gcc.target/riscv/rvv/autovec/materialize-3.c: New test. * gcc.target/riscv/rvv/autovec/materialize-4.c: New test. * gcc.target/riscv/rvv/autovec/materialize-5.c: New test. * gcc.target/riscv/rvv/autovec/materialize-6.c: New test. Signed-off-by: Patrick O'Neill Signed-off-by: Patrick O'Neill --- This causes 4 new regressions on glibc rv64gcv: Appears to be spilling due to the increased register pressure from materializing constants for vslide1down: FAIL: gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c scan-assembler-not jr FAIL: gcc.dg/vect/costmodel/riscv/rvv/pr113112-4.c scan-assembler-not sp Caused due to vle32/64 being replaced with splat & vslide1down: FAIL: gcc.target/riscv/rvv/autovec/vls/init-5.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times vle32\\.v 7 FAIL: gcc.target/riscv/rvv/autovec/vls/init-7.c -O3 -ftree-vectorize -mrvv-vector-bits=scalable scan-assembler-times vle64\\.v 7 I'm not sure if it's profitable to replace a lmul8 load with 127 vslide1down.vx ops but we're being honest with the middle end when returning the # of insns we'll be emitting when costing... --- gcc/config/riscv/riscv-v.cc | 24 +++- gcc/config/riscv/riscv.cc | 103 +++++++++++++++++- .../riscv/rvv/autovec/materialize-1.c | 13 +++ .../riscv/rvv/autovec/materialize-2.c | 13 +++ .../riscv/rvv/autovec/materialize-3.c | 13 +++ .../riscv/rvv/autovec/materialize-4.c | 13 +++ .../riscv/rvv/autovec/materialize-5.c | 13 +++ .../riscv/rvv/autovec/materialize-6.c | 13 +++ 8 files changed, 196 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c -- 2.34.1 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 2b0dc57a021..6ba4b6291bb 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1095,7 +1095,7 @@ expand_vec_series (rtx dest, rtx base, rtx step, rtx vid) emit_move_insn (dest, result); } -/* Subroutine of riscv_vector_expand_vector_init. +/* Subroutine of riscv_vector_expand_vector_init and expand_const_vector. Works as follows: (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER. (b) Skip leading elements from BUILDER, which are the same as @@ -1120,7 +1120,7 @@ expand_vector_init_insert_elems (rtx target, const rvv_builder &builder, } } -/* Subroutine of expand_vec_init to handle case +/* Subroutine of expand_vec_init and expand_const_vector to handle case when all trailing elements of builder are same. This works as follows: (a) Use expand_insn interface to broadcast last vector element in TARGET. @@ -1239,6 +1239,8 @@ expand_const_vector (rtx target, rtx src) } builder.finalize (); + bool emit_catch_all_pattern = false; + if (CONST_VECTOR_DUPLICATE_P (src)) { /* Handle the case with repeating sequence that NELTS_PER_PATTERN = 1 @@ -1546,10 +1548,24 @@ expand_const_vector (rtx target, rtx src) } else /* TODO: We will enable more variable-length vector in the future. */ - gcc_unreachable (); + emit_catch_all_pattern = true; } else - gcc_unreachable (); + emit_catch_all_pattern = true; + + if (emit_catch_all_pattern) + { + int nelts = XVECLEN (src, 0); + + /* Optimize trailing same elements sequence: + v = {y, y2, y3, y4, y5, x, x, x, x, x, x, x, x, x, x, x}; */ + if (!expand_vector_init_trailing_same_elem (result, builder, nelts)) + /* Handle common situation with vslide1down. This function can handle + any case of vec_init. Only the cases that are not optimized + above will fall through here. This prevents us from dumping + to/reading from the stack to initialize vectors. */ + expand_vector_init_insert_elems (result, builder, nelts); + } if (result != target) emit_move_insn (target, result); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index a820cadd205..d1b8c27f4ac 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2141,12 +2141,13 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) out range of [-16, 15]. - 3. const series vector. ...etc. */ - if (riscv_v_ext_mode_p (GET_MODE (x))) + machine_mode mode = GET_MODE (x); + if (riscv_v_ext_mode_p (mode)) { rtx elt; if (const_vec_duplicate_p (x, &elt)) { - if (GET_MODE_CLASS (GET_MODE (x)) == MODE_VECTOR_BOOL) + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) /* Duplicate values of 0/1 can be emitted using vmv.v.i. */ return 1; @@ -2154,7 +2155,7 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) system since the ELT constant value can not held within a single register to disable reload a DI register vec_duplicate into vmv.v.x. */ - scalar_mode smode = GET_MODE_INNER (GET_MODE (x)); + scalar_mode smode = GET_MODE_INNER (mode); if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) && !immediate_operand (elt, Pmode)) return 0; @@ -2190,7 +2191,15 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) return 1; } - if (CONST_VECTOR_STEPPED_P (x)) + if (CONST_VECTOR_DUPLICATE_P (x)) + { + /* TODO: Cost cases of CONST_VECTOR_DUPLICATE_P. + We get ICEs with could not split insn from an + expand_vector_broadcast emitted during LRA when this op is + costed. For now disallow all cases. */ + return 0; + } + else if (CONST_VECTOR_STEPPED_P (x)) { /* Some cases are unhandled so we need construct a builder to detect/allow those cases to be handled by the fallthrough @@ -2226,10 +2235,94 @@ riscv_const_insns (rtx x, bool allow_new_pseudos) /* Fallthrough to catch all pattern. */ } + int nelts = const_vector_encoded_nelts (x); + if (nelts == 0) + return 0; + + /* Most arbitrary vectors can be constructed with a splat and + vslide1up/down. */ + + /* The arbitrary vector's elements must be supported by the + vslide1up/down operation. */ + scalar_mode smode = GET_MODE_INNER (mode); + if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)) + /* vslide1up/down does not handle elts larger than a register. */ + return 0; + if (GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL) + /* vslide1up/down does not handle BImode elts. */ + return 0; + if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT + && maybe_lt (GET_MODE_SIZE (smode), 4)) + /* Our vslide1up/down insn def does not handle HF. */ + return 0; + + /* We already checked for a fully const vector above. Calculate + the number of leading/trailing elements covered by the splat. */ + int leading_ndups = 1; + rtx first_elt = CONST_VECTOR_ENCODED_ELT (x, 0); + for (int i = 1; i < nelts; i++) + { + if (first_elt == CONST_VECTOR_ENCODED_ELT (x, i)) + leading_ndups += 1; + else + break; + } + int trailing_ndups = 1; + if (leading_ndups >= nelts / 2) + /* We already know leading_ndups >= trailing_ndups so just use + leading ndups. */ + trailing_ndups = 0; + else + { + rtx last_elt = CONST_VECTOR_ENCODED_ELT (x, nelts - 1); + for (int i = nelts - 2; i > 0; i--) + { + if (last_elt == CONST_VECTOR_ENCODED_ELT (x, i)) + trailing_ndups += 1; + else + break; + } + } + + /* We always splat the leading/trailing elt with the most contigious + duplicates. */ + int splatted_leading = 0; + int splatted_trailing = 0; + int splat_materialize = 0; + if (leading_ndups > trailing_ndups) + { + splatted_leading = leading_ndups; + splat_materialize = riscv_const_insns (CONST_VECTOR_ELT (x, 0), + allow_new_pseudos); + } + else + { + splatted_trailing = trailing_ndups; + splat_materialize = + riscv_const_insns (CONST_VECTOR_ELT (x, nelts - 1), + allow_new_pseudos); + } + + /* Splat leading/trailing elt. */ + int total_insns = splat_materialize + 1; + + /* TODO: There's room for improvement here. eg. duplicate + constants won't require another materialization. */ + for (int i = splatted_leading; i < nelts - splatted_trailing; i++) + { + rtx elt = CONST_VECTOR_ELT (x, i); + int n = riscv_const_insns (elt, allow_new_pseudos); + if (n == 0) + n = 4; /* memory access. */ + /* materialize + vslide1{up|down}. */ + total_insns += n + 1; + } + + return total_insns; } /* TODO: We may support more const vector in the future. */ - return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; + return x == CONST0_RTX (mode) ? 1 : 0; } case CONST: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c new file mode 100644 index 00000000000..2d7e1cf1556 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-1.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1up. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[4] = {1, 10, 10, 10}; + for (int j = 0; j < 4; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1up.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c new file mode 100644 index 00000000000..22d8365814c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-2.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1up. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[8] = {1, 1, 1, 10, 10, 10, 10, 10}; + for (int j = 0; j < 8; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1up.vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c new file mode 100644 index 00000000000..928e3d5fc74 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-3.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1down. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[4] = {1, 1, 1, 10}; + for (int j = 0; j < 4; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1down.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c new file mode 100644 index 00000000000..ba1b880e901 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-4.c @@ -0,0 +1,13 @@ +/* Vector constants can be constructed using splat + vslide1down. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +void slide1up(int a, int *b) { + int c[8] = {1, 1, 1, 1, 1, 10, 10, 10}; + for (int j = 0; j < 8; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.i} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1down.vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c new file mode 100644 index 00000000000..6fd68ec4a55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-5.c @@ -0,0 +1,13 @@ +/* Arbitrary vector constants can be constructed using splat + vslide1{up|down}. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -O3" } */ + +void slide1down_arbitrary(int a, int *b) { + int c[4] = {100, 12, 324, 1}; + for (int j = 0; j < 4; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.x} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1(up|down).vx} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c new file mode 100644 index 00000000000..0de98bf26b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/materialize-6.c @@ -0,0 +1,13 @@ +/* Arbitrary vector constants can be constructed using splat + vslide1{up|down}. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -O3" } */ + +void slide1down_arbitrary(int a, int *b) { + int c[8] = {100, 12, 324, 1, 57, 16, 98, 60}; + for (int j = 0; j < 8; j++) { + b[j] = c[j]; + } +} + +/* { dg-final { scan-assembler-times {vmv.v.x} 1 } } */ +/* { dg-final { scan-assembler-times {vslide1(up|down).vx} 7 } } */