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Thu, 22 Aug 2024 06:22:20 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52CC120043; Thu, 22 Aug 2024 06:22:18 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1591720040; Thu, 22 Aug 2024 06:22:17 +0000 (GMT) Received: from genoa.aus.stglabs.ibm.com (unknown [9.40.192.157]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 22 Aug 2024 06:22:16 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V2] rs6000: add clober and guard for vsx_stxvd2x4_le_const[pr116030] Date: Thu, 22 Aug 2024 14:22:15 +0800 Message-Id: <20240822062215.1772705-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.25.1 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: he7DrLd-SB1U5cGt1fxDQbbUpf9arpQH X-Proofpoint-GUID: e3I4T1VRJFsVxL_IWldcUoGNFAtHJzaE X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-22_02,2024-08-19_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408220043 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, Previous, vsx_stxvd2x4_le_const_ is introduced for 'split1' pass, so it is guarded by "can_create_pseudo_p ()". While, it would be possible to match the pattern of this insn during/after RA, so this insn could be updated to make it work for split pass after RA. And this insn would not be the best choise, if the address has alignment like "&(-16)", so "!altivec_indexed_or_indirect_operand" is added to guard this insn. Compare with previous version: https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660983.html "!altivec_indexed_or_indirect_operand" is guarded. Bootstrap®test pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu) Guo PR target/116030 gcc/ChangeLog: * config/rs6000/vsx.md (vsx_stxvd2x4_le_const_): Add clobber and guard with !altivec_indexed_or_indirect_operand. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr116030.c: New test. --- gcc/config/rs6000/vsx.md | 10 ++++++---- gcc/testsuite/gcc.target/powerpc/pr116030.c | 21 +++++++++++++++++++++ 2 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr116030.c diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 27069d070e1..6b58fa712c8 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3454,12 +3454,13 @@ (define_insn "*vsx_stxvd2x4_le_" (define_insn_and_split "vsx_stxvd2x4_le_const_" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") - (match_operand:VSX_W 1 "immediate_operand" "W"))] + (match_operand:VSX_W 1 "immediate_operand" "W")) + (clobber (match_scratch:VSX_W 2 "=&wa"))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode) && !TARGET_P9_VECTOR - && const_vec_duplicate_p (operands[1]) - && can_create_pseudo_p ()" + && !altivec_indexed_or_indirect_operand (operands[0], mode) + && const_vec_duplicate_p (operands[1])" "#" "&& 1" [(set (match_dup 2) @@ -3472,7 +3473,8 @@ (define_insn_and_split "vsx_stxvd2x4_le_const_" { /* Here all the constants must be loaded without memory. */ gcc_assert (easy_altivec_constant (operands[1], mode)); - operands[2] = gen_reg_rtx (mode); + if (GET_CODE(operands[2]) == SCRATCH) + operands[2] = gen_reg_rtx (mode); } [(set_attr "type" "vecstore") (set_attr "length" "8")]) diff --git a/gcc/testsuite/gcc.target/powerpc/pr116030.c b/gcc/testsuite/gcc.target/powerpc/pr116030.c new file mode 100644 index 00000000000..304d5519ac6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr116030.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power8 -Os -fno-forward-propagate -ftrivial-auto-var-init=zero -save-temps" } */ + +/* Verify we do not ICE on the tests below. */ + +/* { dg-final { scan-assembler-not "rldicr" { target { le } } } } */ +/* { dg-final { scan-assembler-not "stxvd2x" { target { le } } } } */ + +union U128 +{ + _Decimal128 d; + unsigned long long int u[2]; +}; + +union U128 +foo () +{ + volatile union U128 u128; + u128.d = 0.9999999999999999999999999999999999e+39DL; + return u128; +}