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Signed-off-by: Mayuresh Chitale --- arch/riscv/include/asm/insn-def.h | 42 +++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/riscv/include/asm/insn-def.h diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h new file mode 100644 index 0000000000..99ad5b8f6a --- /dev/null +++ b/arch/riscv/include/asm/insn-def.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Ventana Micro Systems Ltd. + * + * Ported from linux insn-def.h. + */ + +#ifndef _ASM_RISCV_BARRIER_H +#define _ASM_RISCV_BARRIER_H + +#define INSN_I_SIMM12_SHIFT 20 +#define INSN_I_RS1_SHIFT 15 +#define INSN_I_FUNC3_SHIFT 12 +#define INSN_I_RD_SHIFT 7 +#define INSN_I_OPCODE_SHIFT 0 + +#define RV_OPCODE(v) __ASM_STR(v) +#define RV_FUNC3(v) __ASM_STR(v) +#define RV_FUNC7(v) __ASM_STR(v) +#define RV_SIMM12(v) __ASM_STR(v) +#define RV_RD(v) __ASM_STR(v) +#define RV_RS1(v) __ASM_STR(v) +#define RV_RS2(v) __ASM_STR(v) +#define __RV_REG(v) __ASM_STR(x ## v) +#define RV___RD(v) __RV_REG(v) +#define RV___RS1(v) __RV_REG(v) +#define RV___RS2(v) __RV_REG(v) + +#define RV_OPCODE_MISC_MEM RV_OPCODE(15) +#define RV_OPCODE_SYSTEM RV_OPCODE(115) + +#define RV_OPCODE_MISC_MEM RV_OPCODE(15) +#define RV_OPCODE_SYSTEM RV_OPCODE(115) + +#define __INSN_I(opcode, func3, rd, rs1, simm12) \ + ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n" + +#define INSN_I(opcode, func3, rd, rs1, simm12) \ + __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \ + RV_##rs1, RV_##simm12) + +#endif /* _ASM_RISCV_BARRIER_H */ From patchwork Tue Aug 20 09:37:51 2024 Content-Type: text/plain; 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Signed-off-by: Mayuresh Chitale --- arch/riscv/Kconfig | 4 ++ arch/riscv/include/asm/cache.h | 3 ++ arch/riscv/lib/cache.c | 90 ++++++++++++++++++++++++++++++++++ 3 files changed, 97 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fa3b016c52..0f89d07be7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -310,6 +310,10 @@ endmenu config RISCV_ISA_A def_bool y +config RISCV_ISA_ZICBOM + bool "Zicbom support" + depends on !SYS_DISABLE_DCACHE_OPS + config DMA_ADDR_T_64BIT bool default y if 64BIT diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h index 874963d731..42dbce5b4f 100644 --- a/arch/riscv/include/asm/cache.h +++ b/arch/riscv/include/asm/cache.h @@ -9,6 +9,9 @@ /* cache */ void cache_flush(void); +void riscv_zicbom_init(void); +void cbo_flush(unsigned long start, unsigned long end); +void cbo_inval(unsigned long start, unsigned long end); /* * The current upper bound for RISCV L1 data cache line sizes is 32 bytes. diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index afad7e117f..456353d9c1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -5,6 +5,95 @@ */ #include +#include +#include +#include + +#define CBO_INVAL(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(0)) +#define CBO_CLEAN(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(1)) +#define CBO_FLUSH(base) \ + INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \ + RS1(base), SIMM12(2)) +enum { + CBO_CLEAN, + CBO_FLUSH, + CBO_INVAL +} riscv_cbo_ops; +static int zicbom_block_size; + +static inline void do_cbo_clean(unsigned long base) +{ + asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) :: + "r"(base) : "memory"); +} + +static inline void do_cbo_flush(unsigned long base) +{ + asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) :: + "r"(base) : "memory"); +} + +static inline void do_cbo_inval(unsigned long base) +{ + asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) :: + "r"(base) : "memory"); +} + +static void cbo_op(int op_type, unsigned long start, + unsigned long end) +{ + unsigned long op_size = end - start, size = 0; + void (*fn)(unsigned long base); + + switch (op_type) { + case CBO_CLEAN: + fn = do_cbo_clean; + break; + case CBO_FLUSH: + fn = do_cbo_flush; + break; + case CBO_INVAL: + fn = do_cbo_inval; + break; + } + start &= ~(UL(zicbom_block_size - 1)); + while (size < op_size) { + fn(start + size); + size += zicbom_block_size; + } +} + +void cbo_flush(unsigned long start, unsigned long end) +{ + if (zicbom_block_size) + cbo_op(CBO_FLUSH, start, end); +} + +void cbo_inval(unsigned long start, unsigned long end) +{ + if (zicbom_block_size) + cbo_op(CBO_INVAL, start, end); +} + +void riscv_zicbom_init(void) +{ + struct udevice *dev; + + if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM)) + return; + + uclass_first_device(UCLASS_CPU, &dev); + if (!dev) { + log_err("Failed to get cpu device!\n"); + return; + } + + (void)dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size); +} void invalidate_icache_all(void) { @@ -72,4 +161,5 @@ __weak int dcache_status(void) __weak void enable_caches(void) { + puts("WARNING: Caches not enabled\n"); } From patchwork Tue Aug 20 09:37:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mayuresh Chitale X-Patchwork-Id: 1974325 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; 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Tue, 20 Aug 2024 02:38:41 -0700 (PDT) From: Mayuresh Chitale To: u-boot@lists.denx.de Cc: Mayuresh Chitale , Bin Meng , Tom Rini , =?utf-8?q?=C5=81ukasz_Stelmach?= , Leo Yu-Chi Liang Subject: [PATCH v1 3/3] board: qemu-riscv: Override enable_caches Date: Tue, 20 Aug 2024 09:37:52 +0000 Message-Id: <20240820093800.5436-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240820093800.5436-1-mchitale@ventanamicro.com> References: <20240820093800.5436-1-mchitale@ventanamicro.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Define enable_caches function for the qemu-riscv board which probes for the cbom-block-size dt property when RISCV_ISA_ZICBOM is enabled. Also add flush_dcache_range and invalidate_dcache_range functions which use the corresponding CBO ops. Signed-off-by: Mayuresh Chitale --- board/emulation/qemu-riscv/qemu-riscv.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index e5193e31e3..1795d2f831 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -14,6 +14,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -70,3 +71,18 @@ void *board_fdt_blob_setup(int *err) /* Stored the DTB address there during our init */ return (void *)(ulong)gd->arch.firmware_fdt_addr; } + +void enable_caches(void) +{ + riscv_zicbom_init(); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + cbo_flush(start, end); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + cbo_inval(start, end); +}