From patchwork Mon Aug 19 06:57:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 1973682 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WnNl16hDMz1yfj for ; Mon, 19 Aug 2024 16:59:57 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C2B343864810 for ; Mon, 19 Aug 2024 06:59:55 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mailgw2.hygon.cn (unknown [110.188.70.11]) by sourceware.org (Postfix) with ESMTP id 50EF23850206 for ; Mon, 19 Aug 2024 06:58:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 50EF23850206 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=hygon.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=hygon.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 50EF23850206 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=110.188.70.11 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724050710; cv=none; b=m/ae/rziY0ZU4FR8qr6O7DXYXX6LeBFdFmVYjDGxqAK21Cztum3hRC/+og+WY44pfs5gP6hACMBVszY66ge9X1mR4BPtPD88jsH6mGBx3eWvWd7O6qxVRTm8zV3h35GlZWCYew/RHOZNYCZENa9hsDvq3roPRLJzieInHgu8cpw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1724050710; c=relaxed/simple; bh=/x6I/bx8sFJnK+HxywJ1kSss3CoP52YEMyyNBp4nt/E=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=b7ny3hSXuNK8EheuFJ5JCzcJRiwVtwICq3qGlpvXo4RXNS+7YvqdJLSLzXS07fuQonxg07ZaWJqrJZPlc8Cy7GGC7Zux1CoPtxpTMdcrZcMHw1R/9JzYQDPgm4SAtqLO/B3Br+fsf/gC43ptVdialKhL7QLQ5iAcM1OrzT86J4E= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from maildlp1.hygon.cn (unknown [172.23.18.60]) by mailgw2.hygon.cn (Postfix) with ESMTP id 24D343004C97; Mon, 19 Aug 2024 14:58:12 +0800 (CST) Received: from cncheex01.Hygon.cn (unknown [172.23.18.10]) by maildlp1.hygon.cn (Postfix) with ESMTPS id 40E37103F; Mon, 19 Aug 2024 14:58:18 +0800 (CST) Received: from trace.hygon.cn (172.23.18.45) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 19 Aug 2024 14:58:21 +0800 From: Feifei Wang To: CC: , , , , , , Subject: [v2 1/3] x86: Add new architecture type for Hygon processors Date: Mon, 19 Aug 2024 14:57:53 +0800 Message-ID: <1724050675-17136-2-git-send-email-wangfeifei@hygon.cn> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1724050675-17136-1-git-send-email-wangfeifei@hygon.cn> References: <1723445305-99403-1-git-send-email-wangfeifei@hygon.cn> <1724050675-17136-1-git-send-email-wangfeifei@hygon.cn> MIME-Version: 1.0 X-Originating-IP: [172.23.18.45] X-ClientProxiedBy: cncheex01.Hygon.cn (172.23.18.10) To cncheex01.Hygon.cn (172.23.18.10) X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org Add a new architecture type arch_kind_hygon to spilt Hygon branch from AMD. This is to facilitate the Hygon processors to make settings that are suitable for its own characteristics. Signed-off-by: Feifei Wang Reviewed-by: Jing Li Reviewed-by: H.J. Lu --- sysdeps/x86/cpu-features.c | 19 ++++++++++++++++--- sysdeps/x86/include/cpu-features.h | 1 + 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index 0fb50f9432..e6139e2837 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -986,9 +986,8 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht cpu_features->preferred[index_arch_Avoid_Short_Distance_REP_MOVSB] |= bit_arch_Avoid_Short_Distance_REP_MOVSB; } - /* This spells out "AuthenticAMD" or "HygonGenuine". */ - else if ((ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) - || (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)) + /* This spells out "AuthenticAMD". */ + else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) { unsigned int extended_model; @@ -1104,6 +1103,20 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht } } } + /* This spells out "HygonGenuine". */ + else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e) + { + unsigned int extended_model; + + kind = arch_kind_hygon; + + get_common_indices (cpu_features, &family, &model, &extended_model, + &stepping); + + get_extended_indices (cpu_features); + + update_active (cpu_features); + } else { kind = arch_kind_other; diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index aaae44f0e1..b8e790c8fd 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -881,6 +881,7 @@ enum cpu_features_kind arch_kind_intel, arch_kind_amd, arch_kind_zhaoxin, + arch_kind_hygon, arch_kind_other }; From patchwork Mon Aug 19 06:57:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 1973680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; 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Mon, 19 Aug 2024 14:58:18 +0800 (CST) Received: from cncheex01.Hygon.cn (unknown [172.23.18.10]) by maildlp2.hygon.cn (Postfix) with ESMTPS id D55DD300D1C5; Mon, 19 Aug 2024 14:49:11 +0800 (CST) Received: from trace.hygon.cn (172.23.18.45) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 19 Aug 2024 14:58:22 +0800 From: Feifei Wang To: CC: , , , , , , Subject: [v2 2/3] x86: Add cache information support for Hygon processors Date: Mon, 19 Aug 2024 14:57:54 +0800 Message-ID: <1724050675-17136-3-git-send-email-wangfeifei@hygon.cn> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1724050675-17136-1-git-send-email-wangfeifei@hygon.cn> References: <1723445305-99403-1-git-send-email-wangfeifei@hygon.cn> <1724050675-17136-1-git-send-email-wangfeifei@hygon.cn> MIME-Version: 1.0 X-Originating-IP: [172.23.18.45] X-ClientProxiedBy: cncheex01.Hygon.cn (172.23.18.10) To cncheex01.Hygon.cn (172.23.18.10) X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org Add hygon branch in dl_init_cacheinfo function to initialize cache size variables for hygon processors. In the meanwhile, add handle_hygon() function to get cache information. Signed-off-by: Feifei Wang Reviewed-by: Jing Li Reviewed-by: H.J. Lu --- sysdeps/x86/dl-cacheinfo.h | 60 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index 82e4aa5c19..8f4fe98d88 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -567,6 +567,48 @@ handle_zhaoxin (int name) return 0; } +static long int __attribute__ ((noinline)) +handle_hygon (int name) +{ + unsigned int eax; + unsigned int ebx; + unsigned int ecx; + unsigned int edx; + unsigned int count = 0x1; + + if (name >= _SC_LEVEL3_CACHE_SIZE) + count = 0x3; + else if (name >= _SC_LEVEL2_CACHE_SIZE) + count = 0x2; + else if (name >= _SC_LEVEL1_DCACHE_SIZE) + count = 0x0; + + /* Use __cpuid__ '0x8000_001D' to compute cache details. */ + __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx); + + switch (name) + { + case _SC_LEVEL1_ICACHE_ASSOC: + case _SC_LEVEL1_DCACHE_ASSOC: + case _SC_LEVEL2_CACHE_ASSOC: + case _SC_LEVEL3_CACHE_ASSOC: + return ((ebx >> 22) & 0x3ff) + 1; + case _SC_LEVEL1_ICACHE_LINESIZE: + case _SC_LEVEL1_DCACHE_LINESIZE: + case _SC_LEVEL2_CACHE_LINESIZE: + case _SC_LEVEL3_CACHE_LINESIZE: + return (ebx & 0xfff) + 1; + case _SC_LEVEL1_ICACHE_SIZE: + case _SC_LEVEL1_DCACHE_SIZE: + case _SC_LEVEL2_CACHE_SIZE: + case _SC_LEVEL3_CACHE_SIZE: + return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1); + default: + __builtin_unreachable (); + } + return -1; +} + static void get_common_cache_info (long int *shared_ptr, long int * shared_per_thread_ptr, unsigned int *threads_ptr, long int core) @@ -889,6 +931,24 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) shared_per_thread = shared; } + else if (cpu_features->basic.kind == arch_kind_hygon) + { + data = handle_hygon (_SC_LEVEL1_DCACHE_SIZE); + shared = handle_hygon (_SC_LEVEL3_CACHE_SIZE); + shared_per_thread = shared; + + level1_icache_size = handle_hygon (_SC_LEVEL1_ICACHE_SIZE); + level1_icache_linesize = handle_hygon (_SC_LEVEL1_ICACHE_LINESIZE); + level1_dcache_size = data; + level1_dcache_assoc = handle_hygon (_SC_LEVEL1_DCACHE_ASSOC); + level1_dcache_linesize = handle_hygon (_SC_LEVEL1_DCACHE_LINESIZE); + level2_cache_size = handle_hygon (_SC_LEVEL2_CACHE_SIZE);; + level2_cache_assoc = handle_hygon (_SC_LEVEL2_CACHE_ASSOC); + level2_cache_linesize = handle_hygon (_SC_LEVEL2_CACHE_LINESIZE); + level3_cache_size = shared; + level3_cache_assoc = handle_hygon (_SC_LEVEL3_CACHE_ASSOC); + level3_cache_linesize = handle_hygon (_SC_LEVEL3_CACHE_LINESIZE); + } cpu_features->level1_icache_size = level1_icache_size; cpu_features->level1_icache_linesize = level1_icache_linesize; From patchwork Mon Aug 19 06:57:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feifei Wang X-Patchwork-Id: 1973683 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WnNl71mrbz1yfj for ; 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a=rsa-sha256; d=sourceware.org; s=key; t=1724050711; c=relaxed/simple; bh=kMIQj0fLngOGSCELupjPj6SaUxY0O2KZLQzET6IUvC4=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=ZnnfC9bBjWT/sjU+iO33R1U06Ul2c/Dh2GQDiLwjOxa1EAgRQGl0/PxgHojHJdIAwG07DuyA70CLycPW/zc3NJq+A3n9hBTTALVpHgk9hP1+O9Rv864d3Vqz89poTuzxtbXVeJNwczZlxEolo94D2RcRTNHdxacEudyGO7J1t9o= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from maildlp1.hygon.cn (unknown [172.23.18.60]) by mailgw2.hygon.cn (Postfix) with ESMTP id BE1673004C99; Mon, 19 Aug 2024 14:58:12 +0800 (CST) Received: from cncheex01.Hygon.cn (unknown [172.23.18.10]) by maildlp1.hygon.cn (Postfix) with ESMTPS id D86546981; Mon, 19 Aug 2024 14:58:18 +0800 (CST) Received: from trace.hygon.cn (172.23.18.45) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 19 Aug 2024 14:58:22 +0800 From: Feifei Wang To: CC: , , , , , , Subject: [v2 3/3] x86: Enable non-temporal memset for Hygon processors Date: Mon, 19 Aug 2024 14:57:55 +0800 Message-ID: <1724050675-17136-4-git-send-email-wangfeifei@hygon.cn> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1724050675-17136-1-git-send-email-wangfeifei@hygon.cn> References: <1723445305-99403-1-git-send-email-wangfeifei@hygon.cn> <1724050675-17136-1-git-send-email-wangfeifei@hygon.cn> MIME-Version: 1.0 X-Originating-IP: [172.23.18.45] X-ClientProxiedBy: cncheex01.Hygon.cn (172.23.18.10) To cncheex01.Hygon.cn (172.23.18.10) X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org This patch uses 'Avoid_Non_Temporal_Memset' flag to access the non-temporal memset implementation for hygon processors. Test Results: hygon1 arch x86_memset_non_temporal_threshold = 8MB size new performance time / old performance time 1MB 0.994 4MB 0.996 8MB 0.670 16MB 0.343 32MB 0.355 hygon2 arch x86_memset_non_temporal_threshold = 8MB size new performance time / old performance time 1MB 1 4MB 1 8MB 1.312 16MB 0.822 32MB 0.830 hygon3 arch x86_memset_non_temporal_threshold = 8MB size new performance time / old performance time 1MB 1 4MB 0.990 8MB 0.737 16MB 0.390 32MB 0.401 For hygon arch with this patch, non-temporal stores can improve performance by 20% - 65%. Signed-off-by: Feifei Wang Reviewed-by: Jing Li Reviewed-by: H.J. Lu --- sysdeps/x86/cpu-features.c | 9 +++++++-- sysdeps/x86/dl-cacheinfo.h | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index e6139e2837..1f30e237f5 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -756,9 +756,9 @@ init_cpu_features (struct cpu_features *cpu_features) unsigned int stepping = 0; enum cpu_features_kind kind; - /* Default is avoid non-temporal memset for non Intel/AMD hardware. This is, + /* Default is avoid non-temporal memset for non Intel/AMD/Hygon hardware. This is, as of writing this, we only have benchmarks indicatings it profitability - on Intel/AMD. */ + on Intel/AMD/Hygon. */ cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset] |= bit_arch_Avoid_Non_Temporal_Memset; @@ -1116,6 +1116,11 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht get_extended_indices (cpu_features); update_active (cpu_features); + + /* Benchmarks indicate non-temporal memset can be profitable on Hygon + hardware. */ + cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset] + &= ~bit_arch_Avoid_Non_Temporal_Memset; } else { diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index 8f4fe98d88..e9579505a3 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -1071,7 +1071,7 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) /* Non-temporal stores are more performant on some hardware above non_temporal_threshold. Currently Prefer_Non_Temporal is set for for both - Intel and AMD hardware. */ + Intel, AMD and Hygon hardware. */ unsigned long int memset_non_temporal_threshold = SIZE_MAX; if (!CPU_FEATURES_ARCH_P (cpu_features, Avoid_Non_Temporal_Memset)) memset_non_temporal_threshold = non_temporal_threshold;