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Wed, 14 Aug 2024 06:43:59 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5A60B20571; Wed, 14 Aug 2024 06:26:16 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA4842056F; Wed, 14 Aug 2024 06:26:13 +0000 (GMT) Received: from [9.200.102.211] (unknown [9.200.102.211]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 14 Aug 2024 06:26:13 +0000 (GMT) Message-ID: <93661e31-a4dd-4c18-a3ad-d2d42010e5af@linux.ibm.com> Date: Wed, 14 Aug 2024 14:26:12 +0800 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner , Richard Sandiford , Jeff Law From: HAO CHEN GUI Subject: [RFC][PATCH, aarch64] Implement 16-byte vector mode const0 store by TImode X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: iXY6nfz6dtBD5yaslLhLLnvn0ubxNY9O X-Proofpoint-GUID: HfMHyV87M9ix02OPG5gpho_7Ap8DSkUc X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-14_04,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 mlxscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408140045 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, I submitted a patch to change the mode checking for CLEAR_BY_PIECES. https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660344.html It causes some regressions on aarch64. With the patch, V2x8QImode is used to do clear by pieces instead of TImode as vector mode is preferable and V2x8QImode supports const0 store. Thus the efficient "stp" instructions can't be generated. I drafted following patch to fix the problem. It can fix regressions found in memset-corner-cases.c, memset-q-reg.c, auto-init-padding-11.c and auto-init-padding-5.c. Not sure if it should be done on all 16-byte vector modes. Also not sure if the patch is proper. So I send this RFC email. Thanks Gui Haochen ChangeLog aarch64: Implement 16-byte vector mode const0 store by TImode gcc/ * config/aarch64/aarch64-simd.md (mov for VSTRUCT_QD): Expand V2x8QImode const0 store by TImode. patch.diff diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 01b084d8ccb..8aa72940b12 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -7766,7 +7766,14 @@ (define_expand "mov" (match_operand:VSTRUCT_QD 1 "general_operand"))] "TARGET_FLOAT" { - if (can_create_pseudo_p ()) + if (mode == V2x8QImode + && operands[1] == CONST0_RTX (V2x8QImode) + && MEM_P (operands[0])) + { + operands[0] = adjust_address (operands[0], TImode, 0); + operands[1] = CONST0_RTX (TImode); + } + else if (can_create_pseudo_p ()) { if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (mode, operands[1]);