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Tue, 13 Aug 2024 12:41:52 +0000 From: Victor Do Nascimento To: CC: , , , , , , "Victor Do Nascimento" Subject: [PATCH V2 01/10] optabs: Make all `*dot_prod_optab's modeled as conversions Date: Tue, 13 Aug 2024 13:41:41 +0100 Message-ID: <20240813124150.1168825-2-victor.donascimento@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813124150.1168825-1-victor.donascimento@arm.com> References: <20240813124150.1168825-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00027A67:EE_|PAVPR08MB9084:EE_|AM4PEPF00027A66:EE_|AS2PR08MB9546:EE_ X-MS-Office365-Filtering-Correlation-Id: 1b1d5b88-806e-4ee4-9553-08dcbb9556db x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info-Original: D8Fu0zIvU5RksLC8WlcekRbRfleQO3DHniJAW1yH7tYHgXIc/5d5lj+4SJ1MvLhM48YG4Uu6g29tkLy0vDmNVOYLaq0fAoYC0x0joch3JFXYnC/a3fxyponVxq/vAPLgmR/Rotrkz79HfJnHy4VGDr14dC7e9RuD0jPV4lraYamZo+TxcJM4TcCEYmmddn4qSMXUbplK2NdeOKhFWSWCDultbWNyk6YRiVh1KjZSVTu/EBv7fqvYIOWAvcaWszL4QzTWMCwmDiBpPjm0e225Qi/vXQOapWlNj5fm6ds/AKEpavN/GqJdz78dJ2eKjRn1RVZkKWBDMvCkSFJcn9eG+LivU8fjzObYIJrr4jCKiI3xGglWLWWU0V/sV9Iu7CIwKEEiorlUIa1njw8ZZ+Zvinrz7+s/Zl3h5O580kyweA5ptVtgzGuvIvW7ZphpTwzvCbGAM5D6oD1sZO6k/K5XvdrXqpSfJvDuMPKAvmhpZzdS6a7j0cX1s6drflV4U4+Y3o+zGvMvYxBExS2cVnczTZOjS/hOCrDdEHNx0MRDuypnYzAzMlYlnBWSjfpi+/BwnWM0p0ba9+xZXrfkTfBgeUsikBB7IvDxRF+6sCPupUZM/cMRzTaUos/zMKNQKJzMhy2imH+H8zngkZuRKhwfTPbaHjEBQMIXYwt4p95rAyyZgMBVBYepM+yDSqNnWpyGsmLqEu6KyXGEmvLnIOAOLELzFlCVxXfvhHzljL1D+fTnSOcFDT9Iw+suJdMLpdRNHG61rlDrMCqDJgCK8he/V+EZ7SdMytXisLO6nqfqg1FhUlGS1B1he3zD5umEdGAKhWFfz7T4apdKLYOFEtVKh7mFB4OHh3sDdRGrGyJvwFD0vFPnERQgAQJUvPbCAgPq3pp+B0zAROKjdxeIEK5TC0mRKPxddXdDMWI4+BoG4DTUD0p3O7hopYlvYKwZfvb0PHrSuNM9v3RNtsykXzsAAAPCb254wRsOiCfIpfg8d6u2hbyGO2Xr17flF2Kn6hJ+EDpYBtFHYsLZbfPf8O2bp9QtaB2tpMbIAh/Etf+5dcW5iTJFZgVk+moprEJImIX9oInDFgENhpIFGxPDGqMMemZ6WBVcjnwopAv3MHE1FtBTovgsh0Ce1lY0V6OQidH7MMTkxpbZjJG/qmfT4hdzTpnTLKf+lccKn5nKUAy+10i79ev7TZMWuZMPxAy6YtRbM9qN+51Sc2tDB16TvsBBH8qHPhLET/4Hivufe32qSkgCcELQOfTyo+Jbc+QhExBZNvILX/HwkxOQ9vnnEkUNNeBZUYD+9dBQ9v2Jhr7MsiAWF2/zoJhg+mExkfhkIZJ9VKJV0VBXLkZa+1zlFnJTMlPUxCEJEY+3PXB/Er8JHchr/IWDRT53plRlRsej+aoPdD4g9qA0/CX9OXIRE+ZAKABjv1K1bwJnkyfe/yGvbQ9+wTCGcLj/YNAJDZIchmKa X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(35042699022)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2024 12:42:05.9801 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b1d5b88-806e-4ee4-9553-08dcbb9556db X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A66.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9546 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Given the specification in the GCC internals manual defines the {u|s}dot_prod standard name as taking "two signed elements of the same mode, adding them to a third operand of wider mode", there is currently ambiguity in the relationship between the mode of the first two arguments and that of the third. This vagueness means that, in theory, different modes may be supportable in the third argument. This flexibility would allow for a given backend to add to the accumulator a different number of vectorized products, e.g. A backend may provide instructions for both: accum += a[0] * b[0] + a[1] * b[1] + a[2] * b[2] + a[3] * b[3] and accum += a[0] * b[0] + a[1] * b[1], as is now seen in the SVE2.1 extension to AArch64. In spite of the aforementioned flexibility, modeling the dot-product operation as a direct optab means that we have no way to encode both input and the accumulator data modes into the backend pattern name, which prevents us from harnessing this flexibility. We therefore make all dot_prod optabs conversions, allowing, for example, for the encoding of both 2-way and 4-way dot product backend patterns. gcc/ChangeLog: * optabs.def (sdot_prod_optab): Convert from OPTAB_D to OPTAB_CD. (udot_prod_optab): Likewise. (usdot_prod_optab): Likewise. * doc/md.texi (Standard Names): update entries for u,s and us dot_prod names. --- gcc/doc/md.texi | 46 +++++++++++++++++++++------------------------- gcc/optabs.def | 6 +++--- 2 files changed, 24 insertions(+), 28 deletions(-) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 5dc0d55edd6..aa1181a3320 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5760,15 +5760,14 @@ for (i = 0; i < LEN + BIAS; i++) operand0 += operand2[i]; @end smallexample -@cindex @code{sdot_prod@var{m}} instruction pattern -@item @samp{sdot_prod@var{m}} - -Compute the sum of the products of two signed elements. -Operand 1 and operand 2 are of the same mode. Their -product, which is of a wider mode, is computed and added to operand 3. -Operand 3 is of a mode equal or wider than the mode of the product. The -result is placed in operand 0, which is of the same mode as operand 3. -@var{m} is the mode of operand 1 and operand 2. +@cindex @code{sdot_prod@var{m}@var{n}} instruction pattern +@item @samp{sdot_prod@var{m}@var{n}} + +Multiply operand 1 by operand 2 without loss of precision, given that +both operands contain signed elements. Add each product to the overlapping +element of operand 3 and store the result in operand 0. Operands 0 and 3 +have mode @var{m} and operands 1 and 2 have mode @var{n}, with @var{n} +having narrower elements than @var{m}. Semantically the expressions perform the multiplication in the following signs @@ -5778,15 +5777,14 @@ sdot == @dots{} @end smallexample -@cindex @code{udot_prod@var{m}} instruction pattern -@item @samp{udot_prod@var{m}} +@cindex @code{udot_prod@var{m}@var{n}} instruction pattern +@item @samp{udot_prod@var{m}@var{n}} -Compute the sum of the products of two unsigned elements. -Operand 1 and operand 2 are of the same mode. Their -product, which is of a wider mode, is computed and added to operand 3. -Operand 3 is of a mode equal or wider than the mode of the product. The -result is placed in operand 0, which is of the same mode as operand 3. -@var{m} is the mode of operand 1 and operand 2. +Multiply operand 1 by operand 2 without loss of precision, given that +both operands contain unsigned elements. Add each product to the overlapping +element of operand 3 and store the result in operand 0. Operands 0 and 3 +have mode @var{m} and operands 1 and 2 have mode @var{n}, with @var{n} +having narrower elements than @var{m}. Semantically the expressions perform the multiplication in the following signs @@ -5796,14 +5794,12 @@ udot == @dots{} @end smallexample -@cindex @code{usdot_prod@var{m}} instruction pattern -@item @samp{usdot_prod@var{m}} -Compute the sum of the products of elements of different signs. -Operand 1 must be unsigned and operand 2 signed. Their -product, which is of a wider mode, is computed and added to operand 3. -Operand 3 is of a mode equal or wider than the mode of the product. The -result is placed in operand 0, which is of the same mode as operand 3. -@var{m} is the mode of operand 1 and operand 2. +@cindex @code{usdot_prod@var{m}@var{n}} instruction pattern +@item @samp{usdot_prod@var{m}@var{n}} +Multiply operand 1 by operand 2. Add each product to the overlapping +element of operand 3 and store the result in operand 0. Operands 0 and 3 +have mode @var{m} and operands 1 and 2 have mode @var{n}, with @var{n} +having narrower elements than @var{m}. Semantically the expressions perform the multiplication in the following signs diff --git a/gcc/optabs.def b/gcc/optabs.def index 58a939442bd..ba860144d8b 100644 --- a/gcc/optabs.def +++ b/gcc/optabs.def @@ -110,6 +110,9 @@ OPTAB_CD(mask_scatter_store_optab, "mask_scatter_store$a$b") OPTAB_CD(mask_len_scatter_store_optab, "mask_len_scatter_store$a$b") OPTAB_CD(vec_extract_optab, "vec_extract$a$b") OPTAB_CD(vec_init_optab, "vec_init$a$b") +OPTAB_CD (sdot_prod_optab, "sdot_prod$I$a$b") +OPTAB_CD (udot_prod_optab, "udot_prod$I$a$b") +OPTAB_CD (usdot_prod_optab, "usdot_prod$I$a$b") OPTAB_CD (while_ult_optab, "while_ult$a$b") @@ -413,10 +416,7 @@ OPTAB_D (savg_floor_optab, "avg$a3_floor") OPTAB_D (uavg_floor_optab, "uavg$a3_floor") OPTAB_D (savg_ceil_optab, "avg$a3_ceil") OPTAB_D (uavg_ceil_optab, "uavg$a3_ceil") -OPTAB_D (sdot_prod_optab, "sdot_prod$I$a") OPTAB_D (ssum_widen_optab, "widen_ssum$I$a3") -OPTAB_D (udot_prod_optab, "udot_prod$I$a") -OPTAB_D (usdot_prod_optab, "usdot_prod$I$a") OPTAB_D (usum_widen_optab, "widen_usum$I$a3") OPTAB_D (usad_optab, "usad$I$a") OPTAB_D (ssad_optab, "ssad$I$a") From patchwork Tue Aug 13 12:41:42 2024 Content-Type: text/plain; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(35042699022)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2024 12:42:05.8403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f64f4488-ba29-4252-7724-08dcbb9556e0 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509FA.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU5PR08MB10823 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Given the shift from modeling dot products as direct optabs to treating them as conversion optabs, we make necessary changes to the autovectorizer code to ensure that given the relevant tree code, together with the input and output data modes, we can retrieve the relevant optab and subsequently the insn_code for it. gcc/ChangeLog: * gimple-match-exports.cc (directly_supported_p): Add overload for conversion-type optabs. * gimple-match.h (directly_supported_p): Add new function prototype. * optabs.cc (expand_widen_pattern_expr): Make the DOT_PROD_EXPR tree code use `find_widening_optab_handler' to retrieve icode. * tree-vect-loop.cc (vect_is_emulated_mixed_dot_prod): make it call conversion-type overloaded `directly_supported_p'. * tree-vect-patterns.cc (vect_supportable_conv_optab_p): New. (vect_recog_dot_prod_pattern): s/direct/conv/ in call to `vect_supportable_direct_optab_p'. --- gcc/gimple-match-exports.cc | 23 ++++++++++++++++++++ gcc/gimple-match.h | 2 ++ gcc/optabs.cc | 3 ++- gcc/tree-vect-loop.cc | 1 + gcc/tree-vect-patterns.cc | 43 +++++++++++++++++++++++++++++++++++-- 5 files changed, 69 insertions(+), 3 deletions(-) diff --git a/gcc/gimple-match-exports.cc b/gcc/gimple-match-exports.cc index aacf3ff0414..d18497e7c83 100644 --- a/gcc/gimple-match-exports.cc +++ b/gcc/gimple-match-exports.cc @@ -1381,6 +1381,29 @@ directly_supported_p (code_helper code, tree type, optab_subtype query_type) && direct_internal_fn_supported_p (ifn, type, OPTIMIZE_FOR_SPEED)); } +/* As above, overloading the function for conversion-type optabs. */ +bool +directly_supported_p (code_helper code, tree type_out, tree type_in, + optab_subtype query_type) +{ + if (code.is_tree_code ()) + { + convert_optab optab = optab_for_tree_code (tree_code (code), type_in, + query_type); + return (optab != unknown_optab + && convert_optab_handler (optab, TYPE_MODE (type_out), + TYPE_MODE (type_in)) != CODE_FOR_nothing); + } + gcc_assert (query_type == optab_default + || (query_type == optab_vector && VECTOR_TYPE_P (type_in)) + || (query_type == optab_scalar && !VECTOR_TYPE_P (type_in))); + internal_fn ifn = associated_internal_fn (combined_fn (code), type_in); + return (direct_internal_fn_p (ifn) + && direct_internal_fn_supported_p (ifn, tree_pair (type_out, type_in), + OPTIMIZE_FOR_SPEED)); +} + + /* A wrapper around the internal-fn.cc versions of get_conditional_internal_fn for a code_helper CODE operating on type TYPE. */ diff --git a/gcc/gimple-match.h b/gcc/gimple-match.h index d710fcbace2..0333a5db00a 100644 --- a/gcc/gimple-match.h +++ b/gcc/gimple-match.h @@ -419,6 +419,8 @@ code_helper canonicalize_code (code_helper, tree); #ifdef GCC_OPTABS_TREE_H bool directly_supported_p (code_helper, tree, optab_subtype = optab_default); +bool directly_supported_p (code_helper, tree, tree, + optab_subtype = optab_default); #endif internal_fn get_conditional_internal_fn (code_helper, tree); diff --git a/gcc/optabs.cc b/gcc/optabs.cc index 185c5b1a705..32737fb80e8 100644 --- a/gcc/optabs.cc +++ b/gcc/optabs.cc @@ -317,7 +317,8 @@ expand_widen_pattern_expr (const_sepops ops, rtx op0, rtx op1, rtx wide_op, widen_pattern_optab = optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); if (ops->code == WIDEN_MULT_PLUS_EXPR - || ops->code == WIDEN_MULT_MINUS_EXPR) + || ops->code == WIDEN_MULT_MINUS_EXPR + || ops->code == DOT_PROD_EXPR) icode = find_widening_optab_handler (widen_pattern_optab, TYPE_MODE (TREE_TYPE (ops->op2)), tmode0); diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index 6456220cdc9..5f3de7b72a8 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -5289,6 +5289,7 @@ vect_is_emulated_mixed_dot_prod (stmt_vec_info stmt_info) gcc_assert (STMT_VINFO_REDUC_VECTYPE_IN (stmt_info)); return !directly_supported_p (DOT_PROD_EXPR, + STMT_VINFO_VECTYPE (stmt_info), STMT_VINFO_REDUC_VECTYPE_IN (stmt_info), optab_vector_mixed_sign); } diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc index f52de2b6972..3afedc9199b 100644 --- a/gcc/tree-vect-patterns.cc +++ b/gcc/tree-vect-patterns.cc @@ -250,6 +250,45 @@ vect_supportable_direct_optab_p (vec_info *vinfo, tree otype, tree_code code, return true; } +/* Return true if the target supports a vector version of CODE, + where CODE is known to map to a conversion optab with the given SUBTYPE. + ITYPE specifies the type of (some of) the scalar inputs and OTYPE + specifies the type of the scalar result. + + When returning true, set *VECOTYPE_OUT to the vector version of OTYPE. + Also set *VECITYPE_OUT to the vector version of ITYPE if VECITYPE_OUT + is nonnull. */ + +static bool +vect_supportable_conv_optab_p (vec_info *vinfo, tree otype, tree_code code, + tree itype, tree *vecotype_out, + tree *vecitype_out = NULL, + enum optab_subtype subtype = optab_default) +{ + tree vecitype = get_vectype_for_scalar_type (vinfo, itype); + tree vecotype = get_vectype_for_scalar_type (vinfo, otype); + if (!vecitype || !vecotype) + return false; + + optab optab = optab_for_tree_code (code, vecitype, subtype); + if (!optab) + return false; + + insn_code icode = convert_optab_handler (optab, TYPE_MODE (vecotype), + TYPE_MODE (vecitype)); + + if (icode == CODE_FOR_nothing + || insn_data[icode].operand[0].mode != TYPE_MODE (vecotype) + || insn_data[icode].operand[1].mode != TYPE_MODE (vecitype)) + return false; + + *vecotype_out = vecotype; + if (vecitype_out) + *vecitype_out = vecitype; + return true; +} + + /* Round bit precision PRECISION up to a full element. */ static unsigned int @@ -1270,13 +1309,13 @@ vect_recog_dot_prod_pattern (vec_info *vinfo, half_type = signed_type_for (half_type); tree half_vectype; - if (!vect_supportable_direct_optab_p (vinfo, type, DOT_PROD_EXPR, half_type, + if (!vect_supportable_conv_optab_p (vinfo, type, DOT_PROD_EXPR, half_type, type_out, &half_vectype, subtype)) { /* We can emulate a mixed-sign dot-product using a sequence of signed dot-products; see vect_emulate_mixed_dot_prod for details. */ if (subtype != optab_vector_mixed_sign - || !vect_supportable_direct_optab_p (vinfo, signed_type_for (type), + || !vect_supportable_conv_optab_p (vinfo, signed_type_for (type), DOT_PROD_EXPR, half_type, type_out, &half_vectype, optab_vector)) From patchwork Tue Aug 13 12:41:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 1971944 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=W/dfbU3v; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=W/dfbU3v; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024)(35042699022); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2024 12:42:07.8926 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3db10ae6-ec9d-4967-7b5f-08dcbb9557f3 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000190.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9014 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Given recent changes to the dot_prod standard pattern name, this patch fixes the aarch64 back-end by implementing the following changes: 1. Add 2nd mode to all (u|s|us)dot_prod patterns in .md files. 2. Rewrite initialization and function expansion mechanism for simd builtins. 3. Fix all direct calls to back-end `dot_prod' patterns in SVE builtins. Finally, given that it is now possible for the compiler to differentiate between the two- and four-way dot product, we add a test to ensure that autovectorization picks up on dot-product patterns where the result is twice the width of the operands. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (dot_prod): Renamed to... (dot_prod): ...this. (usdot_prod): Renamed to... (usdot_prod): ...this. (sadv16qi): Adjust call to gen_udot_prod take second mode. (popcount): fix use of `udot_prod_optab'. * gcc/config/aarch64/aarch64-sve.md (dot_prod): Renamed to... (dot_prod): ...this. (@dot_prod): Renamed to... (@dot_prod): ...this. (sad): Adjust call to gen_udot_prod take second mode. * gcc/config/aarch64/aarch64-sve2.md (@aarch64_sve_dotvnx4sivnx8hi): Renamed to... (dot_prodvnx4sivnx8hi): ...this. * config/aarch64/aarch64-simd-builtins.def: Modify macro expansion-based initialization and expansion of (u|s|us)dot_prod builtins. * config/aarch64/aarch64-sve-builtins-base.cc (svdot_impl::expand): s/direct/convert/ in `convert_optab_handler_for_sign' function call. (svusdot_impl::expand): add second mode argument in call to `code_for_dot_prod'. * config/aarch64/aarch64-sve-builtins.cc (function_expander::convert_optab_handler_for_sign): New class method. * config/aarch64/aarch64-sve-builtins.h (class function_expander): Add prototype for new `convert_optab_handler_for_sign' method. gcc/testsuite/ChangeLog: * gcc.target/aarch64/sme/vect-dotprod-twoway.c (udot2): New. --- gcc/config/aarch64/aarch64-builtins.cc | 7 ++++++ gcc/config/aarch64/aarch64-simd-builtins.def | 6 ++--- gcc/config/aarch64/aarch64-simd.md | 9 ++++--- .../aarch64/aarch64-sve-builtins-base.cc | 13 +++++----- gcc/config/aarch64/aarch64-sve-builtins.cc | 17 +++++++++++++ gcc/config/aarch64/aarch64-sve-builtins.h | 3 +++ gcc/config/aarch64/aarch64-sve.md | 6 ++--- gcc/config/aarch64/aarch64-sve2.md | 2 +- .../aarch64/sme/vect-dotprod-twoway.c | 25 +++++++++++++++++++ 9 files changed, 71 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 30669f8aa18..8af646ab066 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -458,6 +458,13 @@ aarch64_types_storestruct_lane_p_qualifiers[SIMD_MAX_BUILTIN_ARGS] qualifier_poly, qualifier_struct_load_store_lane_index }; #define TYPES_STORESTRUCT_LANE_P (aarch64_types_storestruct_lane_p_qualifiers) +constexpr insn_code CODE_FOR_aarch64_sdot_prodv8qi = CODE_FOR_sdot_prodv2siv8qi; +constexpr insn_code CODE_FOR_aarch64_udot_prodv8qi = CODE_FOR_udot_prodv2siv8qi; +constexpr insn_code CODE_FOR_aarch64_usdot_prodv8qi = CODE_FOR_usdot_prodv2siv8qi; +constexpr insn_code CODE_FOR_aarch64_sdot_prodv16qi = CODE_FOR_sdot_prodv4siv16qi; +constexpr insn_code CODE_FOR_aarch64_udot_prodv16qi = CODE_FOR_udot_prodv4siv16qi; +constexpr insn_code CODE_FOR_aarch64_usdot_prodv16qi = CODE_FOR_usdot_prodv4siv16qi; + #define CF0(N, X) CODE_FOR_aarch64_##N##X #define CF1(N, X) CODE_FOR_##N##X##1 #define CF2(N, X) CODE_FOR_##N##X##2 diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index e65f73d7ba2..0814f8ba14f 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -418,9 +418,9 @@ BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0, NONE) /* Implemented by _prod. */ - BUILTIN_VB (TERNOP, sdot_prod, 10, NONE) - BUILTIN_VB (TERNOPU, udot_prod, 10, NONE) - BUILTIN_VB (TERNOP_SUSS, usdot_prod, 10, NONE) + BUILTIN_VB (TERNOP, sdot_prod, 0, NONE) + BUILTIN_VB (TERNOPU, udot_prod, 0, NONE) + BUILTIN_VB (TERNOP_SUSS, usdot_prod, 0, NONE) /* Implemented by aarch64__lane{q}. */ BUILTIN_VB (QUADOP_LANE, sdot_lane, 0, NONE) BUILTIN_VB (QUADOPU_LANE, udot_lane, 0, NONE) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index cc612ec2ca0..e15e547b000 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -568,7 +568,7 @@ (define_expand "cmul3" ;; ... ;; ;; and so the vectorizer provides r, in which the result has to be accumulated. -(define_insn "dot_prod" +(define_insn "dot_prod" [(set (match_operand:VS 0 "register_operand" "=w") (plus:VS (unspec:VS [(match_operand: 1 "register_operand" "w") @@ -582,7 +582,7 @@ (define_insn "dot_prod" ;; These instructions map to the __builtins for the Armv8.6-a I8MM usdot ;; (vector) Dot Product operation and the vectorized optab. -(define_insn "usdot_prod" +(define_insn "usdot_prod" [(set (match_operand:VS 0 "register_operand" "=w") (plus:VS (unspec:VS [(match_operand: 1 "register_operand" "w") @@ -1075,7 +1075,7 @@ (define_expand "sadv16qi" rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode)); rtx abd = gen_reg_rtx (V16QImode); emit_insn (gen_aarch64_abdv16qi (abd, operands[1], operands[2])); - emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3])); + emit_insn (gen_udot_prodv4siv16qi (operands[0], abd, ones, operands[3])); DONE; } rtx reduc = gen_reg_rtx (V8HImode); @@ -3528,6 +3528,7 @@ (define_expand "popcount2" /* Generate a byte popcount. */ machine_mode mode = == 64 ? V8QImode : V16QImode; + machine_mode mode2 = == 64 ? V2SImode : V4SImode; rtx tmp = gen_reg_rtx (mode); auto icode = optab_handler (popcount_optab, mode); emit_insn (GEN_FCN (icode) (tmp, gen_lowpart (mode, operands[1]))); @@ -3538,7 +3539,7 @@ (define_expand "popcount2" /* For V4SI and V2SI, we can generate a UDOT with a 0 accumulator and a 1 multiplicand. For V2DI, another UAADDLP is needed. */ rtx ones = force_reg (mode, CONST1_RTX (mode)); - auto icode = optab_handler (udot_prod_optab, mode); + auto icode = convert_optab_handler (udot_prod_optab, mode2, mode); mode = == 64 ? V2SImode : V4SImode; rtx dest = mode == mode ? operands[0] : gen_reg_rtx (mode); rtx zeros = force_reg (mode, CONST0_RTX (mode)); diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index d55bee0b72f..42e9cec57ad 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -804,15 +804,16 @@ public: e.rotate_inputs_left (0, 3); insn_code icode; if (e.type_suffix_ids[1] == NUM_TYPE_SUFFIXES) - icode = e.direct_optab_handler_for_sign (sdot_prod_optab, - udot_prod_optab, - 0, GET_MODE (e.args[0])); + icode = e.convert_optab_handler_for_sign (sdot_prod_optab, + udot_prod_optab, + 0, e.result_mode (), + GET_MODE (e.args[0])); else icode = (e.type_suffix (0).float_p ? CODE_FOR_aarch64_sve_fdotvnx4sfvnx8hf : e.type_suffix (0).unsigned_p - ? CODE_FOR_aarch64_sve_udotvnx4sivnx8hi - : CODE_FOR_aarch64_sve_sdotvnx4sivnx8hi); + ? CODE_FOR_udot_prodvnx4sivnx8hi + : CODE_FOR_sdot_prodvnx4sivnx8hi); return e.use_unpred_insn (icode); } }; @@ -2861,7 +2862,7 @@ public: Hence we do the same rotation on arguments as svdot_impl does. */ e.rotate_inputs_left (0, 3); machine_mode mode = e.vector_mode (0); - insn_code icode = code_for_dot_prod (UNSPEC_USDOT, mode); + insn_code icode = code_for_dot_prod (UNSPEC_USDOT, e.result_mode (), mode); return e.use_exact_insn (icode); } diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc b/gcc/config/aarch64/aarch64-sve-builtins.cc index 0a560eaedca..975eca0bbd6 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins.cc @@ -3745,6 +3745,23 @@ function_expander::direct_optab_handler_for_sign (optab signed_op, return ::direct_optab_handler (op, mode); } +/* Choose between signed and unsigned convert optabs SIGNED_OP and + UNSIGNED_OP based on the signedness of type suffix SUFFIX_I, then + pick the appropriate optab handler for the mode. Use MODE as the + mode if given, otherwise use the mode of type suffix SUFFIX_I. */ +insn_code +function_expander::convert_optab_handler_for_sign (optab signed_op, + optab unsigned_op, + unsigned int suffix_i, + machine_mode to_mode, + machine_mode from_mode) +{ + if (from_mode == VOIDmode) + from_mode = vector_mode (suffix_i); + optab op = type_suffix (suffix_i).unsigned_p ? unsigned_op : signed_op; + return ::convert_optab_handler (op, to_mode, from_mode); +} + /* Return true if X overlaps any input. */ bool function_expander::overlaps_input_p (rtx x) diff --git a/gcc/config/aarch64/aarch64-sve-builtins.h b/gcc/config/aarch64/aarch64-sve-builtins.h index 9ab6f202c30..7534a58c3d7 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins.h +++ b/gcc/config/aarch64/aarch64-sve-builtins.h @@ -659,6 +659,9 @@ public: insn_code direct_optab_handler (optab, unsigned int = 0); insn_code direct_optab_handler_for_sign (optab, optab, unsigned int = 0, machine_mode = E_VOIDmode); + insn_code convert_optab_handler_for_sign (optab, optab, unsigned int = 0, + machine_mode = E_VOIDmode, + machine_mode = E_VOIDmode); machine_mode result_mode () const; diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index a5cd42be9d5..2fe18bdacfe 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -7197,7 +7197,7 @@ (define_insn_and_rewrite "*cond_fnma_any" ;; ------------------------------------------------------------------------- ;; Four-element integer dot-product with accumulation. -(define_insn "dot_prod" +(define_insn "dot_prod" [(set (match_operand:SVE_FULL_SDI 0 "register_operand") (plus:SVE_FULL_SDI (unspec:SVE_FULL_SDI @@ -7235,7 +7235,7 @@ (define_insn "@aarch64_dot_prod_lane" } ) -(define_insn "@dot_prod" +(define_insn "@dot_prod" [(set (match_operand:VNx4SI_ONLY 0 "register_operand") (plus:VNx4SI_ONLY (unspec:VNx4SI_ONLY @@ -7293,7 +7293,7 @@ (define_expand "sad" rtx ones = force_reg (mode, CONST1_RTX (mode)); rtx diff = gen_reg_rtx (mode); emit_insn (gen_abd3 (diff, operands[1], operands[2])); - emit_insn (gen_udot_prod (operands[0], diff, ones, operands[3])); + emit_insn (gen_udot_prod (operands[0], diff, ones, operands[3])); DONE; } ) diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 972b03a4fef..725092cc95f 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -2021,7 +2021,7 @@ (define_insn "@aarch64_sve_qsub__lane_" ) ;; Two-way dot-product. -(define_insn "@aarch64_sve_dotvnx4sivnx8hi" +(define_insn "dot_prodvnx4sivnx8hi" [(set (match_operand:VNx4SI 0 "register_operand") (plus:VNx4SI (unspec:VNx4SI diff --git a/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c b/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c new file mode 100644 index 00000000000..453f3a75e6f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c @@ -0,0 +1,25 @@ +/* { dg-additional-options "-march=armv9.2-a+sme2 -O2 -ftree-vectorize" } */ + +#include + +uint32_t udot2(int n, uint16_t* data) __arm_streaming +{ + uint32_t sum = 0; + for (int i=0; i X-Patchwork-Id: 1971948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Tue, 13 Aug 2024 12:41:54 +0000 From: Victor Do Nascimento To: CC: , , , , , , "Victor Do Nascimento" Subject: [PATCH V2 04/10] arm: Fix arm backend-use of (u|s|us)dot_prod patterns Date: Tue, 13 Aug 2024 13:41:44 +0100 Message-ID: <20240813124150.1168825-5-victor.donascimento@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240813124150.1168825-1-victor.donascimento@arm.com> References: <20240813124150.1168825-1-victor.donascimento@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM4PEPF00027A5D:EE_|DU0PR08MB7415:EE_|DB1PEPF000509FD:EE_|PA4PR08MB5982:EE_ X-MS-Office365-Filtering-Correlation-Id: e1235fc6-020d-4658-8bf4-08dcbb9556e2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info-Original: SnmgmS0WYdeuYOcU5JDgKz6TyKRAdkrhivgr52pNptNG7sTEodw2paYYeOY16Y+Z6VJlpoB8ZIqa+Rv2Srx2xffD2RVe+p4VJhArH+l9Y0CSeF2ZRsQwaeT8sCJDBVFb2iL6TwexpLWphavjeASqQZS30cZhBUVBP0Kgq/12u2YqH4bCkqL+yAMusFG7pwzQ0RuDXC7hgQpLsbKhyRDTirFrNXvT3RA3hiHvZis481qO6v+r8RlXGYneiJZjEZrDYSr8Cdm9qifkRkWFoPzDg7O1iJPu+XkC9+xLnpstRAKsE0ngjM71bY55ZexEQx6BSBisx6cETADzxyUf0dPKhoCa+HCq4MDSlLyhm/hEj1e4MNSrQGIowXPwD7FVacUcupCV8l8mM6e7pc0F3bBW2DEN0ZjTxlYFMfgLha0BPQxK6/AYnbdXSgLeS9/1vw/5sPV9faoHRVtFXeSuY4vqYacK+FFxBNQdtVTD5CTaGp3x7oT6oUwHUfxgPPeanIn1thiisXVS9s0ey5y2vNPpm6cN0e70kH6UkFXKsO4VKBV3axDl3xtD+p1NGQRn+ttnSXQSt4Wgok3uGc7wA6Qr968CknBdRaHdLEOR0xUByQc+AM3B7Nnh3TPBNtwvtwskCrIalFPCPBnllGHJmWxsu2mJGSzSUX14QVwGmWlbLFs83f2jdee3IfAXjntp7pi1AbyiWteoU7FOWAsEh5SRcMVqneZhe+gykUVGPhwIV90GJNgsKetZe35MRhW+aB9lSaAUYsRoFXZNnjdEqPVJzVvluckwmbzYV2pOWyDEGqk0WJrMtYrELjUb9Ng2lxmPe/vrLWtg2YJICISupZDbuiJaIaoLXETTUonMa7jY3pPe0dZqXZekKL5O83C71xwQhuReKNjFhOeoOLoEIJUvjntuVtRMgEkFKyuO89NPuf9eZypAN6zcNiiDeDGCDJr6YZ5e7mT/2ZPj3MRQeNEFoiGiEXMWbVnRiCrf2ludFsjNSVt7s0xbJR90Yob+3fMb6qd8N9AKwOoKXOosY/DJjZWXof685osZB7H5EKwHnc0u+uM3mWHeulkg4eqdvntxR5a0D0/82mw7hBNbiErwO/kxF6kplyQNNxxNF0N3qZL/h4Ngq90NZp8itVVue7EXGuYO8L5JLOxwCUikbrQnqqynuO8dVqxg86Sgw5G1xeNkGen5IYUTEVB0vy0l+qGki+EnlwUOvx6M9N+NyJWLyYsWzKd9bgtxeDAYHub6gw6Y7OLACfFtYnNEzGhe0ZOsMG8g7Dnw4LjWI0KuWKAbIUnoSVFBNb6t0Ids+XpFRjF4LQUdHN4E1PaJnTQgliPsGoZ0W4kb2+I/GFPbY1CoP5WFChteQwcxefvDQkoXWkXzmlNcxvSAVhL6l0UugRMQkb++9X6WmNRLzrIfLpbxSsLq1J8RfdFQnhI1R8OwLWwugFgpimR3tfBDry6Ld142 X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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(arm_init_dotprod_builtins): New. (arm_init_builtins): Add call to `arm_init_dotprod_builtins'. (arm_general_gimple_fold_builtin): New. * config/arm/arm-protos.h (arm_general_gimple_fold_builtin): New prototype. * config/arm/arm.cc (arm_gimple_fold_builtin): Add call to `arm_general_gimple_fold_builtin'. * config/arm/neon.md (dot_prod): Renamed to... (dot_prod): ...this. (neon_usdot): Renamed to... (neon_usdot): ...this. --- gcc/config/arm/arm-builtins.cc | 95 ++++++++++++++++++++++++++++ gcc/config/arm/arm-protos.h | 3 + gcc/config/arm/arm.cc | 1 + gcc/config/arm/arm_neon_builtins.def | 3 - gcc/config/arm/neon.md | 6 +- 5 files changed, 102 insertions(+), 6 deletions(-) diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc index c9d50bf8fbb..b23b6caa063 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -45,6 +45,8 @@ #include "arm-builtins.h" #include "stringpool.h" #include "attribs.h" +#include "basic-block.h" +#include "gimple.h" #define SIMD_MAX_BUILTIN_ARGS 7 @@ -1298,6 +1300,13 @@ enum arm_builtins #define VAR1(T, N, X) \ ARM_BUILTIN_##N, + ARM_BUILTIN_NEON_SDOTV8QI, + ARM_BUILTIN_NEON_SDOTV16QI, + ARM_BUILTIN_NEON_UDOTV8QI, + ARM_BUILTIN_NEON_UDOTV16QI, + ARM_BUILTIN_NEON_USDOTV8QI, + ARM_BUILTIN_NEON_USDOTV16QI, + ARM_BUILTIN_ACLE_BASE, ARM_BUILTIN_SAT_IMM_CHECK = ARM_BUILTIN_ACLE_BASE, @@ -2648,6 +2657,60 @@ arm_init_fp16_builtins (void) "__fp16"); } +static void +arm_init_dotprod_builtins (void) +{ + tree fndecl = NULL; + tree ftype = NULL; + + tree uv8qi = arm_simd_builtin_type (V8QImode, qualifier_unsigned); + tree sv8qi = arm_simd_builtin_type (V8QImode, qualifier_none); + tree uv16qi = arm_simd_builtin_type (V16QImode, qualifier_unsigned); + tree sv16qi = arm_simd_builtin_type (V16QImode, qualifier_none); + tree uv2si = arm_simd_builtin_type (V2SImode, qualifier_unsigned); + tree sv2si = arm_simd_builtin_type (V2SImode, qualifier_none); + tree uv4si = arm_simd_builtin_type (V4SImode, qualifier_unsigned); + tree sv4si = arm_simd_builtin_type (V4SImode, qualifier_none); + + struct builtin_decls_data + { + tree out_type_node; + tree in_type1_node; + tree in_type2_node; + const char *builtin_name; + int function_code; + }; + +#define NAME(A) "__builtin_neon_" #A +#define ENUM(B) ARM_BUILTIN_NEON_##B + + builtin_decls_data bdda[] = + { + { sv2si, sv8qi, sv8qi, NAME (sdotv8qi), ENUM (SDOTV8QI) }, + { uv2si, uv8qi, uv8qi, NAME (udotv8qi_uuuu), ENUM (UDOTV8QI) }, + { sv2si, uv8qi, sv8qi, NAME (usdotv8qi_ssus), ENUM (USDOTV8QI) }, + { sv4si, sv16qi, sv16qi, NAME (sdotv16qi), ENUM (SDOTV16QI) }, + { uv4si, uv16qi, uv16qi, NAME (udotv16qi_uuuu), ENUM (UDOTV16QI) }, + { sv4si, uv16qi, sv16qi, NAME (usdotv16qi_ssus), ENUM (USDOTV16QI) }, + }; + +#undef NAME +#undef ENUM + + builtin_decls_data *bdd = bdda; + builtin_decls_data *bdd_end = bdd + (ARRAY_SIZE (bdda)); + + for (; bdd < bdd_end; bdd++) + { + ftype = build_function_type_list (bdd->out_type_node, bdd->out_type_node, + bdd->in_type1_node, bdd->in_type2_node, + NULL_TREE); + fndecl = arm_general_add_builtin_function (bdd->builtin_name, + ftype, bdd->function_code); + arm_builtin_decls[bdd->function_code] = fndecl; + } +} + void arm_init_builtins (void) { @@ -2676,6 +2739,7 @@ arm_init_builtins (void) arm_init_neon_builtins (); arm_init_vfp_builtins (); arm_init_crypto_builtins (); + arm_init_dotprod_builtins (); } if (TARGET_CDE) @@ -2738,6 +2802,37 @@ arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) } } +/* Try to fold STMT, given that it's a call to the built-in function with + subcode FCODE. Return the new statement on success and null on + failure. */ +gimple * +arm_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, + gimple_stmt_iterator *gsi ATTRIBUTE_UNUSED) +{ + gimple *new_stmt = NULL; + unsigned nargs = gimple_call_num_args (stmt); + tree *args = (nargs > 0 + ? gimple_call_arg_ptr (stmt, 0) + : &error_mark_node); + + switch (fcode) + { + case ARM_BUILTIN_NEON_SDOTV8QI: + case ARM_BUILTIN_NEON_SDOTV16QI: + case ARM_BUILTIN_NEON_UDOTV8QI: + case ARM_BUILTIN_NEON_UDOTV16QI: + case ARM_BUILTIN_NEON_USDOTV8QI: + case ARM_BUILTIN_NEON_USDOTV16QI: + new_stmt = gimple_build_assign (gimple_call_lhs (stmt), + DOT_PROD_EXPR, args[1], + args[2], args[0]); + break; + default: + break; + } + return new_stmt; +} + /* Errors in the source file can cause expand_expr to return const0_rtx where we expect a vector. To avoid crashing, use one of the vector clear instructions. */ diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 50cae2b513a..4e31d1d0225 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -57,6 +57,9 @@ extern rtx arm_expand_builtin (tree exp, rtx target, rtx subtarget extern tree arm_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED); extern void arm_init_builtins (void); +extern gimple *arm_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt, + gimple_stmt_iterator *gsi + ATTRIBUTE_UNUSED); extern void arm_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update); extern rtx arm_simd_vect_par_cnst_half (machine_mode mode, bool high); extern bool arm_simd_check_vect_par_cnst_half_p (rtx op, machine_mode mode, diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 92cd168e659..109e9c131f5 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -2852,6 +2852,7 @@ arm_gimple_fold_builtin (gimple_stmt_iterator *gsi) switch (code & ARM_BUILTIN_CLASS) { case ARM_BUILTIN_GENERAL: + new_stmt = arm_general_gimple_fold_builtin (subcode, stmt, gsi); break; case ARM_BUILTIN_MVE: new_stmt = arm_mve::gimple_fold_builtin (subcode, stmt); diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 0c5d40b96e5..cf5537ca95d 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -349,14 +349,11 @@ VAR13 (STORE1, vst4, v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf) VAR11 (STORE1LANE, vst4_lane, v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf, v4bf, v8bf) -VAR2 (TERNOP, sdot, v8qi, v16qi) -VAR2 (UTERNOP, udot, v8qi, v16qi) VAR2 (MAC_LANE, sdot_lane, v8qi, v16qi) VAR2 (UMAC_LANE, udot_lane, v8qi, v16qi) VAR2 (MAC_LANE, sdot_laneq, v8qi, v16qi) VAR2 (UMAC_LANE, udot_laneq, v8qi, v16qi) -VAR2 (USTERNOP, usdot, v8qi, v16qi) VAR2 (USMAC_LANE_QUADTUP, usdot_lane, v8qi, v16qi) VAR2 (SUMAC_LANE_QUADTUP, sudot_lane, v8qi, v16qi) VAR2 (USMAC_LANE_QUADTUP, usdot_laneq, v8qi, v16qi) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index fa4a7aeda35..b3a3564ca2b 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2989,7 +2989,7 @@ (define_expand "cmul3" ;; ... ;; ;; and so the vectorizer provides r, in which the result has to be accumulated. -(define_insn "dot_prod" +(define_insn "dot_prod" [(set (match_operand:VCVTI 0 "register_operand" "=w") (plus:VCVTI (unspec:VCVTI [(match_operand: 1 "register_operand" "w") @@ -3013,7 +3013,7 @@ (define_expand "neon_dot" ) ;; These instructions map to the __builtins for the Dot Product operations. -(define_insn "neon_usdot" +(define_insn "neon_usdot" [(set (match_operand:VCVTI 0 "register_operand" "=w") (plus:VCVTI (unspec:VCVTI @@ -3112,7 +3112,7 @@ (define_insn "neon_dot_laneq" ) ;; Auto-vectorizer pattern for usdot -(define_expand "usdot_prod" +(define_expand "usdot_prod" [(set (match_operand:VCVTI 0 "register_operand") (plus:VCVTI (unspec:VCVTI [(match_operand: 1 "register_operand") From patchwork Tue Aug 13 12:41:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 1971949 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(usdot_prodv2siv8qi): ...this. (sdot_prodv8qi): Renamed to... (sdot_prodv2siv8qi): ...this. (udot_prodv8qi): Renamed to... (udot_prodv2siv8qi): ...this. (usdot_prodv4hi): Renamed to... (usdot_prodv2siv4hi): ...this. (udot_prodv4hi): Renamed to... (udot_prodv2siv4hi): ...this. (sdot_prodv4hi): Renamed to... (sdot_prodv2siv4hi): ...this. * config/i386/sse.md (sdot_prod): Renamed to... (sdot_prod): ...this. (sdot_prodv4si): Renamed to... (sdot_prodv2div4si): ...this. (usdot_prod): Renamed to... (usdot_prod): ...this. (sdot_prod): Renamed to... (sdot_prod): ...this. (sdot_prodv64qi): Renamed to... (sdot_prodv16siv64qi): ...this. (udot_prod): Renamed to... (udot_prod): ...this. (udot_prodv64qi): Renamed to... (udot_prodv16qiv64qi): ...this. (usdot_prod): Renamed to... (usdot_prod): ...this. (udot_prod): Renamed to... (udot_prod): ...this. --- gcc/config/i386/mmx.md | 30 +++++++++++++++--------------- gcc/config/i386/sse.md | 38 +++++++++++++++++++------------------- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 94d3a6e5692..d78739b033d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -6344,7 +6344,7 @@ (define_expand "usadv8qi" DONE; }) -(define_expand "usdot_prodv8qi" +(define_expand "usdot_prodv2siv8qi" [(match_operand:V2SI 0 "register_operand") (match_operand:V8QI 1 "register_operand") (match_operand:V8QI 2 "register_operand") @@ -6363,7 +6363,7 @@ (define_expand "usdot_prodv8qi" rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode); rtx op0 = gen_reg_rtx (V4SImode); - emit_insn (gen_usdot_prodv16qi (op0, op1, op2, op3)); + emit_insn (gen_usdot_prodv4siv16qi (op0, op1, op2, op3)); emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); } else @@ -6377,7 +6377,7 @@ (define_expand "usdot_prodv8qi" emit_move_insn (op3, CONST0_RTX (V4SImode)); emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1])); emit_insn (gen_extendv8qiv8hi2 (op2, operands[2])); - emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3)); + emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3)); /* vec_perm (op0, 2, 3, 0, 1); */ emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78))); @@ -6388,7 +6388,7 @@ (define_expand "usdot_prodv8qi" DONE; }) -(define_expand "sdot_prodv8qi" +(define_expand "sdot_prodv2siv8qi" [(match_operand:V2SI 0 "register_operand") (match_operand:V8QI 1 "register_operand") (match_operand:V8QI 2 "register_operand") @@ -6406,7 +6406,7 @@ (define_expand "sdot_prodv8qi" rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode); rtx op0 = gen_reg_rtx (V4SImode); - emit_insn (gen_sdot_prodv16qi (op0, op1, op2, op3)); + emit_insn (gen_sdot_prodv4siv16qi (op0, op1, op2, op3)); emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); } else @@ -6420,7 +6420,7 @@ (define_expand "sdot_prodv8qi" emit_move_insn (op3, CONST0_RTX (V4SImode)); emit_insn (gen_extendv8qiv8hi2 (op1, operands[1])); emit_insn (gen_extendv8qiv8hi2 (op2, operands[2])); - emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3)); + emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3)); /* vec_perm (op0, 2, 3, 0, 1); */ emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78))); @@ -6432,7 +6432,7 @@ (define_expand "sdot_prodv8qi" }) -(define_expand "udot_prodv8qi" +(define_expand "udot_prodv2siv8qi" [(match_operand:V2SI 0 "register_operand") (match_operand:V8QI 1 "register_operand") (match_operand:V8QI 2 "register_operand") @@ -6450,7 +6450,7 @@ (define_expand "udot_prodv8qi" rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode); rtx op0 = gen_reg_rtx (V4SImode); - emit_insn (gen_udot_prodv16qi (op0, op1, op2, op3)); + emit_insn (gen_udot_prodv4siv16qi (op0, op1, op2, op3)); emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); } else @@ -6464,7 +6464,7 @@ (define_expand "udot_prodv8qi" emit_move_insn (op3, CONST0_RTX (V4SImode)); emit_insn (gen_zero_extendv8qiv8hi2 (op1, operands[1])); emit_insn (gen_zero_extendv8qiv8hi2 (op2, operands[2])); - emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3)); + emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3)); /* vec_perm (op0, 2, 3, 0, 1); */ emit_insn (gen_sse2_pshufd (op0_1, op0, GEN_INT (78))); @@ -6476,7 +6476,7 @@ (define_expand "udot_prodv8qi" }) -(define_expand "usdot_prodv4hi" +(define_expand "usdot_prodv2siv4hi" [(match_operand:V2SI 0 "register_operand") (match_operand:V4HI 1 "register_operand") (match_operand:V4HI 2 "register_operand") @@ -6492,12 +6492,12 @@ (define_expand "usdot_prodv4hi" rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode); rtx op0 = gen_reg_rtx (V4SImode); - emit_insn (gen_usdot_prodv8hi (op0, op1, op2, op3)); + emit_insn (gen_usdot_prodv4siv8hi (op0, op1, op2, op3)); emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); DONE; }) -(define_expand "udot_prodv4hi" +(define_expand "udot_prodv2siv4hi" [(match_operand:V2SI 0 "register_operand") (match_operand:V4HI 1 "register_operand") (match_operand:V4HI 2 "register_operand") @@ -6513,12 +6513,12 @@ (define_expand "udot_prodv4hi" rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode); rtx op0 = gen_reg_rtx (V4SImode); - emit_insn (gen_udot_prodv8hi (op0, op1, op2, op3)); + emit_insn (gen_udot_prodv4siv8hi (op0, op1, op2, op3)); emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); DONE; }) -(define_expand "sdot_prodv4hi" +(define_expand "sdot_prodv2siv4hi" [(match_operand:V2SI 0 "register_operand") (match_operand:V4HI 1 "register_operand") (match_operand:V4HI 2 "register_operand") @@ -6534,7 +6534,7 @@ (define_expand "sdot_prodv4hi" rtx op3 = lowpart_subreg (V4SImode, operands[3], V2SImode); rtx op0 = gen_reg_rtx (V4SImode); - emit_insn (gen_sdot_prodv8hi (op0, op1, op2, op3)); + emit_insn (gen_sdot_prodv4siv8hi (op0, op1, op2, op3)); emit_move_insn (operands[0], lowpart_subreg (V2SImode, op0, V4SImode)); DONE; }) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d1010bc5682..0bf250c86d9 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16727,7 +16727,7 @@ (define_mode_attr SDOT_PMADD_SUF (define_mode_attr SDOT_VPDP_SUF [(V32HI "v16si") (V16HI "v8si") (V8HI "v4si")]) -(define_expand "sdot_prod" +(define_expand "sdot_prod" [(match_operand: 0 "register_operand") (match_operand:VI2_AVX512VNNIBW 1 "register_operand") (match_operand:VI2_AVX512VNNIBW 2 "register_operand") @@ -16762,7 +16762,7 @@ (define_expand "sdot_prod" ;; Normally we use widen_mul_even/odd, but combine can't quite get it all ;; back together when madd is available. -(define_expand "sdot_prodv4si" +(define_expand "sdot_prodv2div4si" [(match_operand:V2DI 0 "register_operand") (match_operand:V4SI 1 "register_operand") (match_operand:V4SI 2 "register_operand") @@ -30190,7 +30190,7 @@ (define_insn "vpshldv__maskz_1" [(set_attr ("prefix") ("evex")) (set_attr "mode" "")]) -(define_expand "usdot_prod" +(define_expand "usdot_prod" [(match_operand: 0 "register_operand") (match_operand:VI1_AVX512 1 "register_operand") (match_operand:VI1_AVX512 2 "register_operand") @@ -30228,9 +30228,9 @@ (define_expand "usdot_prod" rtx sum = gen_reg_rtx (mode); emit_move_insn (sum, CONST0_RTX (mode)); - emit_insn (gen_sdot_prod (res1, op1_lo, + emit_insn (gen_sdot_prod (res1, op1_lo, op2_lo, sum)); - emit_insn (gen_sdot_prod (res2, op1_hi, + emit_insn (gen_sdot_prod (res2, op1_hi, op2_hi, operands[3])); emit_insn (gen_add3 (operands[0], res1, res2)); } @@ -31049,7 +31049,7 @@ (define_int_attr vpdotprodtype (UNSPEC_VPDPBSUD "bsud") (UNSPEC_VPDPBSUDS "bsuds") (UNSPEC_VPDPBUUD "buud") (UNSPEC_VPDPBUUDS "buuds")]) -(define_expand "sdot_prod" +(define_expand "sdot_prod" [(match_operand: 0 "register_operand") (match_operand:VI1_AVX2 1 "register_operand") (match_operand:VI1_AVX2 2 "register_operand") @@ -31085,9 +31085,9 @@ (define_expand "sdot_prod" rtx sum = gen_reg_rtx (mode); emit_move_insn (sum, CONST0_RTX (mode)); - emit_insn (gen_sdot_prod (res1, op1_lo, + emit_insn (gen_sdot_prod (res1, op1_lo, op2_lo, sum)); - emit_insn (gen_sdot_prod (res2, op1_hi, + emit_insn (gen_sdot_prod (res2, op1_hi, op2_hi, operands[3])); emit_insn (gen_add3 (operands[0], res1, res2)); } @@ -31095,7 +31095,7 @@ (define_expand "sdot_prod" DONE; }) -(define_expand "sdot_prodv64qi" +(define_expand "sdot_prodv16siv64qi" [(match_operand:V16SI 0 "register_operand") (match_operand:V64QI 1 "register_operand") (match_operand:V64QI 2 "register_operand") @@ -31118,14 +31118,14 @@ (define_expand "sdot_prodv64qi" rtx sum = gen_reg_rtx (V16SImode); emit_move_insn (sum, CONST0_RTX (V16SImode)); - emit_insn (gen_sdot_prodv32hi (res1, op1_lo, op2_lo, sum)); - emit_insn (gen_sdot_prodv32hi (res2, op1_hi, op2_hi, operands[3])); + emit_insn (gen_sdot_prodv16siv32hi (res1, op1_lo, op2_lo, sum)); + emit_insn (gen_sdot_prodv16siv32hi (res2, op1_hi, op2_hi, operands[3])); emit_insn (gen_addv16si3 (operands[0], res1, res2)); DONE; }) -(define_expand "udot_prod" +(define_expand "udot_prod" [(match_operand: 0 "register_operand") (match_operand:VI1_AVX2 1 "register_operand") (match_operand:VI1_AVX2 2 "register_operand") @@ -31161,9 +31161,9 @@ (define_expand "udot_prod" rtx sum = gen_reg_rtx (mode); emit_move_insn (sum, CONST0_RTX (mode)); - emit_insn (gen_sdot_prod (res1, op1_lo, + emit_insn (gen_sdot_prod (res1, op1_lo, op2_lo, sum)); - emit_insn (gen_sdot_prod (res2, op1_hi, + emit_insn (gen_sdot_prod (res2, op1_hi, op2_hi, operands[3])); emit_insn (gen_add3 (operands[0], res1, res2)); } @@ -31171,7 +31171,7 @@ (define_expand "udot_prod" DONE; }) -(define_expand "udot_prodv64qi" +(define_expand "udot_prodv16qiv64qi" [(match_operand:V16SI 0 "register_operand") (match_operand:V64QI 1 "register_operand") (match_operand:V64QI 2 "register_operand") @@ -31194,8 +31194,8 @@ (define_expand "udot_prodv64qi" rtx sum = gen_reg_rtx (V16SImode); emit_move_insn (sum, CONST0_RTX (V16SImode)); - emit_insn (gen_sdot_prodv32hi (res1, op1_lo, op2_lo, sum)); - emit_insn (gen_sdot_prodv32hi (res2, op1_hi, op2_hi, operands[3])); + emit_insn (gen_sdot_prodv16siv32hi (res1, op1_lo, op2_lo, sum)); + emit_insn (gen_sdot_prodv16siv32hi (res2, op1_hi, op2_hi, operands[3])); emit_insn (gen_addv16si3 (operands[0], res1, res2)); DONE; @@ -31301,7 +31301,7 @@ (define_int_attr vpdpwprodtype (UNSPEC_VPDPWSUD "wsud") (UNSPEC_VPDPWSUDS "wsuds") (UNSPEC_VPDPWUUD "wuud") (UNSPEC_VPDPWUUDS "wuuds")]) -(define_expand "usdot_prod" +(define_expand "usdot_prod" [(match_operand: 0 "register_operand") (match_operand:VI2_AVX2 1 "register_operand") (match_operand:VI2_AVX2 2 "register_operand") @@ -31319,7 +31319,7 @@ (define_expand "usdot_prod" DONE; }) -(define_expand "udot_prod" +(define_expand "udot_prod" [(match_operand: 0 "register_operand") (match_operand:VI2_AVX2 1 "register_operand") (match_operand:VI2_AVX2 2 "register_operand") From patchwork Tue Aug 13 12:41:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 1971946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(sdot_prodsiv2hi): ...this. (udot_prodv2hi): Renamed to... (udot_prodsiv2hi): ...this. (sdot_prodv4hi): Renamed to... (sdot_prodv2siv4hi): ...this. (udot_prodv4hi): Renamed to... (udot_prodv2siv4hi): ...this. --- gcc/config/arc/simdext.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index 4e51a237c3a..0696f0abb70 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -1643,7 +1643,7 @@ (define_insn "dmpyh" ;; We can use dmac as well here. To be investigated which version ;; brings more. -(define_expand "sdot_prodv2hi" +(define_expand "sdot_prodsiv2hi" [(match_operand:SI 0 "register_operand" "") (match_operand:V2HI 1 "register_operand" "") (match_operand:V2HI 2 "register_operand" "") @@ -1656,7 +1656,7 @@ (define_expand "sdot_prodv2hi" DONE; }) -(define_expand "udot_prodv2hi" +(define_expand "udot_prodsiv2hi" [(match_operand:SI 0 "register_operand" "") (match_operand:V2HI 1 "register_operand" "") (match_operand:V2HI 2 "register_operand" "") @@ -1669,7 +1669,7 @@ (define_expand "udot_prodv2hi" DONE; }) -(define_expand "sdot_prodv4hi" +(define_expand "sdot_prodv2siv4hi" [(match_operand:V2SI 0 "register_operand" "") (match_operand:V4HI 1 "register_operand" "") (match_operand:V4HI 2 "register_operand" "") @@ -1688,7 +1688,7 @@ (define_expand "sdot_prodv4hi" DONE; }) -(define_expand "udot_prodv4hi" +(define_expand "udot_prodv2siv4hi" [(match_operand:V2SI 0 "register_operand" "") (match_operand:V4HI 1 "register_operand" "") (match_operand:V4HI 2 "register_operand" "") From patchwork Tue Aug 13 12:41:47 2024 Content-Type: text/plain; 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(sdot_prodv2siv4hi): ...this. --- gcc/config/mips/loongson-mmi.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/mips/loongson-mmi.md b/gcc/config/mips/loongson-mmi.md index dd166bfa4c9..4d958730139 100644 --- a/gcc/config/mips/loongson-mmi.md +++ b/gcc/config/mips/loongson-mmi.md @@ -394,7 +394,7 @@ (define_insn "loongson_pmaddhw" "pmaddhw\t%0,%1,%2" [(set_attr "type" "fmul")]) -(define_expand "sdot_prodv4hi" +(define_expand "sdot_prodv2siv4hi" [(match_operand:V2SI 0 "register_operand" "") (match_operand:V4HI 1 "register_operand" "") (match_operand:V4HI 2 "register_operand" "") From patchwork Tue Aug 13 12:41:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 1971950 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=cqotB++p; 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(udot_prodv4si): ...this. (sdot_prodv8hi): Renamed to... (sdot_prodv4siv8hi): ...this. --- gcc/config/rs6000/altivec.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 1f5489b974f..0911c1792a8 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3698,7 +3698,7 @@ (define_expand "neg2" } }) -(define_expand "udot_prod" +(define_expand "udot_prodv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") (plus:V4SI (match_operand:V4SI 3 "register_operand" "v") (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v") @@ -3710,7 +3710,7 @@ (define_expand "udot_prod" DONE; }) -(define_expand "sdot_prodv8hi" +(define_expand "sdot_prodv4siv8hi" [(set (match_operand:V4SI 0 "register_operand" "=v") (plus:V4SI (match_operand:V4SI 3 "register_operand" "v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") From patchwork Tue Aug 13 12:41:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 1971945 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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(sdot_prodsiv2hi): ...this. --- gcc/config/c6x/c6x.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md index 5964dd69d0d..ea9ffe8b4e1 100644 --- a/gcc/config/c6x/c6x.md +++ b/gcc/config/c6x/c6x.md @@ -3082,7 +3082,7 @@ (define_insn "v2hi3" ;; Widening vector multiply and dot product. ;; See c6x-mult.md.in for the define_insn patterns -(define_expand "sdot_prodv2hi" +(define_expand "sdot_prodsiv2hi" [(match_operand:SI 0 "register_operand" "") (match_operand:V2HI 1 "register_operand" "") (match_operand:V2HI 2 "register_operand" "") From patchwork Tue Aug 13 12:41:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 1971953 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=YwQyWCLu; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024)(35042699022); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Aug 2024 13:03:07.8020 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7972a829-1a53-4bb4-677a-08dcbb9846ea X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A79A.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB5973 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Victor Do Nascimento Given the novel treatment of the dot product optab as a conversion, we are now able to targe different relationships between output modes and input modes. This is made clearer by way of example. Previously, on AArch64, the following loop was vectorizable: uint32_t udot4(int n, uint8_t* data) { uint32_t sum = 0; for (int i=0; i + +uint32_t udot4(int n, uint8_t* data) { + uint32_t sum = 0; + for (int i=0; i +#include + +uint32_t +udot2 (int n, uint16_t* data) __arm_streaming +{ + uint32_t sum = 0; + for (int i=0; i