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Tue, 13 Aug 2024 09:36:03 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5009C2004D; Tue, 13 Aug 2024 09:36:01 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 330B120040; Tue, 13 Aug 2024 09:35:59 +0000 (GMT) Received: from [9.200.158.244] (unknown [9.200.158.244]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 13 Aug 2024 09:35:58 +0000 (GMT) Message-ID: <6f2e9ff8-53b1-944d-17a3-ec3a2c1aca4d@linux.ibm.com> Date: Tue, 13 Aug 2024 17:35:57 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Content-Language: en-US To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner , Richard Sandiford , Michael Meissner From: "Kewen.Lin" Subject: [PATCH 1/2] rs6000: Fix vsx_le_perm_store_* splitters for !reload_completed X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: wakJhAm4Sm23SmBCSibVX3t0vXeJFNyM X-Proofpoint-GUID: tq1XaDVPzEeBnaMNL1BCbkF8HGXss5FD X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-13_02,2024-08-13_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 phishscore=0 mlxscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408130068 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, For vsx_le_perm_store_* we have two splitters, one is for !reload_completed and the other is for reload_completed. As Richard pointed out in [1], operand 1 here is a pure input for DF and most passes, but it could be used as the vector rotation (64 bit) destination of itself, so we re-compute the source (back to the original value) for the case reload_completed, while for !reload_completed we generate one new pseudo, so both cases are fine if operand 1 is still live after this insn. But according to the source code, for !reload_completed case, it can logically reuse the operand 1 as the new pseudo generation is conditional on can_create_pseudo_p, then it can cause wrong result once operand 1 is live. So considering this and there is no splitting for this when reload_in_progress, this patch is to fix the code to assert can_create_pseudo_p there, so that both !reload_completed and reload_completed cases would ensure operand 1 is unchanged (pure input), it is also prepared for the following up patch which would strip the unnecessary INOUT constraint modifier "+". This also fixes an oversight in the splitter for VSX_LE_128 (!reload_completed), it should use operand 1 rather than operand 0. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660145.html Bootstrapped and regtested on powerpc64-linux-gnu P8/P9 and powerpc64le-linux-gnu P9 and P10. I'm going to push this next week if no objections. BR, Kewen ----- gcc/ChangeLog: * config/rs6000/vsx.md (*vsx_le_perm_store_{,, v8hi,v16qi,} !reload_completed splitters): Assert can_create_pseudo_p and always generate one new pseudo for operand 1. --- gcc/config/rs6000/vsx.md | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) -- 2.39.1 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7892477fa92..9c9d2fb2bb4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -703,8 +703,8 @@ (define_split /* Otherwise, fall through to transform into a swapping store. */ } - operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) - : operands[1]; + gcc_assert (can_create_pseudo_p ()); + operands[2] = gen_reg_rtx_and_attrs (operands[1]); }) ;; The post-reload split requires that we re-permute the source @@ -775,8 +775,8 @@ (define_split /* Otherwise, fall through to transform into a swapping store. */ } - operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) - : operands[1]; + gcc_assert (can_create_pseudo_p ()); + operands[2] = gen_reg_rtx_and_attrs (operands[1]); }) ;; The post-reload split requires that we re-permute the source @@ -854,8 +854,8 @@ (define_split /* Otherwise, fall through to transform into a swapping store. */ } - operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) - : operands[1]; + gcc_assert (can_create_pseudo_p ()); + operands[2] = gen_reg_rtx_and_attrs (operands[1]); }) ;; The post-reload split requires that we re-permute the source @@ -947,8 +947,8 @@ (define_split /* Otherwise, fall through to transform into a swapping store. */ } - operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) - : operands[1]; + gcc_assert (can_create_pseudo_p ()); + operands[2] = gen_reg_rtx_and_attrs (operands[1]); }) ;; The post-reload split requires that we re-permute the source @@ -1076,9 +1076,8 @@ (define_split && !altivec_indexed_or_indirect_operand (operands[0], mode)" [(const_int 0)] { - rtx tmp = (can_create_pseudo_p () - ? gen_reg_rtx_and_attrs (operands[0]) - : operands[0]); + gcc_assert (can_create_pseudo_p ()); + rtx tmp = gen_reg_rtx_and_attrs (operands[1]); rs6000_emit_le_vsx_permute (tmp, operands[1], mode); rs6000_emit_le_vsx_permute (operands[0], tmp, mode); DONE; From patchwork Tue Aug 13 09:40:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kewen.Lin" X-Patchwork-Id: 1971863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=tLa1OqHx; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WjmcG4JrVz1yZl for ; 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Tue, 13 Aug 2024 09:40:58 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E520F2004D; Tue, 13 Aug 2024 09:40:55 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CB9092005A; Tue, 13 Aug 2024 09:40:53 +0000 (GMT) Received: from [9.200.158.244] (unknown [9.200.158.244]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 13 Aug 2024 09:40:53 +0000 (GMT) Message-ID: <302a12f9-e5bd-dd7f-6c22-8bc2c1f077b0@linux.ibm.com> Date: Tue, 13 Aug 2024 17:40:52 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: [PATCH 2/2] rs6000: Remove "+" constraint modifier from *vsx_le_perm_store_* insns Content-Language: en-US From: "Kewen.Lin" To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner , Richard Sandiford , Michael Meissner References: <6f2e9ff8-53b1-944d-17a3-ec3a2c1aca4d@linux.ibm.com> In-Reply-To: <6f2e9ff8-53b1-944d-17a3-ec3a2c1aca4d@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: gdy0wi5rPLIeCNlVjBPu5R6fdJjKYJVZ X-Proofpoint-GUID: 0A5eyXN_27uaQcX128y13bhDXizN8H0E X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-13_02,2024-08-13_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 mlxscore=0 suspectscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408130068 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, Since *vsx_le_perm_store_* can be split into vector permute and vector store, after reload_completed, we reuse the operand 1 as the destination of vector permute, so we set operand 1 with constraint modifier "+". But since it's taken as pure input in DF and most passes as Richard pointed out in [1], to ensure it's correct when operand 1 is still live, we actually restore the operand 1's value after the store with vector permute, that is: op1 = vector permute op1 (doubleword swapping) op0 = op2 op1 = vector permute op1 (doubleword swapping) , it means op1's value isn't changed by this insn. So according to the comments from Richard and Segher in that thread, this patch is to remove the "+" constraint modifier of operand 1 from *vsx_le_perm_store_* insns. [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-August/660145.html Bootstrapped and regtested on powerpc64-linux-gnu P8/P9 and powerpc64le-linux-gnu P9 and P10. I'm going to push this next week if no objections. BR, Kewen ----- gcc/ChangeLog: * config/rs6000/vsx.md (define_insn *vsx_le_perm_store_{, ,v8hi,v16qi,}): Remove constraint modifier "+" from operand 1. --- gcc/config/rs6000/vsx.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.39.1 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 9c9d2fb2bb4..af4f01e1f0e 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -659,7 +659,7 @@ (define_insn_and_split "*vsx_le_perm_load_v16qi" (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "=Z") - (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_D 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -729,7 +729,7 @@ (define_split (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_W 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -804,7 +804,7 @@ (define_split (define_insn "*vsx_le_perm_store_v8hi" [(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "=Z") - (match_operand:V8HI 1 "vsx_register_operand" "+wa"))] + (match_operand:V8HI 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -889,7 +889,7 @@ (define_split (define_insn "*vsx_le_perm_store_v16qi" [(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "=Z") - (match_operand:V16QI 1 "vsx_register_operand" "+wa"))] + (match_operand:V16QI 1 "vsx_register_operand" "wa"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "#" [(set_attr "type" "vecstore") @@ -1059,7 +1059,7 @@ (define_insn_and_split "*vsx_le_perm_load_" (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_LE_128 0 "memory_operand" "=Z,Q") - (match_operand:VSX_LE_128 1 "vsx_register_operand" "+wa,r"))] + (match_operand:VSX_LE_128 1 "vsx_register_operand" "wa,r"))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !altivec_indexed_or_indirect_operand (operands[0], mode)" "@