From patchwork Sun Aug 11 10:43:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1971261 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HiEdHPWS; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WhZ5B5MTjz1yXh for ; Sun, 11 Aug 2024 20:43:58 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 087613858C52 for ; Sun, 11 Aug 2024 10:43:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by sourceware.org (Postfix) with ESMTPS id 4149F3858D34 for ; Sun, 11 Aug 2024 10:43:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4149F3858D34 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4149F3858D34 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723373017; cv=none; b=XzUSQrrXUsqb6vWPdNHQqa5Kuvue803z+sfKq4KhgyJzOd4Lxgxvfc/GHl9KQgHDs/ww8b2DRmbabRiRy7RSdfpV4ZjTzR0WMLeMNp9XpYguAc9uE1VxdxB0gMplGWDkp+M/ErgTRNFpiodOLHa10W23L7a4aKqUAa7GTSihsdk= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723373017; c=relaxed/simple; bh=MZ5kCqhZuMB2XzOGe7mnKSdNzGi+JUXj2b0YXHkygcY=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=quBVcf269KA+7XGJ2bNt9TE2fJ7PoaWxwAlgVPIM2//eZlWHy0qs3QQJJAefcQLR6LOYTQ7gsi6sWA4fqkmBoe2dnIVQoWPfGRIMbQHH+/8DAzSbYCscR5xHLwGOJuHrzZ0QGNP4lVYoMIPWSmiGLtO7kQRiBRnZ7d0nGJGbNjE= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723373015; x=1754909015; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MZ5kCqhZuMB2XzOGe7mnKSdNzGi+JUXj2b0YXHkygcY=; b=HiEdHPWSnm65ReZ9MRiYq6b7V/Z9gevKu7bqexo1yYmZ2jdD+tYmhr9z VrfWEgvqjgbnMlg/q23swdPmHKjrXHgorA22cl9kjmroy3WxeOr9ZK9gU FtAjGhOqEiy20yMumzRsZsVUR0IfqZsnlKRW2BUrp1wjd/2NtQoYQ3q6o DNZTcylEFNhgWuyO58K7w6jbyaZX5TewKyRtIYhBWhw+YDJ6X2/IqeQs1 R9l2zHkSS+zOlBuRjahXNBOpukVI1XTvB9ugh0ZPeKks4hlDcrl7iPUhM R9esUIyLeRp71MO4eCmmVaDwOzuWTf2HefNHJlRGGuZKqs/8bSCJwCDSz g==; X-CSE-ConnectionGUID: 0jP7oSzGStut30UcSZT1tw== X-CSE-MsgGUID: PWJg4KVeS8emr9OuZ7NfVQ== X-IronPort-AV: E=McAfee;i="6700,10204,11160"; a="21633597" X-IronPort-AV: E=Sophos;i="6.09,281,1716274800"; d="scan'208";a="21633597" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Aug 2024 03:43:33 -0700 X-CSE-ConnectionGUID: LKLYcQRYQc6JiQkB3FMCWg== X-CSE-MsgGUID: smYf/NRySyu1aCuljoOa2w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,281,1716274800"; d="scan'208";a="58557837" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orviesa007.jf.intel.com with ESMTP; 11 Aug 2024 03:43:32 -0700 Received: from panli.sh.intel.com (panli.sh.intel.com [10.239.154.73]) by shvmail02.sh.intel.com (Postfix) with ESMTP id BC36710071C4; Sun, 11 Aug 2024 18:43:30 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v2] RISC-V: Make sure high bits of usadd operands is clean for HI/QI [PR116278] Date: Sun, 11 Aug 2024 18:43:17 +0800 Message-ID: <20240811104317.531505-1-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li For QI/HImode of .SAT_ADD, the operands may be sign-extended and the high bits of Xmode may be all 1 which is not expected. For example as below code. signed char b[1]; unsigned short c; signed char *d = b; int main() { b[0] = -40; c = ({ (unsigned short)d[0] < 0xFFF6 ? (unsigned short)d[0] : 0xFFF6; }) + 9; __builtin_printf("%d\n", c); } After expanding we have: ;; _6 = .SAT_ADD (_3, 9); (insn 8 7 9 (set (reg:DI 143) (high:DI (symbol_ref:DI ("d") [flags 0x86] ))) (nil)) (insn 9 8 10 (set (reg/f:DI 142) (mem/f/c:DI (lo_sum:DI (reg:DI 143) (symbol_ref:DI ("d") [flags 0x86] )) [1 d+0 S8 A64])) (nil)) (insn 10 9 11 (set (reg:HI 144 [ _3 ]) (sign_extend:HI (mem:QI (reg/f:DI 142) [0 *d.0_1+0 S1 A8]))) "test.c":7:10 -1 (nil)) The convert from signed char to unsigned short will have sign_extend rtl as above. And finally become the lb insn as below: lb a1,0(a5) // a1 is -40, aka 0xffffffffffffffd8 lui a0,0x1a addi a5,a1,9 slli a5,a5,0x30 srli a5,a5,0x30 // a5 is 65505 sltu a1,a5,a1 // compare 65505 and 0xffffffffffffffd8 => TRUE The sltu try to compare 65505 and 0xffffffffffffffd8 here, but we actually want to compare 65505 and 65496 (0xffd8). Thus we need to clean up the high bits to ensure this. The below test suites are passed for this patch: * The rv64gcv fully regression test. PR target/116278 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Add new func impl to zero extend rtx. (riscv_expand_usadd): Leverage above func to cleanup operands and sum. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr116278-run-1.c: New test. Signed-off-by: Pan Li --- gcc/config/riscv/riscv.cc | 19 ++++++++++++++++++- .../gcc.target/riscv/pr116278-run-1.c | 16 ++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr116278-run-1.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5fe4273beb7..cfdb3d82972 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11564,6 +11564,23 @@ riscv_get_raw_result_mode (int regno) return default_get_reg_raw_mode (regno); } +/* Generate a new rtx of Xmode based on the rtx and mode in define pattern. + The rtx x will be zero extended to Xmode if the mode is HI/QImode, and + the new zero extended Xmode rtx will be returned. + Or the gen_lowpart rtx of Xmode will be returned. */ + +static rtx +riscv_gen_zero_extend_rtx (rtx x, machine_mode mode) +{ + if (mode != HImode && mode != QImode) + return gen_lowpart (Xmode, x); + + rtx xmode_reg = gen_reg_rtx (Xmode); + riscv_emit_unary (ZERO_EXTEND, xmode_reg, x); + + return xmode_reg; +} + /* Implements the unsigned saturation add standard name usadd for int mode. z = SAT_ADD(x, y). @@ -11580,7 +11597,7 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) machine_mode mode = GET_MODE (dest); rtx xmode_sum = gen_reg_rtx (Xmode); rtx xmode_lt = gen_reg_rtx (Xmode); - rtx xmode_x = gen_lowpart (Xmode, x); + rtx xmode_x = riscv_gen_zero_extend_rtx (x, mode); rtx xmode_y = gen_lowpart (Xmode, y); rtx xmode_dest = gen_reg_rtx (Xmode); diff --git a/gcc/testsuite/gcc.target/riscv/pr116278-run-1.c b/gcc/testsuite/gcc.target/riscv/pr116278-run-1.c new file mode 100644 index 00000000000..f6268e290ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr116278-run-1.c @@ -0,0 +1,16 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +signed char b[1]; +int c; +signed char *d = b; + +int main() { + b[0] = -40; + c = ({ + (unsigned short)d[0] < 0xFFF6 ? (unsigned short)d[0] : 0xFFF6; + }) + 9; + + if (c != 65505) + __builtin_abort (); +}