From patchwork Sun Aug 11 05:56:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 1971232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20230601 header.b=dYnUQZ2Y; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WhRjp6C7mz1yYl for ; Sun, 11 Aug 2024 15:56:46 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A3F493858D34 for ; Sun, 11 Aug 2024 05:56:44 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by sourceware.org (Postfix) with ESMTPS id 1FE573858D26 for ; Sun, 11 Aug 2024 05:56:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1FE573858D26 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 1FE573858D26 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::633 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723355790; cv=none; b=fCUzWHboI8XdIe5sDMv+3v297FrnWwPRPA28XjnzGXNuDj166brZTqDaP2dZ2sfSiZWuW9h50+6KFT9PYGm1tpg//u4lR4FBuE2ceh45EQ2US6tf/eF+qy/T8Ez2qLe/qBO9bRf7FI3GwVLW5i3miZhy2xkiuOrcc3CCZEMf5ac= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723355790; c=relaxed/simple; bh=qZuxAqGssAUTp9iKm0+4YN1tV/mh5KV5VVR2pVTUppk=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qO5EUSOtKo/EJn2GYHvl5rHBBSjUPrXgGxMC7KZf/BrBD4jjDnzcrfwWbt7xVLsu0ar96HpVwd9hnswwHmCfyJytQHKyTaHVfnO1NYB5u4C9Hhtq+Dhf9nVu79I4aaQn8R9ISuhP8fXt7FzOO0dOkeofldSyp3h+WlDEUDVALDg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a7aa086b077so310585066b.0 for ; Sat, 10 Aug 2024 22:56:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1723355786; x=1723960586; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zb5wAvJwnQPf4lJueluLtoFq6wogutFG/3a0pFnh8Ec=; b=dYnUQZ2YZQ3RSed2Bo8GN6EowwXQZn/zT892PpQoQOdBV4WSSo9WTqgDQt/osgDuWh YiK7KiJkXRp8k4o/yOkMBBcKc92obY7YxWkOBGzW4ns19nz8wGZp3y5g8zYfdEisPBjk fLvDbIPdPrjZEyjvS8RtBgxRe+JvPtqq3zjovlKNTQYUrRGSFduxCIe+c2bQC04KOPfM 6fMjdukBTRl/mgvsCGYc3t1VEr++2CQTny3peUlzJheabTKBAAZlSWRuxzJThgCHevcY MWvsPJ0eIje212wmYxYiexzZOj3erd1uLOHaMghPvLIB5uJwKLpCQI0llNGvJoeYmAui nK6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723355786; x=1723960586; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zb5wAvJwnQPf4lJueluLtoFq6wogutFG/3a0pFnh8Ec=; b=HSlIAnnP/EAfTOvllfe45dTLdB5k76IzwuNbYiQ1jW2ITc2hCaJSH4AMw9WBe1BTfi B7CKV6liyiV3FgLmZJ5HCAwKpnXGEy5Bph2RnWtico0PDHDpiw/J201TpcHBbbGJVbck gaL+JY23rBdN/q4kP4uw/6rcEDFmPQiBEcZeFXKgDaqvEFoDwTTzr6VmPU7qU1BJaLgN o/SvrOtBEQqUs158ZtJRXs8882nLbD7884H0oV6GejZqnaNgvIuOI5N1XsX+eLsb2xhd uysab44+ihjkfaKr/fV2JMim1JvbWh8hC9L+soHzt7yJCeqUZYRTyLcpF0vB5jSV48cG H6jg== X-Gm-Message-State: AOJu0YxFWghi7vth+wmjizwXNWBewNhSfV50HA7uOWPLPtZdPuGAfWMO /LYEjkDWBZT43XCFl64rO8q17MT2meuPXeSgJd3q6mNvd5GMmyBKIrANxys2 X-Google-Smtp-Source: AGHT+IF2PfxexoPQPPDC+lyVyiGgeQFwDKBt9yRRPIdNjDcwT4eoP9Xsl07ir1AC1Ik/5BVeRXzmfQ== X-Received: by 2002:a17:907:d584:b0:a7a:9f0f:ab14 with SMTP id a640c23a62f3a-a80aa5ebb23mr398038866b.33.1723355785581; Sat, 10 Aug 2024 22:56:25 -0700 (PDT) Received: from noahgold-desk.. ([185.209.199.109]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a80bb2136d1sm120805066b.155.2024.08.10.22.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Aug 2024 22:56:25 -0700 (PDT) From: Noah Goldstein To: libc-alpha@sourceware.org Cc: goldstein.w.n@gmail.com, hjl.tools@gmail.com, carlos@systemhalted.org Subject: [PATCH v2] x86: Add new cpu-flag `Prefer_Non_Temporal` Date: Sun, 11 Aug 2024 13:56:19 +0800 Message-Id: <20240811055619.2863839-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240710065226.2509525-1-goldstein.w.n@gmail.com> References: <20240710065226.2509525-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org The goal of this flag is to allow targets which don't prefer/have ERMS to still access the non-temporal memset implementation. --- sysdeps/x86/cpu-tunables.c | 2 ++ sysdeps/x86/dl-cacheinfo.h | 32 ++++++++++++++++--- ...cpu-features-preferred_feature_index_1.def | 1 + sysdeps/x86/tst-hwcap-tunables.c | 6 ++-- sysdeps/x86_64/multiarch/ifunc-memset.h | 15 ++++++--- 5 files changed, 45 insertions(+), 11 deletions(-) diff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c index ccc6b64dc2..789646ba26 100644 --- a/sysdeps/x86/cpu-tunables.c +++ b/sysdeps/x86/cpu-tunables.c @@ -223,6 +223,8 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp) Fast_Unaligned_Load, 19); CHECK_GLIBC_IFUNC_PREFERRED_BOTH (n, cpu_features, Fast_Unaligned_Copy, 19); + CHECK_GLIBC_IFUNC_PREFERRED_BOTH (n, cpu_features, + Prefer_Non_Temporal, 19); } break; case 20: diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h index a1c03b8903..b8ba0c098d 100644 --- a/sysdeps/x86/dl-cacheinfo.h +++ b/sysdeps/x86/dl-cacheinfo.h @@ -992,7 +992,8 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) non_temporal_threshold. Enable this for both Intel and AMD hardware. */ unsigned long int memset_non_temporal_threshold = SIZE_MAX; if (!CPU_FEATURES_ARCH_P (cpu_features, Avoid_Non_Temporal_Memset) - && (cpu_features->basic.kind == arch_kind_intel + && (CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal) + || cpu_features->basic.kind == arch_kind_intel || cpu_features->basic.kind == arch_kind_amd)) memset_non_temporal_threshold = non_temporal_threshold; @@ -1042,14 +1043,37 @@ dl_init_cacheinfo (struct cpu_features *cpu_features) slightly better than ERMS. */ rep_stosb_threshold = SIZE_MAX; + /* + For memset, the non-temporal implementation is only accessed through the + stosb code. ie: + ``` + if (size >= rep_stosb_thresh) + { + if (size >= non_temporal_thresh) + { + do_non_temporal (); + } + do_stosb (); + } + do_normal_vec_loop (); + ``` + So if we prefer non-temporal, set `rep_stosb_thresh = non_temporal_thresh` + to enable the implementation. If `rep_stosb_thresh = non_temporal_thresh`, + `rep stosb` will never be used. + */ + TUNABLE_SET_WITH_BOUNDS (x86_memset_non_temporal_threshold, + memset_non_temporal_threshold, + minimum_non_temporal_threshold, SIZE_MAX); + if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal)) + rep_stosb_threshold + = TUNABLE_GET (x86_memset_non_temporal_threshold, long int, NULL); + + TUNABLE_SET_WITH_BOUNDS (x86_data_cache_size, data, 0, SIZE_MAX); TUNABLE_SET_WITH_BOUNDS (x86_shared_cache_size, shared, 0, SIZE_MAX); TUNABLE_SET_WITH_BOUNDS (x86_non_temporal_threshold, non_temporal_threshold, minimum_non_temporal_threshold, maximum_non_temporal_threshold); - TUNABLE_SET_WITH_BOUNDS (x86_memset_non_temporal_threshold, - memset_non_temporal_threshold, - minimum_non_temporal_threshold, SIZE_MAX); TUNABLE_SET_WITH_BOUNDS (x86_rep_movsb_threshold, rep_movsb_threshold, minimum_rep_movsb_threshold, SIZE_MAX); TUNABLE_SET_WITH_BOUNDS (x86_rep_stosb_threshold, rep_stosb_threshold, 1, diff --git a/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def b/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def index 61bbbc2e89..f15344a8be 100644 --- a/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def +++ b/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def @@ -34,3 +34,4 @@ BIT (MathVec_Prefer_No_AVX512) BIT (Prefer_FSRM) BIT (Avoid_Short_Distance_REP_MOVSB) BIT (Avoid_Non_Temporal_Memset) +BIT (Prefer_Non_Temporal) \ No newline at end of file diff --git a/sysdeps/x86/tst-hwcap-tunables.c b/sysdeps/x86/tst-hwcap-tunables.c index 94307283d7..b33e0e92f4 100644 --- a/sysdeps/x86/tst-hwcap-tunables.c +++ b/sysdeps/x86/tst-hwcap-tunables.c @@ -60,7 +60,8 @@ static const struct test_t /* Disable everything. */ "-Prefer_ERMS,-Prefer_FSRM,-AVX,-AVX2,-AVX512F,-AVX512VL," "-SSE4_1,-SSE4_2,-SSSE3,-Fast_Unaligned_Load,-ERMS," - "-AVX_Fast_Unaligned_Load,-Avoid_Non_Temporal_Memset", + "-AVX_Fast_Unaligned_Load,-Avoid_Non_Temporal_Memset," + "-Prefer_Non_Temporal", test_1, array_length (test_1) }, @@ -68,7 +69,8 @@ static const struct test_t /* Same as before, but with some empty suboptions. */ ",-,-Prefer_ERMS,-Prefer_FSRM,-AVX,-AVX2,-AVX512F,-AVX512VL," "-SSE4_1,-SSE4_2,-SSSE3,-Fast_Unaligned_Load,,-," - "-ERMS,-AVX_Fast_Unaligned_Load,-Avoid_Non_Temporal_Memset,-,", + "-ERMS,-AVX_Fast_Unaligned_Load,-Avoid_Non_Temporal_Memset," + "-Prefer_Non_Temporal,-,", test_1, array_length (test_1) } diff --git a/sysdeps/x86_64/multiarch/ifunc-memset.h b/sysdeps/x86_64/multiarch/ifunc-memset.h index 7a637ef7ca..27f04e9dce 100644 --- a/sysdeps/x86_64/multiarch/ifunc-memset.h +++ b/sysdeps/x86_64/multiarch/ifunc-memset.h @@ -61,7 +61,8 @@ IFUNC_SELECTOR (void) && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)) { - if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) + if (CPU_FEATURE_USABLE_P (cpu_features, ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal)) return OPTIMIZE (avx512_unaligned_erms); return OPTIMIZE (avx512_unaligned); @@ -76,7 +77,8 @@ IFUNC_SELECTOR (void) && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)) { - if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) + if (CPU_FEATURE_USABLE_P (cpu_features, ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal)) return OPTIMIZE (evex_unaligned_erms); return OPTIMIZE (evex_unaligned); @@ -84,7 +86,8 @@ IFUNC_SELECTOR (void) if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) { - if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) + if (CPU_FEATURE_USABLE_P (cpu_features, ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal)) return OPTIMIZE (avx2_unaligned_erms_rtm); return OPTIMIZE (avx2_unaligned_rtm); @@ -93,14 +96,16 @@ IFUNC_SELECTOR (void) if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER, !)) { - if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) + if (CPU_FEATURE_USABLE_P (cpu_features, ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal)) return OPTIMIZE (avx2_unaligned_erms); return OPTIMIZE (avx2_unaligned); } } - if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) + if (CPU_FEATURE_USABLE_P (cpu_features, ERMS) + || CPU_FEATURES_ARCH_P (cpu_features, Prefer_Non_Temporal)) return OPTIMIZE (sse2_unaligned_erms); return OPTIMIZE (sse2_unaligned);