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Fri, 9 Aug 2024 09:50:26 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F2CF120040; Fri, 9 Aug 2024 09:50:23 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 55A632004B; Fri, 9 Aug 2024 09:50:21 +0000 (GMT) Received: from [9.197.239.15] (unknown [9.197.239.15]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 9 Aug 2024 09:50:20 +0000 (GMT) Message-ID: Date: Fri, 9 Aug 2024 17:50:18 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Content-Language: en-US To: GCC Patches Cc: Segher Boessenkool , David Edelsohn , Peter Bergner From: "Kewen.Lin" Subject: [PATCH] rs6000: Add TARGET_P10_VECTOR for Power10 vector insns [PR116266] X-TM-AS-GCONF: 00 X-Proofpoint-GUID: vGsPZ8lTRWBbTUv9ws9pDjjpoYSGA0ap X-Proofpoint-ORIG-GUID: w7nfGogc_al7431ac3zCJgZX8LekNtxn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-09_06,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 spamscore=0 mlxscore=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408090070 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, As PR116266 shows, we miss TARGET_P10_VECTOR to guard those Power10 related vector instructions as well as their according built-in functions. This patch is to introduce TARGET_P10_VECTOR which is actually TARGET_POWER10 && TARGET_VSX underlying, it updates many places that should adopt TARGET_P10_VECTOR rather than TARGET_POWER10. It also replaces the existing power10 stanza with power10-vector since all built-ins under it are all vector related. When making this patch, I noticed there are several places which need extra fixing, like xxswapd_v1ti which shouldn't use TARGET_POWER10, define floatti2 etc. which actually needs TARGET_FLOAT128_HW and so on, I'll make separated patches for them soon. Bootstrapped and regtested on powerpc64-linux-gnu P8/P9 and powerpc64le-linux-gnu P9 and P10. I'm going to push this next week late if no objections. BR, Kewen ----- PR target/116266 gcc/ChangeLog: * config/rs6000/altivec.md (define_insn altivec_eqv1ti, *altivec_gtv1ti, *altivec_gtuv1ti, vsdb_, vstrir_direct_, vstrir_p_direct_, vstril_direct_, vstril_p_direct_, altivec_vmuleud, altivec_vmuloud, altivec_vmulesd, altivec_vmulosd, altivec_vrlq, altivec_vrlqmi_inst, altivec_vrlqnm_inst, altivec_vslq_, altivec_vsrq_, altivec_vsraq, altivec_vcmpequt_p, *altivec_vcmpgtst_p, *altivec_vcmpgtut_p, vcfuged, vclzdm, vctzdm, vpdepd, vpextd, vgnb, vclrlb, vclrrb): Replace condition TARGET_POWER10 with TARGET_P10_VECTOR. (define_expand vstrir_, vstrir_p_, vstril_, vstril_p_, vec_widen_umult_even_v2di, vec_widen_smult_even_v2di, vec_widen_umult_odd_v2di, vec_widen_smult_odd_v2di, altivec_vrlqmi, altivec_vrlqnm): Likewise. * config/rs6000/predicates.md (define_predicate easy_fp_constant, easy_vector_constant): Replace TARGET_POWER10 with TARGET_P10_VECTOR. (define_predicate easy_vector_constant_ieee128): Replace !TARGET_POWER10 || !TARGET_VSX with !TARGET_P10_VECTOR. * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Remove the handling for case ENB_P10, add the handling for case ENB_P10V. (rs6000_builtin_is_supported): Likewise. (rs6000_builtin_md_vectorized_function): Replace TARGET_POWER10 with TARGET_P10_VECTOR. * config/rs6000/rs6000-builtins.def: Replace stanza [power10] with [power10-vector]. * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Remove BSTZ_P10 and add BSTZ_P10V. (stanza_map): Remove entry for power10 and add an entry for power10-vector. (enable_string): Remove ENB_P10 and add ENB_P10V. (write_decls): Remove print for ENB_P10 and add print for ENB_P10V. * config/rs6000/rs6000-string.cc (expand_block_move): Replace TARGET_POWER10 with TARGET_P10_VECTOR for lxvl and stxvl. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace TARGET_POWER10 with TARGET_P10_VECTOR for condition of setting param_vect_partial_vector_usage (output_vec_const_move): Replace TARGET_POWER10 with TARGET_P10_VECTOR. (constant_generates_lxvkq): Likewise. * config/rs6000/rs6000.h (TARGET_P10_VECTOR): New define. * config/rs6000/rs6000.md (define_attr isa): Add p10v. (define_insn udivti3, divti3, umodti3, modti3, xxspltidp__internal, xxspltiw__internal, xxspltiw__internal): Replace TARGET_POWER10 with TARGET_P10_VECTOR. * config/rs6000/vector.md (mode_iterator VEC_IC): Replace TARGET_POWER10 with TARGET_P10_VECTOR. (vector_eq_v1ti_p, vector_ne_v1ti_p, vector_ae_v1ti_p, vector_gt_v1ti_p, vashl3, vlshr3): Replace TARGET_POWER10 with TARGET_P10_VECTOR. * config/rs6000/vsx.md (vsx_mov_64bit, *vsx_mov_32bit): Replace isa attr p10 with p10v. (define_expand vsx_store_, xvtlsbbo, xvtlsbbz, xxgenpcvm_, vextractl, vextractr, vinsertvl_, vinsertvr_, vinsertgl_, vinsertgr_, vreplace_elt_, vcmpnet, xxspltiw_v4sf, xxspltidp_v2df, xxsplti32dx_v4si, xxsplti32dx_v4sf, xxpermx): Replace condition TARGET_POWER10 with TARGET_P10_VECTOR. (define_insn vsx_lxvrx, vsx_stxvrx, vsx_div_v1ti, vsx_udiv_v1ti, vsx_dives_v1ti, vsx_diveu_v1ti, vsx_mods_v1ti, vsx_modu_v1ti, *xvtlsbb_internal, xxgenpcvm__internal, vextractl_internal, vextractr_internal, vinsertvl_internal_, vinsertvr_internal_, vinsertgl_internal_, vinsertgr_internal_, vreplace_elt__inst, vreplace_un_, vsx_sign_extend_v2di_v1ti, extendditi2_vector, vsx_, vec_mtvsrbmi, vec_mtvsr_, vec_cntmb_, vec_extract_, vec_expand_, dives_, diveu_, div3, udiv3, mod3, umod3, smul3_highpart, umul3_highpart, mulv2di3, xxspltiw_v4si, xxspltiw_v4sf_inst, xxspltidp_v2df_inst, xxsplti32dx_v4si_inst, xxsplti32dx_v4sf_inst, xxblend_, xxpermx_inst, xxeval, vmsumcud): Likewise. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr116266.c: New test. --- gcc/config/rs6000/altivec.md | 78 ++++++------ gcc/config/rs6000/predicates.md | 7 +- gcc/config/rs6000/rs6000-builtin.cc | 13 +- gcc/config/rs6000/rs6000-builtins.def | 3 +- gcc/config/rs6000/rs6000-gen-builtins.cc | 8 +- gcc/config/rs6000/rs6000-string.cc | 2 +- gcc/config/rs6000/rs6000.cc | 8 +- gcc/config/rs6000/rs6000.h | 3 + gcc/config/rs6000/rs6000.md | 20 ++-- gcc/config/rs6000/vector.md | 14 +-- gcc/config/rs6000/vsx.md | 124 ++++++++++---------- gcc/testsuite/gcc.target/powerpc/pr116266.c | 14 +++ 12 files changed, 158 insertions(+), 136 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr116266.c -- 2.45.2 diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index aa9d8fffc90..e8495bf4c63 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -623,7 +623,7 @@ (define_insn "altivec_eqv1ti" [(set (match_operand:V1TI 0 "altivec_register_operand" "=v") (eq:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v") (match_operand:V1TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcmpequq %0,%1,%2" [(set_attr "type" "veccmpfx")]) @@ -647,7 +647,7 @@ (define_insn "*altivec_gtv1ti" [(set (match_operand:V1TI 0 "altivec_register_operand" "=v") (gt:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v") (match_operand:V1TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcmpgtsq %0,%1,%2" [(set_attr "type" "veccmpfx")]) @@ -663,7 +663,7 @@ (define_insn "*altivec_gtuv1ti" [(set (match_operand:V1TI 0 "altivec_register_operand" "=v") (gtu:V1TI (match_operand:V1TI 1 "altivec_register_operand" "v") (match_operand:V1TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcmpgtuq %0,%1,%2" [(set_attr "type" "veccmpfx")]) @@ -882,7 +882,7 @@ (define_insn "vsdb_" (match_operand:VI2 2 "register_operand" "v") (match_operand:QI 3 "const_0_to_12_operand" "n")] VSHIFT_DBL_LR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vsdbi %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) @@ -890,7 +890,7 @@ (define_expand "vstrir_" [(set (match_operand:VIshort 0 "altivec_register_operand") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] UNSPEC_VSTRIR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vstrir_direct_ (operands[0], operands[1])); @@ -904,7 +904,7 @@ (define_insn "vstrir_direct_" (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vstrir %0,%1" [(set_attr "type" "vecsimple")]) @@ -915,7 +915,7 @@ (define_insn "vstrir_direct_" (define_expand "vstrir_p_" [(match_operand:SI 0 "gpc_reg_operand") (match_operand:VIshort 1 "altivec_register_operand")] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { rtx scratch = gen_reg_rtx (mode); if (BYTES_BIG_ENDIAN) @@ -934,7 +934,7 @@ (define_insn "vstrir_p_direct_" (set (reg:CC CR6_REGNO) (unspec:CC [(match_dup 1)] UNSPEC_VSTRIR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vstrir. %0,%1" [(set_attr "type" "vecsimple")]) @@ -942,7 +942,7 @@ (define_expand "vstril_" [(set (match_operand:VIshort 0 "altivec_register_operand") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] UNSPEC_VSTRIR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vstril_direct_ (operands[0], operands[1])); @@ -956,7 +956,7 @@ (define_insn "vstril_direct_" (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vstril %0,%1" [(set_attr "type" "vecsimple")]) @@ -967,7 +967,7 @@ (define_insn "vstril_direct_" (define_expand "vstril_p_" [(match_operand:SI 0 "gpc_reg_operand") (match_operand:VIshort 1 "altivec_register_operand")] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { rtx scratch = gen_reg_rtx (mode); if (BYTES_BIG_ENDIAN) @@ -986,7 +986,7 @@ (define_insn "vstril_p_direct_" (set (reg:CC CR6_REGNO) (unspec:CC [(match_dup 1)] UNSPEC_VSTRIR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vstril. %0,%1" [(set_attr "type" "vecsimple")]) @@ -1614,7 +1614,7 @@ (define_expand "vec_widen_umult_even_v2di" [(use (match_operand:V1TI 0 "register_operand")) (use (match_operand:V2DI 1 "register_operand")) (use (match_operand:V2DI 2 "register_operand"))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_altivec_vmuleud (operands[0], operands[1], operands[2])); @@ -1640,7 +1640,7 @@ (define_expand "vec_widen_smult_even_v2di" [(use (match_operand:V1TI 0 "register_operand")) (use (match_operand:V2DI 1 "register_operand")) (use (match_operand:V2DI 2 "register_operand"))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_altivec_vmulesd (operands[0], operands[1], operands[2])); @@ -1718,7 +1718,7 @@ (define_expand "vec_widen_umult_odd_v2di" [(use (match_operand:V1TI 0 "register_operand")) (use (match_operand:V2DI 1 "register_operand")) (use (match_operand:V2DI 2 "register_operand"))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_altivec_vmuloud (operands[0], operands[1], operands[2])); @@ -1744,7 +1744,7 @@ (define_expand "vec_widen_smult_odd_v2di" [(use (match_operand:V1TI 0 "register_operand")) (use (match_operand:V2DI 1 "register_operand")) (use (match_operand:V2DI 2 "register_operand"))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_altivec_vmulosd (operands[0], operands[1], operands[2])); @@ -1839,7 +1839,7 @@ (define_insn "altivec_vmuleud" (unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v") (match_operand:V2DI 2 "register_operand" "v")] UNSPEC_VMULEUD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmuleud %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -1857,7 +1857,7 @@ (define_insn "altivec_vmuloud" (unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v") (match_operand:V2DI 2 "register_operand" "v")] UNSPEC_VMULOUD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmuloud %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -1875,7 +1875,7 @@ (define_insn "altivec_vmulesd" (unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v") (match_operand:V2DI 2 "register_operand" "v")] UNSPEC_VMULESD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmulesd %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -1893,7 +1893,7 @@ (define_insn "altivec_vmulosd" (unspec:V1TI [(match_operand:V2DI 1 "register_operand" "v") (match_operand:V2DI 2 "register_operand" "v")] UNSPEC_VMULOSD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmulosd %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -1994,7 +1994,7 @@ (define_insn "altivec_vrlq" [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") (rotate:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" ;; rotate amount in needs to be in bits[57:63] of operand2. "vrlq %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -2015,7 +2015,7 @@ (define_expand "altivec_vrlqmi" (match_operand:V1TI 2 "vsx_register_operand") (match_operand:V1TI 3 "vsx_register_operand")] UNSPEC_VRLMI))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { /* Mask bit begin, end fields need to be in bits [41:55] of 128-bit operand2. Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */ @@ -2033,7 +2033,7 @@ (define_insn "altivec_vrlqmi_inst" (match_operand:V1TI 2 "vsx_register_operand" "0") (match_operand:V1TI 3 "vsx_register_operand" "v")] UNSPEC_VRLMI))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vrlqmi %0,%1,%3" [(set_attr "type" "veclogical")]) @@ -2051,7 +2051,7 @@ (define_expand "altivec_vrlqnm" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand") (match_operand:V1TI 2 "vsx_register_operand")] UNSPEC_VRLNM))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { /* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */ rtx tmp = gen_reg_rtx (V1TImode); @@ -2066,7 +2066,7 @@ (define_insn "altivec_vrlqnm_inst" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VRLNM))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" ;; rotate and mask bits need to be in upper 64-bits of operand2. "vrlqnm %0,%1,%2" [(set_attr "type" "veclogical")]) @@ -2119,7 +2119,7 @@ (define_insn "altivec_vslq_" [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") (ashift:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand" "v") (match_operand:VEC_TI 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" /* Shift amount in needs to be in bits[57:63] of 128-bit operand. */ "vslq %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -2136,7 +2136,7 @@ (define_insn "altivec_vsrq_" [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") (lshiftrt:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand" "v") (match_operand:VEC_TI 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" /* Shift amount in needs to be in bits[57:63] of 128-bit operand. */ "vsrq %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -2153,7 +2153,7 @@ (define_insn "altivec_vsraq" [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") (ashiftrt:V1TI (match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" /* Shift amount in needs to be in bits[57:63] of 128-bit operand. */ "vsraq %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -2768,7 +2768,7 @@ (define_insn "altivec_vcmpequt_p" (set (match_operand:V1TI 0 "altivec_register_operand" "=v") (eq:V1TI (match_dup 1) (match_dup 2)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcmpequq. %0,%1,%2" [(set_attr "type" "veccmpfx")]) @@ -2804,7 +2804,7 @@ (define_insn "*altivec_vcmpgtst_p" (set (match_operand:V1TI 0 "register_operand" "=v") (gt:V1TI (match_dup 1) (match_dup 2)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcmpgtsq. %0,%1,%2" [(set_attr "type" "veccmpfx")]) @@ -2828,7 +2828,7 @@ (define_insn "*altivec_vcmpgtut_p" (set (match_operand:V1TI 0 "register_operand" "=v") (gtu:V1TI (match_dup 1) (match_dup 2)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcmpgtuq. %0,%1,%2" [(set_attr "type" "veccmpfx")]) @@ -4583,7 +4583,7 @@ (define_insn "vcfuged" (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") (match_operand:V2DI 2 "altivec_register_operand" "v")] UNSPEC_VCFUGED))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcfuged %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4592,7 +4592,7 @@ (define_insn "vclzdm" (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") (match_operand:V2DI 2 "altivec_register_operand" "v")] UNSPEC_VCLZDM))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vclzdm %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4601,7 +4601,7 @@ (define_insn "vctzdm" (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") (match_operand:V2DI 2 "altivec_register_operand" "v")] UNSPEC_VCTZDM))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vctzdm %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4610,7 +4610,7 @@ (define_insn "vpdepd" (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") (match_operand:V2DI 2 "altivec_register_operand" "v")] UNSPEC_VPDEPD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vpdepd %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4619,7 +4619,7 @@ (define_insn "vpextd" (unspec:V2DI [(match_operand:V2DI 1 "altivec_register_operand" "v") (match_operand:V2DI 2 "altivec_register_operand" "v")] UNSPEC_VPEXTD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vpextd %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4628,7 +4628,7 @@ (define_insn "vgnb" (unspec:DI [(match_operand:V2DI 1 "altivec_register_operand" "v") (match_operand:QI 2 "u3bit_cint_operand" "n")] UNSPEC_VGNB))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vgnb %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4637,7 +4637,7 @@ (define_insn "vclrlb" (unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v") (match_operand:SI 2 "gpc_reg_operand" "r")] UNSPEC_VCLRLB))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) return "vclrlb %0,%1,%2"; @@ -4651,7 +4651,7 @@ (define_insn "vclrrb" (unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v") (match_operand:SI 2 "gpc_reg_operand" "r")] UNSPEC_VCLRRB))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) return "vclrrb %0,%1,%2"; diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index cdfd400f639..de0571a68c0 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -603,7 +603,7 @@ (define_predicate "easy_fp_constant" /* Constants that can be generated with ISA 3.1 instructions are easy. */ vec_const_128bit_type vsx_const; - if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) + if (TARGET_P10_VECTOR && vec_const_128bit_to_bytes (op, mode, &vsx_const)) { if (constant_generates_lxvkq (&vsx_const)) return true; @@ -671,8 +671,7 @@ (define_predicate "easy_vector_constant_ieee128" vec_const_128bit_type vsx_const; /* Can we generate the LXVKQ instruction? */ - if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 - || !TARGET_VSX) + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_P10_VECTOR) return false; return (vec_const_128bit_to_bytes (op, mode, &vsx_const) @@ -732,7 +731,7 @@ (define_predicate "easy_vector_constant" /* Constants that can be generated with ISA 3.1 instructions are easy. */ vec_const_128bit_type vsx_const; - if (TARGET_POWER10 && vec_const_128bit_to_bytes (op, mode, &vsx_const)) + if (TARGET_P10_VECTOR && vec_const_128bit_to_bytes (op, mode, &vsx_const)) { if (constant_generates_lxvkq (&vsx_const)) return true; diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 099cbc82245..ff1719da93c 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -129,13 +129,14 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode) case ENB_HTM: error ("%qs requires the %qs option", name, "-mhtm"); break; - case ENB_P10: - error ("%qs requires the %qs option", name, "-mcpu=power10"); - break; case ENB_P10_64: error ("%qs requires the %qs option and either the %qs or %qs option", name, "-mcpu=power10", "-m64", "-mpowerpc64"); break; + case ENB_P10V: + error ("%qs requires the %qs and %qs options", name, "-mcpu=power10", + "-mvsx"); + break; case ENB_MMA: error ("%qs requires the %qs option", name, "-mmma"); break; @@ -174,10 +175,10 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins fncode) return TARGET_MODULO && TARGET_POWERPC64; case ENB_P9V: return TARGET_P9_VECTOR; - case ENB_P10: - return TARGET_POWER10; case ENB_P10_64: return TARGET_POWER10 && TARGET_POWERPC64; + case ENB_P10V: + return TARGET_P10_VECTOR; case ENB_ALTIVEC: return TARGET_ALTIVEC; case ENB_VSX: @@ -301,7 +302,7 @@ rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out, machine_mode out_vmode = TYPE_MODE (type_out); /* Power10 supported vectorized built-in functions. */ - if (TARGET_POWER10 + if (TARGET_P10_VECTOR && in_vmode == out_vmode && VECTOR_UNIT_ALTIVEC_OR_VSX_P (in_vmode)) { diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 0c3c884c110..d4a4404a261 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -2906,7 +2906,8 @@ TTEST ttest {htm,htmcr} -[power10] +; Power10 vector builtins. +[power10-vector] const vbq __builtin_altivec_cmpge_1ti (vsq, vsq); CMPGE_1TI vector_nltv1ti {} diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc b/gcc/config/rs6000/rs6000-gen-builtins.cc index 1e2e780c610..5db5bac1ec3 100644 --- a/gcc/config/rs6000/rs6000-gen-builtins.cc +++ b/gcc/config/rs6000/rs6000-gen-builtins.cc @@ -229,8 +229,8 @@ enum bif_stanza BSTZ_DFP, BSTZ_CRYPTO, BSTZ_HTM, - BSTZ_P10, BSTZ_P10_64, + BSTZ_P10V, BSTZ_MMA, NUMBIFSTANZAS }; @@ -263,8 +263,8 @@ static stanza_entry stanza_map[NUMBIFSTANZAS] = { "dfp", BSTZ_DFP }, { "crypto", BSTZ_CRYPTO }, { "htm", BSTZ_HTM }, - { "power10", BSTZ_P10 }, { "power10-64", BSTZ_P10_64 }, + { "power10-vector", BSTZ_P10V }, { "mma", BSTZ_MMA } }; @@ -288,8 +288,8 @@ static const char *enable_string[NUMBIFSTANZAS] = "ENB_DFP", "ENB_CRYPTO", "ENB_HTM", - "ENB_P10", "ENB_P10_64", + "ENB_P10V", "ENB_MMA" }; @@ -2247,8 +2247,8 @@ write_decls (void) fprintf (header_file, " ENB_DFP,\n"); fprintf (header_file, " ENB_CRYPTO,\n"); fprintf (header_file, " ENB_HTM,\n"); - fprintf (header_file, " ENB_P10,\n"); fprintf (header_file, " ENB_P10_64,\n"); + fprintf (header_file, " ENB_P10V,\n"); fprintf (header_file, " ENB_MMA\n"); fprintf (header_file, "};\n\n"); diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 55b4133b1a3..8abd5416d81 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -2803,7 +2803,7 @@ expand_block_move (rtx operands[], bool might_overlap) } else if (TARGET_BLOCK_OPS_UNALIGNED_VSX /* Only use lxvl/stxvl on 64bit POWER10. */ - && TARGET_POWER10 + && TARGET_P10_VECTOR && TARGET_64BIT && bytes < 16 && orig_bytes > 16 diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 0bcc6a2d0ab..0e101ec7de1 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4769,7 +4769,7 @@ rs6000_option_override_internal (bool global_init_p) param_max_completely_peeled_insns, 400); /* The lxvl/stxvl instructions don't perform well before Power10. */ - if (TARGET_POWER10) + if (TARGET_P10_VECTOR) SET_OPTION_IF_UNSET (&global_options, &global_options_set, param_vect_partial_vector_usage, 1); else @@ -6708,7 +6708,8 @@ output_vec_const_move (rtx *operands) } vec_const_128bit_type vsx_const; - if (TARGET_POWER10 && vec_const_128bit_to_bytes (vec, mode, &vsx_const)) + if (TARGET_P10_VECTOR + && vec_const_128bit_to_bytes (vec, mode, &vsx_const)) { unsigned imm = constant_generates_lxvkq (&vsx_const); if (imm) @@ -29123,8 +29124,7 @@ constant_generates_lxvkq (vec_const_128bit_type *vsx_const) { /* Is the instruction supported with power10 code generation, IEEE 128-bit floating point hardware and VSX registers are available. */ - if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 - || !TARGET_VSX) + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_P10_VECTOR) return 0; /* All of the constants that are generated by LXVKQ have the bottom 3 words diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 703be908d94..a5b874bc21a 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -501,6 +501,9 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) +/* ISA 3.1 vector instruction support. */ +#define TARGET_P10_VECTOR (TARGET_POWER10 && TARGET_VSX) + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. The MASK_ options that have not yet been replaced by their OPTION_MASK_ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d352a1431ad..427e45aefbd 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -355,7 +355,7 @@ (define_attr "cpu" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,p10v" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -407,6 +407,10 @@ (define_attr "enabled" "" (and (eq_attr "isa" "p10") (match_test "TARGET_POWER10")) (const_int 1) + + (and (eq_attr "isa" "p10v") + (match_test "TARGET_P10_VECTOR")) + (const_int 1) ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor @@ -3305,7 +3309,7 @@ (define_insn "udivti3" [(set (match_operand:TI 0 "altivec_register_operand" "=v") (udiv:TI (match_operand:TI 1 "altivec_register_operand" "v") (match_operand:TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10 && TARGET_POWERPC64" + "TARGET_P10_VECTOR && TARGET_POWERPC64" "vdivuq %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -3403,7 +3407,7 @@ (define_insn "divti3" [(set (match_operand:TI 0 "altivec_register_operand" "=v") (div:TI (match_operand:TI 1 "altivec_register_operand" "v") (match_operand:TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10 && TARGET_POWERPC64" + "TARGET_P10_VECTOR && TARGET_POWERPC64" "vdivsq %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -3542,7 +3546,7 @@ (define_insn "umodti3" [(set (match_operand:TI 0 "altivec_register_operand" "=v") (umod:TI (match_operand:TI 1 "altivec_register_operand" "v") (match_operand:TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" + "TARGET_P10_VECTOR && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" "vmoduq %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -3551,7 +3555,7 @@ (define_insn "modti3" [(set (match_operand:TI 0 "altivec_register_operand" "=v") (mod:TI (match_operand:TI 1 "altivec_register_operand" "v") (match_operand:TI 2 "altivec_register_operand" "v")))] - "TARGET_POWER10 && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" + "TARGET_P10_VECTOR && TARGET_POWERPC64 && !RS6000_DISABLE_SCALAR_MODULO" "vmodsq %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -8690,7 +8694,7 @@ (define_insn "xxspltidp__internal" [(set (match_operand:SFDF 0 "register_operand" "=wa") (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] UNSPEC_XXSPLTIDP_CONST))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxspltidp %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -8699,7 +8703,7 @@ (define_insn "xxspltiw__internal" [(set (match_operand:SFDF 0 "register_operand" "=wa") (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] UNSPEC_XXSPLTIW_CONST))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxspltiw %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -8707,7 +8711,7 @@ (define_insn "xxspltiw__internal" (define_split [(set (match_operand:SFDF 0 "vsx_register_operand") (match_operand:SFDF 1 "vsx_prefixed_constant"))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" [(pc)] { rtx dest = operands[0]; diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index 524ba87d6d1..495867e2c27 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -28,7 +28,7 @@ (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) ;; Vector int modes for comparison, shift and rotation. ISA 3.1 adds the V1TI mode ;; for the vector int128 type. -(define_mode_iterator VEC_IC [V16QI V8HI V4SI V2DI (V1TI "TARGET_POWER10")]) +(define_mode_iterator VEC_IC [V16QI V8HI V4SI V2DI (V1TI "TARGET_P10_VECTOR")]) ;; 128-bit int modes (define_mode_iterator VEC_TI [V1TI TI]) @@ -734,7 +734,7 @@ (define_expand "vector_eq_v1ti_p" (set (match_operand:V1TI 0 "vlogical_operand") (eq:V1TI (match_dup 1) (match_dup 2)))])] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "") ;; This expansion handles the V16QI, V8HI, and V4SI modes in the @@ -831,7 +831,7 @@ (define_expand "vector_ne_v1ti_p" (set (match_operand:SI 0 "register_operand" "=r") (eq:SI (reg:CC CR6_REGNO) (const_int 0)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { operands[3] = gen_reg_rtx (V1TImode); }) @@ -877,7 +877,7 @@ (define_expand "vector_ae_v1ti_p" (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { operands[3] = gen_reg_rtx (V1TImode); }) @@ -950,7 +950,7 @@ (define_expand "vector_gt_v1ti_p" (set (match_operand:V1TI 0 "vlogical_operand") (gt:V1TI (match_dup 1) (match_dup 2)))])] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "") (define_expand "vector_ge__p" @@ -1400,7 +1400,7 @@ (define_expand "vashl3" [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") (ashift:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand") (match_operand:VEC_TI 2 "vsx_register_operand")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { /* Shift amount in needs to be put in bits[57:63] of 128-bit operand2. */ rtx tmp = gen_reg_rtx (mode); @@ -1423,7 +1423,7 @@ (define_expand "vlshr3" [(set (match_operand:VEC_TI 0 "vsx_register_operand" "=v") (lshiftrt:VEC_TI (match_operand:VEC_TI 1 "vsx_register_operand") (match_operand:VEC_TI 2 "vsx_register_operand")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { /* Shift amount in needs to be put into bits[57:63] of 128-bit operand2. */ rtx tmp = gen_reg_rtx (mode); diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7892477fa92..bfaf617ea15 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1285,7 +1285,7 @@ (define_insn "vsx_mov_64bit" (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - p10, p10, + p10v, p10v, , *, *, *, *") (set_attr "prefixed" "*, *, *, *, *, *, @@ -1328,7 +1328,7 @@ (define_insn "*vsx_mov_32bit" *, *") (set_attr "isa" ", , , *, *, *, - p10, p10, + p10v, p10v, p9v, *, , *, *, *, *") (set_attr "prefixed" @@ -1371,7 +1371,7 @@ (define_expand "vsx_store_" (define_insn "vsx_lxvrx" [(set (match_operand:TI 0 "vsx_register_operand" "=wa") (zero_extend:TI (match_operand:INT_ISA3 1 "memory_operand" "Z")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "lxvrx %x0,%y1" [(set_attr "type" "vecload")]) @@ -1380,7 +1380,7 @@ (define_insn "vsx_lxvrx" (define_insn "vsx_stxvrx" [(set (match_operand:INT_ISA3 0 "memory_operand" "=Z") (truncate:INT_ISA3 (match_operand:TI 1 "vsx_register_operand" "wa")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "stxvrx %x1,%y0" [(set_attr "type" "vecstore")]) @@ -1885,7 +1885,7 @@ (define_insn "vsx_div_v1ti" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VSX_DIVSQ))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdivsq %0,%1,%2" [(set_attr "type" "div")]) @@ -1894,7 +1894,7 @@ (define_insn "vsx_udiv_v1ti" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VSX_DIVUQ))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdivuq %0,%1,%2" [(set_attr "type" "div")]) @@ -1903,7 +1903,7 @@ (define_insn "vsx_dives_v1ti" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VSX_DIVESQ))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdivesq %0,%1,%2" [(set_attr "type" "div")]) @@ -1912,7 +1912,7 @@ (define_insn "vsx_diveu_v1ti" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VSX_DIVEUQ))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdiveuq %0,%1,%2" [(set_attr "type" "div")]) @@ -1921,7 +1921,7 @@ (define_insn "vsx_mods_v1ti" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VSX_MODSQ))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmodsq %0,%1,%2" [(set_attr "type" "div")]) @@ -1930,7 +1930,7 @@ (define_insn "vsx_modu_v1ti" (unspec:V1TI [(match_operand:V1TI 1 "vsx_register_operand" "v") (match_operand:V1TI 2 "vsx_register_operand" "v")] UNSPEC_VSX_MODUQ))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmoduq %0,%1,%2" [(set_attr "type" "div")]) @@ -2212,7 +2212,7 @@ (define_insn "*xvtlsbb_internal" [(set (match_operand:CC 0 "cc_reg_operand" "=y") (unspec:CC [(match_operand:V16QI 1 "vsx_register_operand" "wa")] UNSPEC_XVTLSBB))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xvtlsbb %0,%x1" [(set_attr "type" "logical")]) @@ -2229,7 +2229,7 @@ (define_expand "xvtlsbbo" UNSPEC_XVTLSBB)) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (lt:SI (match_dup 2) (const_int 0)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { operands[2] = gen_reg_rtx (CCmode); }) @@ -2239,7 +2239,7 @@ (define_expand "xvtlsbbz" UNSPEC_XVTLSBB)) (set (match_operand:SI 0 "gpc_reg_operand" "=r") (eq:SI (match_dup 2) (const_int 0)))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { operands[2] = gen_reg_rtx (CCmode); }) @@ -3358,7 +3358,7 @@ (define_insn "xxgenpcvm__internal" [(match_operand:VSX_EXTRACT_I4 1 "altivec_register_operand" "v") (match_operand:QI 2 "const_0_to_3_operand" "n")] UNSPEC_XXGENPCV))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxgenpcvm %x0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -3366,7 +3366,7 @@ (define_expand "xxgenpcvm_" [(use (match_operand:VSX_EXTRACT_I4 0 "register_operand")) (use (match_operand:VSX_EXTRACT_I4 1 "register_operand")) (use (match_operand:QI 2 "immediate_operand"))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (!BYTES_BIG_ENDIAN) { @@ -4217,7 +4217,7 @@ (define_expand "vextractl" (match_operand:VI2 2 "altivec_register_operand") (match_operand:SI 3 "register_operand")] UNSPEC_EXTRACTL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) { @@ -4237,7 +4237,7 @@ (define_insn "vextractl_internal" (match_operand:VEC_I 2 "altivec_register_operand" "v") (match_operand:SI 3 "register_operand" "r")] UNSPEC_EXTRACTL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vextvlx %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) @@ -4247,7 +4247,7 @@ (define_expand "vextractr" (match_operand:VI2 2 "altivec_register_operand") (match_operand:SI 3 "register_operand")] UNSPEC_EXTRACTR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) { @@ -4267,7 +4267,7 @@ (define_insn "vextractr_internal" (match_operand:VEC_I 2 "altivec_register_operand" "v") (match_operand:SI 3 "register_operand" "r")] UNSPEC_EXTRACTR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vextvrx %0,%1,%2,%3" [(set_attr "type" "vecsimple")]) @@ -4277,7 +4277,7 @@ (define_expand "vinsertvl_" (match_operand:VI2 2 "altivec_register_operand") (match_operand:SI 3 "register_operand" "r")] UNSPEC_INSERTL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vinsertvl_internal_ (operands[0], operands[3], @@ -4294,7 +4294,7 @@ (define_insn "vinsertvl_internal_" (match_operand:VEC_I 2 "altivec_register_operand" "v") (match_operand:VEC_I 3 "altivec_register_operand" "0")] UNSPEC_INSERTL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vinsvlx %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4304,7 +4304,7 @@ (define_expand "vinsertvr_" (match_operand:VI2 2 "altivec_register_operand") (match_operand:SI 3 "register_operand" "r")] UNSPEC_INSERTR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vinsertvr_internal_ (operands[0], operands[3], @@ -4321,7 +4321,7 @@ (define_insn "vinsertvr_internal_" (match_operand:VEC_I 2 "altivec_register_operand" "v") (match_operand:VEC_I 3 "altivec_register_operand" "0")] UNSPEC_INSERTR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vinsvrx %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4331,7 +4331,7 @@ (define_expand "vinsertgl_" (match_operand:VI2 2 "altivec_register_operand") (match_operand:SI 3 "register_operand")] UNSPEC_INSERTL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vinsertgl_internal_ (operands[0], operands[3], @@ -4348,7 +4348,7 @@ (define_insn "vinsertgl_internal_" (match_operand:SI 2 "register_operand" "r") (match_operand:VEC_I 3 "altivec_register_operand" "0")] UNSPEC_INSERTL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vinslx %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4358,7 +4358,7 @@ (define_expand "vinsertgr_" (match_operand:VI2 2 "altivec_register_operand") (match_operand:SI 3 "register_operand")] UNSPEC_INSERTR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_vinsertgr_internal_ (operands[0], operands[3], @@ -4375,7 +4375,7 @@ (define_insn "vinsertgr_internal_" (match_operand:SI 2 "register_operand" "r") (match_operand:VEC_I 3 "altivec_register_operand" "0")] UNSPEC_INSERTR))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vinsrx %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -4385,7 +4385,7 @@ (define_expand "vreplace_elt_" (match_operand: 2 "register_operand") (match_operand:QI 3 "const_0_to_3_operand")] UNSPEC_REPLACE_ELT))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { int index; /* Immediate value is the word index, convert to byte index and adjust for @@ -4409,7 +4409,7 @@ (define_insn "vreplace_elt__inst" (match_operand: 2 "register_operand" "r") (match_operand:QI 3 "const_0_to_12_operand" "n")] UNSPEC_REPLACE_ELT))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vins %0,%2,%3" [(set_attr "type" "vecsimple")]) @@ -4419,7 +4419,7 @@ (define_insn "vreplace_un_" (match_operand:REPLACE_ELT 2 "register_operand" "r") (match_operand:QI 3 "const_0_to_12_operand" "n")] UNSPEC_REPLACE_UN))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vins %0,%2,%3" [(set_attr "type" "vecsimple")]) @@ -5084,7 +5084,7 @@ (define_insn "vsx_sign_extend_v2di_v1ti" [(set (match_operand:V1TI 0 "vsx_register_operand" "=v") (unspec:V1TI [(match_operand:V2DI 1 "vsx_register_operand" "v")] UNSPEC_VSX_SIGN_EXTEND))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vextsd2q %0,%1" [(set_attr "type" "vecexts")]) @@ -5183,7 +5183,7 @@ (define_insn "extendditi2_vector" [(set (match_operand:TI 0 "gpc_reg_operand" "=v") (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")] UNSPEC_EXTENDDITI2))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vextsd2q %0,%1" [(set_attr "type" "vecexts")]) @@ -5855,7 +5855,7 @@ (define_expand "vcmpnet" (not:V1TI (eq:V1TI (match_operand:V1TI 1 "altivec_register_operand") (match_operand:V1TI 2 "altivec_register_operand"))))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { emit_insn (gen_eqvv1ti3 (operands[0], operands[1], operands[2])); emit_insn (gen_one_cmplv1ti2 (operands[0], operands[0])); @@ -6429,7 +6429,7 @@ (define_insn "vsx_" [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") (unspec:V16QI [(match_operand:V16QI 1 "vsx_register_operand" "wa")] XVCVBF16))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" " %x0,%x1" [(set_attr "type" "vecfloat")]) @@ -6437,7 +6437,7 @@ (define_insn "vec_mtvsrbmi" [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") (unspec:V16QI [(match_operand:QI 1 "u6bit_cint_operand" "n")] UNSPEC_MTVSBM))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "mtvsrbmi %0,%1" ) @@ -6445,7 +6445,7 @@ (define_insn "vec_mtvsr_" [(set (match_operand:VSX_MM 0 "altivec_register_operand" "=v") (unspec:VSX_MM [(match_operand:DI 1 "gpc_reg_operand" "r")] UNSPEC_MTVSBM))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "mtvsrm %0,%1"; [(set_attr "type" "vecsimple")]) @@ -6454,7 +6454,7 @@ (define_insn "vec_cntmb_" (unspec:DI [(match_operand:VSX_MM4 1 "altivec_register_operand" "v") (match_operand:QI 2 "const_0_to_1_operand" "n")] UNSPEC_VCNTMB))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vcntmb %0,%1,%2" [(set_attr "type" "vecsimple")]) @@ -6462,7 +6462,7 @@ (define_insn "vec_extract_" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:VSX_MM 1 "altivec_register_operand" "v")] UNSPEC_VEXTRACT))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vextractm %0,%1" [(set_attr "type" "vecsimple")]) @@ -6470,7 +6470,7 @@ (define_insn "vec_expand_" [(set (match_operand:VSX_MM 0 "vsx_register_operand" "=v") (unspec:VSX_MM [(match_operand:VSX_MM 1 "vsx_register_operand" "v")] UNSPEC_VEXPAND))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vexpandm %0,%1" [(set_attr "type" "vecsimple")]) @@ -6479,7 +6479,7 @@ (define_insn "dives_" (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")] UNSPEC_VDIVES))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdives %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "")]) @@ -6489,7 +6489,7 @@ (define_insn "diveu_" (unspec:VIlong [(match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")] UNSPEC_VDIVEU))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdiveu %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "")]) @@ -6498,7 +6498,7 @@ (define_insn "div3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (div:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdivs %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "")]) @@ -6507,7 +6507,7 @@ (define_insn "udiv3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (udiv:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vdivu %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "")]) @@ -6516,7 +6516,7 @@ (define_insn "mod3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmods %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "")]) @@ -6525,7 +6525,7 @@ (define_insn "umod3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmodu %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "")]) @@ -6538,7 +6538,7 @@ (define_insn "smul3_highpart" (ashiftrt (match_operand:VIlong 2 "vsx_register_operand" "v") (const_int 32))))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmulhs %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -6550,7 +6550,7 @@ (define_insn "umul3_highpart" (ashiftrt (match_operand:VIlong 2 "vsx_register_operand" "v") (const_int 32))))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmulhu %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -6559,7 +6559,7 @@ (define_insn "mulv2di3" [(set (match_operand:V2DI 0 "vsx_register_operand" "=v") (mult:V2DI (match_operand:V2DI 1 "vsx_register_operand" "v") (match_operand:V2DI 2 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmulld %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -6569,7 +6569,7 @@ (define_insn "xxspltiw_v4si" [(set (match_operand:V4SI 0 "register_operand" "=wa") (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] UNSPEC_XXSPLTIW))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxspltiw %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6578,7 +6578,7 @@ (define_expand "xxspltiw_v4sf" [(set (match_operand:V4SF 0 "register_operand" "=wa") (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] UNSPEC_XXSPLTIW))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { long value = rs6000_const_f32_to_i32 (operands[1]); emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); @@ -6589,7 +6589,7 @@ (define_insn "xxspltiw_v4sf_inst" [(set (match_operand:V4SF 0 "register_operand" "=wa") (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] UNSPEC_XXSPLTIW))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxspltiw %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6599,7 +6599,7 @@ (define_expand "xxspltidp_v2df" [(set (match_operand:V2DF 0 "register_operand" ) (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] UNSPEC_XXSPLTIDP))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { long value = rs6000_const_f32_to_i32 (operands[1]); rs6000_emit_xxspltidp_v2df (operands[0], value); @@ -6610,7 +6610,7 @@ (define_insn "xxspltidp_v2df_inst" [(set (match_operand:V2DF 0 "register_operand" "=wa") (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] UNSPEC_XXSPLTIDP))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxspltidp %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6622,7 +6622,7 @@ (define_expand "xxsplti32dx_v4si" (match_operand:QI 2 "u1bit_cint_operand" "n") (match_operand:SI 3 "s32bit_cint_operand" "n")] UNSPEC_XXSPLTI32DX))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { int index = INTVAL (operands[2]); @@ -6641,7 +6641,7 @@ (define_insn "xxsplti32dx_v4si_inst" (match_operand:QI 2 "u1bit_cint_operand" "n") (match_operand:SI 3 "s32bit_cint_operand" "n")] UNSPEC_XXSPLTI32DX))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxsplti32dx %x0,%2,%3" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6652,7 +6652,7 @@ (define_expand "xxsplti32dx_v4sf" (match_operand:QI 2 "u1bit_cint_operand" "n") (match_operand:SF 3 "const_double_operand" "n")] UNSPEC_XXSPLTI32DX))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { int index = INTVAL (operands[2]); long value = rs6000_const_f32_to_i32 (operands[3]); @@ -6670,7 +6670,7 @@ (define_insn "xxsplti32dx_v4sf_inst" (match_operand:QI 2 "u1bit_cint_operand" "n") (match_operand:SI 3 "s32bit_cint_operand" "n")] UNSPEC_XXSPLTI32DX))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxsplti32dx %x0,%2,%3" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6682,7 +6682,7 @@ (define_insn "xxblend_" (match_operand:VM3 2 "register_operand" "wa") (match_operand:VM3 3 "register_operand" "wa")] UNSPEC_XXBLEND))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxblendv %x0,%x1,%x2,%x3" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6695,7 +6695,7 @@ (define_expand "xxpermx" (match_operand:V16QI 3 "register_operand" "wa") (match_operand:QI 4 "u8bit_cint_operand" "n")] UNSPEC_XXPERMX))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" { if (BYTES_BIG_ENDIAN) emit_insn (gen_xxpermx_inst (operands[0], operands[1], @@ -6728,7 +6728,7 @@ (define_insn "xxpermx_inst" (match_operand:V16QI 3 "register_operand" "v") (match_operand:QI 4 "u3bit_cint_operand" "n")] UNSPEC_XXPERMX))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxpermx %x0,%x1,%x2,%x3,%4" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6741,7 +6741,7 @@ (define_insn "xxeval" (match_operand:V2DI 3 "register_operand" "wa") (match_operand:QI 4 "u8bit_cint_operand" "n")] UNSPEC_XXEVAL))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "xxeval %x0,%x1,%x2,%x3,%4" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) @@ -6770,7 +6770,7 @@ (define_insn "vmsumcud" (match_operand:V2DI 2 "register_operand" "v") (match_operand:V1TI 3 "register_operand" "v")] UNSPEC_VMSUMCUD))] - "TARGET_POWER10" + "TARGET_P10_VECTOR" "vmsumcud %0,%1,%2,%3" [(set_attr "type" "veccomplex")] ) diff --git a/gcc/testsuite/gcc.target/powerpc/pr116266.c b/gcc/testsuite/gcc.target/powerpc/pr116266.c new file mode 100644 index 00000000000..ab8a7c26f8a --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr116266.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_vsx } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mno-vsx" } */ + +/* Verify there is no ICE, so ignore error messages. */ +/* { dg-excess-errors "pr116266.c" } */ + +#include "altivec.h" + +vector unsigned char +foo (vector unsigned char a, vector unsigned char b, vector unsigned char c) +{ + return vec_ternarylogic (a, b, c, 128); +}