From patchwork Fri Aug 9 08:18:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 1970851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.a=rsa-sha256 header.s=default header.b=o0oCdEju; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WgH2p5ZFrz1ydk for ; Fri, 9 Aug 2024 18:22:26 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F098D3858D28 for ; Fri, 9 Aug 2024 08:22:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-110.freemail.mail.aliyun.com (out30-110.freemail.mail.aliyun.com [115.124.30.110]) by sourceware.org (Postfix) with ESMTPS id 997123858C33 for ; Fri, 9 Aug 2024 08:18:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 997123858C33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 997123858C33 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.110 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723191523; cv=none; b=Csy5j/MA4248bopMnaxcuSNJrL9NXbK7fYlY8G88lBnZx4+2RI8uYmCRQO/uz0ODVaBaZEyOD867H9dnXWQsfK6Q5PahObeWvCWf5z7ZRphckU+mCGNBoAGekhYvJBaJidj1vOzXyKHLWeua9WviWJafrgbKwUuX1+G++gj2RTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1723191523; c=relaxed/simple; bh=6q58ffkPK2B8EEhnfDOuHLxEjuxV5UjKfG3xqNpRH/Q=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=wlOB0QPt5eBa11l/lbFe7pufFtQwykmDME+239AdT5Da6QHtsPNkR752g6qT9lrWjlYY5EH/bY0gXH8CYQUjzCc7qryUGA6UFlzsTikZBDN07gBzh7j4NltuMQSaDbWRk2UfRKsyBN8wUrWxYflYLX6atUiCGHbMNDbPh2lMSXc= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1723191517; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=8EVRH00EkrHnBfWdDbRJ7ip5VNtyjua9orFsMiCsyi8=; b=o0oCdEjuhJ8GvPGVwBMaCpaWIMx0dIFBf3VGYqF+mvQtBZ2ZzKaRiUr7tya627N77NuSHFx3Li8lIxX35oXgtlfWd4oZjV/xQOpWFZH4Z4ucdg1aBZ+pBS77yfoUMLjSkZ3Q+9YpVleCLxGntclrzY1E3qhdsT1pDjg3ixlV9XE= Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0WCPMr2K_1723191513) by smtp.aliyun-inc.com; Fri, 09 Aug 2024 16:18:34 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com, juzhe.zhong@rivai.ai, pan2.li@intel.com Cc: kito.cheng@gmail.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker Date: Fri, 9 Aug 2024 16:18:17 +0800 Message-Id: <20240809081817.1498-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-27.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org When compiling an interface for rounding of type 'vfloat16*' without using zvfh or zvfhmin, it is not enough to use FLOAT_MODE_P because the type does not support it. Although the subsequent riscv_validate_vector_type checks will still fail and throw exceptions, I don't think we should have ICE here. internal compiler error: in check, at config/riscv/riscv-vector-builtins-shapes.cc:444 10 | return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl); | ^~~~~~ 0x4191794 internal_error(char const*, ...) /iothome/jin.ma/code/master/gcc/gcc/diagnostic-global-context.cc:491 0x416ebf5 fancy_abort(char const*, int, char const*) /iothome/jin.ma/code/master/gcc/gcc/diagnostic.cc:1772 0x220aae6 riscv_vector::build_frm_base::check(riscv_vector::function_checker&) const /iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins-shapes.cc:444 0x2205323 riscv_vector::function_checker::check() /iothome/jin.ma/code/master/gcc/gcc/config/riscv/riscv-vector-builtins.cc:4414 gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_vector_float_type_p): New. * config/riscv/riscv-vector-builtins.cc (function_instance::any_type_float_p): Use riscv_vector_float_type_p instead of FLOAT_MODE_P for judgment. * config/riscv/riscv.cc (riscv_vector_int_type_p): Change static to extern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-9.c: New test. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-vector-builtins.cc | 4 ++-- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c | 13 +++++++++++++ 4 files changed, 17 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 124ae2c073a..f8fc2874cbb 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -171,6 +171,7 @@ extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); extern bool riscv_reg_frame_related (rtx); extern void riscv_split_sum_of_two_s12 (HOST_WIDE_INT, HOST_WIDE_INT *, HOST_WIDE_INT *); +extern bool riscv_vector_float_type_p (const_tree type); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 49a1cb1708f..fa940d30caa 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3497,11 +3497,11 @@ function_instance::operator== (const function_instance &other) const bool function_instance::any_type_float_p () const { - if (FLOAT_MODE_P (TYPE_MODE (get_return_type ()))) + if (riscv_vector_float_type_p (get_return_type ())) return true; for (int i = 0; op_info->args[i].base_type != NUM_BASE_TYPES; ++i) - if (FLOAT_MODE_P (TYPE_MODE (get_arg_type (i)))) + if (riscv_vector_float_type_p (get_arg_type (i))) return true; return false; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3d0a1d12b14..84dc906c04d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5929,7 +5929,7 @@ riscv_vector_int_type_p (const_tree type) return strstr (name, "int") != NULL || strstr (name, "uint") != NULL; } -static bool +bool riscv_vector_float_type_p (const_tree type) { machine_mode mode = TYPE_MODE (type); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c new file mode 100644 index 00000000000..20ae9ebf6f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-9.c @@ -0,0 +1,13 @@ +/* Test that we do not have ice when compile */ +/* { dg-do assemble } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O2" { target { rv32 } } } */ + +#include + +vfloat16m1_t f0 (vfloat16m1_t vs2, vfloat16m1_t vs1, size_t vl) +{ + return __riscv_vfadd_vv_f16m1_rm (vs2, vs1, 0, vl); +} + +/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */