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Wed, 7 Aug 2024 17:15:14 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6F48058065; Wed, 7 Aug 2024 17:15:12 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 80E7C58070; Wed, 7 Aug 2024 17:15:11 +0000 (GMT) Received: from [9.67.100.70] (unknown [9.67.100.70]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Wed, 7 Aug 2024 17:15:11 +0000 (GMT) Message-ID: Date: Wed, 7 Aug 2024 10:15:10 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/4] rs6000, add testcases to the overloaded vec_perm built-in To: GCC Patches , Kewen , Peter Bergner , segher , David Edelsohn , cel References: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> Content-Language: en-US From: Carl Love In-Reply-To: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: zbIHtpbJSiX6WLLhT8H-Zs_3F1BGTGQU X-Proofpoint-GUID: D2oqQ3jFXhXSSRn5tEecEnpQwahEBTwd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 mlxscore=0 adultscore=0 clxscore=1015 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070118 X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org GCC maintainers: The following patch adds missing test cases for the overloaded vec_perm built-in.  It also fixes and issue with printing the 128-bit values in the DEBUG section that was noticed when adding the additional test cases. The patch has been tested on Power 10 LE and BE with no regressions. Please let me know if it is acceptable for mainline.  Thanks.                       Carl ------------------------------------------------------------- rs6000, add testcases to the overloaded vec_perm built-in The overloaded vec_perm built-in supports permuting signed and unsigned vectors of char, bool char, short int, short bool, int, bool, long long int, long long bool, int128, float and double.  However, not all of the supported arguments are included in the test cases.  This patch adds the missing test cases. Additionally, in the 128-bit debug print statements the expected result and the result need to be cast to unsigned long long to print correctly.  The patch makes this additional change to the print statements. gcc/ChangeLog:     * doc/extend.texi: Fix spelling mistake in description of the     vec_sel built-in.     Add documentation of the 128-bit vec_perm instance. gcc/testsuite/ChangeLog:     * gcc.target/powerpc/vsx-builtin-3.c: Add vec_perm test cases    for     arguments of type vector signed long long int, long long bool,     bool, bool short, bool char and pixel,     vector unsigned long long int, unsigned int, unsigned short int,     unsigned char.     Cast arguments for debug prints to unsigned long long.     * gcc.target/powerpc/builtins-4-int128-runnable.c: Add vec_perm     test cases for signed and unsigned int128 arguments. ---  gcc/doc/extend.texi                           |  12 +-  .../powerpc/builtins-4-int128-runnable.c      | 108 +++++++++++++++---  .../gcc.target/powerpc/vsx-builtin-3.c        |  18 +++  3 files changed, 121 insertions(+), 17 deletions(-) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 48b27ff9f39..bf6f4094040 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21553,9 +21553,19 @@ vector bool __int128 vec_sel (vector bool __int128,                 vector bool __int128, vector unsigned __int128);  @end smallexample -The instance is an extension of the exiting overloaded built-in @code{vec_sel} +The instance is an extension of the existing overloaded built-in @code{vec_sel}  that is documented in the PVIPR. +@smallexample +vector signed __int128 vec_perm (vector signed __int128, +               vector signed __int128); +vector unsigned __int128 vec_perm (vector unsigned __int128, +               vector unsigned __int128); +@end smallexample + +The 128-bit integer arguments for the @code{vec_perm} built-in are in addition +to the instances that are documented in the PVIPR. +  @node Basic PowerPC Built-in Functions Available on ISA 2.06  @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.06 diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c index 62c11132cf3..c61b0ecb854 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-4-int128-runnable.c @@ -18,6 +18,16 @@ int main() {    __uint128_t data_u128[100];    __int128_t data_128[100]; +#ifdef __BIG_ENDIAN__ +  vector unsigned char vuc = {0xC, 0xD, 0xE, 0xF, 0x8, 0x9, 0xA, 0xB, +                              0x1C, 0x1D, 0x1E, 0x1F, 0x18, 0x19, 0x1A, 0x1B}; +#else +  vector unsigned char vuc = {0x4, 0x5, 0x6, 0x7, 0x0, 0x1, 0x2, 0x3, +                  0x14, 0x15, 0x16, 0x17, 0x10, 0x11, 0x12, 0x13}; +#endif + +  vector __int128_t vec_128_arg1, vec_128_arg2; +  vector __uint128_t vec_u128_arg1, vec_u128_arg2;    vector __int128_t vec_128_expected1, vec_128_result1;    vector __uint128_t vec_u128_expected1, vec_u128_result1;    signed long long zero = (signed long long) 0; @@ -37,11 +47,13 @@ int main() {      {  #ifdef DEBUG      printf("Error: vec_xl(), vec_128_result1[0] = %lld %llu; ", -           vec_128_result1[0] >> 64, -           vec_128_result1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_128_result1[0] >> 64), +           (unsigned long long)(vec_128_result1[0] +                    & (__int128_t)0xFFFFFFFFFFFFFFFF));      printf("vec_128_expected1[0] = %lld %llu\n", -           vec_128_expected1[0] >> 64, -           vec_128_expected1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_128_expected1[0] >> 64), +           (unsigned long long)(vec_128_expected1[0] +                    & (__int128_t)0xFFFFFFFFFFFFFFFF));  #else      abort ();  #endif @@ -53,11 +65,13 @@ int main() {      {  #ifdef DEBUG      printf("Error: vec_xl(), vec_u128_result1[0] = %lld; ", -           vec_u128_result1[0] >> 64, -           vec_u128_result1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_u128_result1[0] >> 64), +           (unsigned long long)(vec_u128_result1[0] +                    & (__int128_t)0xFFFFFFFFFFFFFFFF));      printf("vec_u128_expected1[0] = %lld\n", -           vec_u128_expected1[0] >> 64, -           vec_u128_expected1[0] & (__int128_t)0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_u128_expected1[0] >> 64), +           (unsigned long long)(vec_u128_expected1[0] +                    & (__int128_t)0xFFFFFFFFFFFFFFFF));  #else      abort ();  #endif @@ -76,11 +90,12 @@ int main() {      {  #ifdef DEBUG      printf("Error: vec_xl_be(), vec_128_result1[0] = %llu %llu;", -           vec_128_result1[0] >> 64, -           vec_128_result1[0] & 0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_128_result1[0] >> 64), +           (unsigned long long)(vec_128_result1[0] & 0xFFFFFFFFFFFFFFFF));      printf(" vec_128_expected1[0] = %llu %llu\n", -           vec_128_expected1[0] >> 64, -           vec_128_expected1[0] & 0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_128_expected1[0] >> 64), +           (unsigned long long)(vec_128_expected1[0] +                    & 0xFFFFFFFFFFFFFFFF));  #else        abort ();  #endif @@ -98,11 +113,72 @@ int main() {      {  #ifdef DEBUG      printf("Error: vec_xl_be(), vec_u128_result1[0] = %llu %llu;", -           vec_u128_result1[0] >> 64, -           vec_u128_result1[0] & 0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_u128_result1[0] >> 64), +           (unsigned long long)(vec_u128_result1[0] & 0xFFFFFFFFFFFFFFFF)); +    printf(" vec_u128_expected1[0] = %llu %llu\n", +           (unsigned long long)(vec_u128_expected1[0] >> 64), +           (unsigned long long)(vec_u128_expected1[0] +                    & 0xFFFFFFFFFFFFFFFF)); +#else +      abort (); +#endif +    } + +  /* vec_perm() tests */ +  vec_128_arg1 = (vector __int128_t){ (__uint128_t)0x1122334455667788ULL }; +  vec_128_arg2 = (vector __int128_t){ (__uint128_t)0xAAABBBCCCDDDEEEF }; + +#ifdef __BIG_ENDIAN__ +  vec_128_expected1[0] = 0x5566778811223344ULL; +  vec_128_expected1[0] = (vec_128_expected1[0] << 64) | +    0xcdddeeefaaabbbccULL; +#else +  vec_128_expected1[0] = 0xcdddeeefaaabbbccULL; +  vec_128_expected1[0] = (vec_128_expected1[0] << 64) | +    0x5566778811223344ULL; +#endif + +  vec_128_result1 = vec_perm (vec_128_arg1, vec_128_arg2, vuc); + +  if (vec_128_expected1[0] != vec_128_result1[0]) +    { +#ifdef DEBUG +    printf("Error: vec_perm(), vec_128_result1[0] = %llu %llu;", +           (unsigned long long)(vec_128_result1[0] >> 64), +           (unsigned long long)(vec_128_result1[0] & 0xFFFFFFFFFFFFFFFF)); +    printf(" vec_128_expected1[0] = %llu %llu\n", +           (unsigned long long)(vec_128_expected1[0] >> 64), +           (unsigned long long)(vec_128_expected1[0] +                    & 0xFFFFFFFFFFFFFFFF)); +#else +      abort (); +#endif +    } +  vec_u128_arg1 = (vector __uint128_t){ (__uint128_t)0x1122334455667788ULL }; +  vec_u128_arg2 = (vector __uint128_t){ (__uint128_t)0xAAABBBCCCDDDEEEF }; + +#ifdef __BIG_ENDIAN__ +  vec_u128_expected1[0] = 0x5566778811223344ULL; +  vec_u128_expected1[0] = (vec_u128_expected1[0] << 64) | +    0xcdddeeefaaabbbccULL; +#else +  vec_u128_expected1[0] = 0xcdddeeefaaabbbccULL; +  vec_u128_expected1[0] = (vec_u128_expected1[0] << 64) | +    0x5566778811223344ULL; +#endif + +  vec_u128_result1 = vec_perm (vec_u128_arg1, vec_u128_arg2, vuc); + +  if (vec_u128_expected1[0] != vec_u128_result1[0]) +    { +#ifdef DEBUG +    printf("Error: vec_perm(), vec_u128_result1[0] = %llu %llu;", +           (unsigned long long)(vec_u128_result1[0] >> 64), +           (unsigned long long)(vec_u128_result1[0] & 0xFFFFFFFFFFFFFFFF));      printf(" vec_u128_expected1[0] = %llu %llu\n", -           vec_u128_expected1[0] >> 64, -           vec_u128_expected1[0] & 0xFFFFFFFFFFFFFFFF); +           (unsigned long long)(vec_u128_expected1[0] >> 64), +           (unsigned long long)(vec_u128_expected1[0] +                    & 0xFFFFFFFFFFFFFFFF));  #else        abort ();  #endif diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c index 67c93be1469..b3b76be34b9 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c @@ -39,10 +39,17 @@  #include +extern __vector long long int sll[][4]; +extern __vector long long bool bll[][4];  extern __vector int si[][4]; +extern __vector bool int bi[][4];  extern __vector short ss[][4]; +extern __vector bool short bs[][4];  extern __vector signed char sc[][4]; +extern __vector bool char bc[][4]; +extern __vector pixel p[][4];  extern __vector float f[][4]; +extern __vector unsigned long long int ull[][4];  extern __vector unsigned int ui[][4];  extern __vector unsigned short us[][4];  extern __vector unsigned char uc[][4]; @@ -88,12 +95,23 @@ int do_perm(void)  {    int i = 0; +  sll[i][0] = vec_perm (sll[i][1], sll[i][2], uc[i][3]); i++; +  bll[i][0] = vec_perm (bll[i][1], bll[i][2], uc[i][3]); i++;    si[i][0] = vec_perm (si[i][1], si[i][2], uc[i][3]); i++; +  bi[i][0] = vec_perm (bi[i][1], bi[i][2], uc[i][3]); i++;    ss[i][0] = vec_perm (ss[i][1], ss[i][2], uc[i][3]); i++; +  bs[i][0] = vec_perm (bs[i][1], bs[i][2], uc[i][3]); i++;    sc[i][0] = vec_perm (sc[i][1], sc[i][2], uc[i][3]); i++; +  bc[i][0] = vec_perm (bc[i][1], bc[i][2], uc[i][3]); i++; +  p[i][0] = vec_perm (p[i][1], p[i][2], uc[i][3]); i++;    f[i][0] = vec_perm (f[i][1], f[i][2], uc[i][3]); i++;    d[i][0] = vec_perm (d[i][1], d[i][2], uc[i][3]); i++; +  ull[i][0] = vec_perm (ull[i][1], ull[i][2], uc[i][3]); i++; +  ui[i][0] = vec_perm (ui[i][1], ui[i][2], uc[i][3]); i++; +  us[i][0] = vec_perm (us[i][1], us[i][2], uc[i][3]); i++; +  uc[i][0] = vec_perm (uc[i][1], uc[i][2], uc[i][3]); i++; +    si[i][0] = vec_perm (si[i][1], si[i][2], uc[i][3]); i++;    ss[i][0] = vec_perm (ss[i][1], ss[i][2], uc[i][3]); i++;    sc[i][0] = vec_perm (sc[i][1], sc[i][2], uc[i][3]); i++; From patchwork Wed Aug 7 17:15:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 1970162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=dTv4jtWf; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WfGzJ3JzRz1ydt for ; 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Wed, 7 Aug 2024 17:15:23 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8CF2458062; Wed, 7 Aug 2024 17:15:21 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BB0705805A; Wed, 7 Aug 2024 17:15:20 +0000 (GMT) Received: from [9.67.100.70] (unknown [9.67.100.70]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Wed, 7 Aug 2024 17:15:20 +0000 (GMT) Message-ID: Date: Wed, 7 Aug 2024 10:15:20 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/4] rs6000, remove built-ins __builtin_vsx_vperm_8hi and, __builtin_vsx_vperm_8hi_uns To: GCC Patches , Kewen , Peter Bergner , segher , David Edelsohn , cel References: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> Content-Language: en-US From: Carl Love In-Reply-To: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: h4a-j9az6-txEOLsXhUJnB9HVuRjlWmY X-Proofpoint-ORIG-GUID: LmObxfQ2vJLa5rx-HcZPnDAv4mjkUzUl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 mlxscore=0 suspectscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070118 X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org GCC maintainers: The following patch removes two redundant built-ins __builtin_vsx_vperm_8hi and __builtin_vsx_vperm_8hi_uns.  The built-ins are covered by the overloaded vec_perm built-in. The patch has been tested on Power 10 LE and BE with no regressions. Please let me know if it is acceptable for mainline.  Thanks.                       Carl ------------------------------------------------------------- rs6000, remove built-ins __builtin_vsx_vperm_8hi and __builtin_vsx_vperm_8hi_uns The two built-ins __builtin_vsx_vperm_8hi and __builtin_vsx_vperm_8hi_uns are redundant. The are covered by the overloaded vec_perm built-in.  The built-ins are not documented and do not have test cases. This patch removes the redundant built-ins. gcc/ChangeLog:     * config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_8hi,     __builtin_vsx_vperm_8hi_uns): Remove built-in definitions. ---  gcc/config/rs6000/rs6000-builtins.def | 6 ------  1 file changed, 6 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 0c3c884c110..8bb7686bcc8 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1469,12 +1469,6 @@    const vf __builtin_vsx_uns_floato_v2di (vsll);      UNS_FLOATO_V2DI unsfloatov2di {} -  const vss __builtin_vsx_vperm_8hi (vss, vss, vuc); -    VPERM_8HI_X altivec_vperm_v8hi {} - -  const vus __builtin_vsx_vperm_8hi_uns (vus, vus, vuc); -    VPERM_8HI_UNS_X altivec_vperm_v8hi_uns {} -    const vsll __builtin_vsx_vsigned_v2df (vd);      VEC_VSIGNED_V2DF vsx_xvcvdpsxds {} From patchwork Wed Aug 7 17:15:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Carl Love X-Patchwork-Id: 1970163 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Wed, 7 Aug 2024 17:15:24 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF1075805E; Wed, 7 Aug 2024 17:15:23 +0000 (GMT) Received: from [9.67.100.70] (unknown [9.67.100.70]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Wed, 7 Aug 2024 17:15:23 +0000 (GMT) Message-ID: <2dbd42ec-844a-4479-956a-9454db0fae92@linux.ibm.com> Date: Wed, 7 Aug 2024 10:15:23 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 3/4] rs6000, Remove redundant built-in __builtin_vsx_xvcvuxwdp To: GCC Patches , Kewen , Peter Bergner , segher , David Edelsohn , cel References: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> Content-Language: en-US From: Carl Love In-Reply-To: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: PzAFR7H2IxZs4I1eMAIQN1RSeCRDQPUB X-Proofpoint-GUID: lyVg0m6WPKQw4MUygpv6MA3YXbPurRDV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=871 impostorscore=0 spamscore=0 mlxscore=0 adultscore=0 clxscore=1015 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070118 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org GCC maintainers: The patch removed the built-in __builtin_vsx_xvcvuxwdp as it is covered by the overloaded vec_doubleo built-in. The patch has been tested on Power 10 LE and BE with no regressions. Please let me know if it is acceptable for mainline.  Thanks.                       Carl -------------------------------------------------------------------- rs6000, Remove redundant built-in __builtin_vsx_xvcvuxwdp The built-in __builtin_vsx_xvcvuxwdp is a duplicate of the overloaded built-in vec_doubleo.  There are no test cases or documentation for __builtin_vsx_xvcvuxwdp.  This patch removes the redundant built-in. gcc/ChangeLog:     * config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvuxwdp):     Remove built-in definition. ---  gcc/config/rs6000/rs6000-builtins.def | 3 ---  1 file changed, 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 8bb7686bcc8..f2bebd299b2 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1613,9 +1613,6 @@    const vf __builtin_vsx_xvcvuxdsp (vull);      XVCVUXDSP vsx_xvcvuxdsp {} -  const vd __builtin_vsx_xvcvuxwdp (vsi); -    XVCVUXWDP vsx_xvcvuxwdp {} -    const vf __builtin_vsx_xvcvuxwsp (vsi); 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Wed, 7 Aug 2024 17:15:30 GMT Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1C70458068; Wed, 7 Aug 2024 17:15:28 +0000 (GMT) Received: from smtpav02.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2FA3B5805A; Wed, 7 Aug 2024 17:15:27 +0000 (GMT) Received: from [9.67.100.70] (unknown [9.67.100.70]) by smtpav02.dal12v.mail.ibm.com (Postfix) with ESMTP; Wed, 7 Aug 2024 17:15:27 +0000 (GMT) Message-ID: <4e8ccb7a-85b6-462f-853f-d160000907d7@linux.ibm.com> Date: Wed, 7 Aug 2024 10:15:26 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 4/4] rs6000, Add tests and documentation for vector, conversions between integer and float To: GCC Patches , Kewen , Peter Bergner , segher , David Edelsohn , cel References: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> Content-Language: en-US From: Carl Love In-Reply-To: <4aede9fb-787b-4aec-a4cd-5bd0224fbed6@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: WJXAwPqwytwJ-ip-VYbKg_YPXMdOZXF0 X-Proofpoint-ORIG-GUID: flHBonAUs_XUYzvk1A-O02yim_fNSmab X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 mlxscore=0 malwarescore=0 spamscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070118 X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org GCC maintainers: The following patch fixes errors in the definition of the __builtin_vsx_uns_floate_v2di, __builtin_vsx_uns_floato_v2di and __builtin_vsx_uns_float2_v2di built-ins.  The arguments should be unsigned but are listed as signed. Additionally, there are a number of test cases that are missing for the various instances of the built-ins.  Additionally, the documentation for the various built-ins is missing. This patch adds the missing test cases and documentation. The patch has been tested on Power 10 LE and BE with no regressions. Please let me know if it is acceptable for mainline.  Thanks.                                             Carl ------------------------------------------------------------------------------------- rs6000, Add tests and documentation for vector conversions between integer and float The arguments for the __builtin_vsx_uns_floate_v2di, __builtin_vsx_uns_floato_v2di and __builtin_vsx_uns_float2_v2di built-ins should be unsigned. Add tests for the following existing integer and long long int to float built-ins:   __builtin_altivecfloat_sisf (vsi);   __builtin_altivec_uns_float_sisf (vui);   __builtin_vsxfloate_v2di (vsll);   __builtin_vsx_uns_floate_v2di (vull);   __builtin_vsx_floato_v2di (vsll);   __builtin_vsx_uns_floato_v2di (vull);   __builtin_vsx_float2_v2di (vsll, vsll);   __builtin_vsx_uns_float2_v2di (vull, vull); Add tests for the vector float to vector int built-ins:   __builtin_altivec_fix_sfsi   __builtin_altivec_fixuns_sfsi The various built-ins are not documented.  The patch adds the missing documentation for the variouls built-ins. This patch fixes the incorrect __builtin_vsx_uns_float[o|e|2]_v2di argument types and adds test cases for each of the built-ins listed above. gcc/ChangeLog:     * config/rs6000/rs6000-builtins.def (__builtin_vsx_uns_floate_v2di,     __builtin_vsx_uns_floato_v2di,__builtin_vsx_uns_float2_v2di): Change     argument from signed to unsigned.     * doc/extend.texi: Add documentation for each of the built-ins. gcc/testsuite/ChangeLog:     * gcc.target/powerpc/vsx-int-to-float-runnable.c: New file. ---  gcc/config/rs6000/rs6000-builtins.def         |   6 +-  gcc/doc/extend.texi                           |  37 +++  .../powerpc/vsx-int-to-float-runnable.c       | 260 ++++++++++++++++++  3 files changed, 300 insertions(+), 3 deletions(-)  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-int-to-float-runnable.c +      printf ("ERROR, __builtin_altivec_fixuns_sfsi (src_f) result doe not match expected output.\n"); +      printf ("  result_uint[%d] = %d  ", i, result_uint[i]); +      printf ("  expected_result_uint[%d] = %d\n", i, +          expected_result_uint[i]); +    } +#else +        abort (); +#endif +    } +} diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index f2bebd299b2..1227daa1555 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -1463,10 +1463,10 @@    const vd __builtin_vsx_uns_doubleo_v4si (vsi);      UNS_DOUBLEO_V4SI unsdoubleov4si2 {} -  const vf __builtin_vsx_uns_floate_v2di (vsll); +  const vf __builtin_vsx_uns_floate_v2di (vull);      UNS_FLOATE_V2DI unsfloatev2di {} -  const vf __builtin_vsx_uns_floato_v2di (vsll); +  const vf __builtin_vsx_uns_floato_v2di (vull);      UNS_FLOATO_V2DI unsfloatov2di {}    const vsll __builtin_vsx_vsigned_v2df (vd); @@ -2272,7 +2272,7 @@    const vss __builtin_vsx_revb_v8hi (vss);      REVB_V8HI revb_v8hi {} -  const vf __builtin_vsx_uns_float2_v2di (vsll, vsll); +  const vf __builtin_vsx_uns_float2_v2di (vull, vull);      UNS_FLOAT2_V2DI uns_float2_v2di {}    const vsi __builtin_vsx_vsigned2_v2df (vd, vd); diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index bf6f4094040..7ec4f19a6bf 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -22919,6 +22919,43 @@ but the index value must be 0.  Only functions excluded from the PVIPR are listed here. +The following built-ins convert signed and unsigned vectors of ints and +long long ints to a vector of 32-bit floating point values. + +@smallexample +vector float __builtin_altivec_float_sisf (vector int); +vector float __builtin_altivec_uns_float_sisf (vector unsigned int); +vector float __builtin_vsx_floate_v2di (vector signed long long int); +vector float __builtin_vsx_uns_floate_v2di (vector unsigned long long int); +vector float __builtin_vsx_floato_v2di (vector signed long long int); +vector float __builtin_vsx_uns_floato_v2di (vector unsigned long long int); +vector float __builtin_vsx_float2_v2di (vector signed long long int, +                                        vector signed long long int); +vector float __builtin_vsx_uns_float2_v2di (vector unsigned long long int, +                                            vector signed long long int); +@end smallexample + +The @code{__builtin_altivec_float_sisf} and +@code{__builtin_altivec_uns_float_sisf} built-ins convert signed and +unsigned vectors of 32-bit integers to a vector of 32-bit floating point +values.  The @code{__builtin_vsx_floate_v2di} and +@code{__builtin_vsx_uns_floate_v2di} built-ins converts a vector +long long ints to 32-bit floating point values storing the results in +the corresonding even vector element locations.  Similarly, +@code{__builtin_vsx_floato_v2di} and @code{__builtin_vsx_uns_floato_v2di} +convert the long long ints and store them in the odd vector element locations. +The @code{__builtin_vsx_uns_float2_v2di} takes two long long int vectors +and converts them to single vector of 32-bit floating point values. + +@smallexample +vector int __builtin_altivec_fix_sfsi (vector float); +vector int __builtin_altivec_fixuns_sfsi (vector float); +@end smallexample + +The @code{__builtin_altivec_fix_sfsi} and @code{__builtin_altivec_fixuns_sfsi} +built-ins convert vectors of 32-bit floating point values to +signed or unsigned 32-bit integers respectively. +  @smallexample  vector __int128 vec_vaddcuq (vector __int128, vector __int128);  vector __uint128 vec_vaddcuq (vector __uint128, vector __uint128); diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-int-to-float-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx-int-to-float-runnable.c new file mode 100644 index 00000000000..e01bb274721 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-int-to-float-runnable.c @@ -0,0 +1,260 @@ +/* { dg-do run } */ +/* { dg-options "-mvsx -mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_vsx } */ + +/* The __builtin_vsx_float2_v2di builtin uses the vmgrow instruction which is +   Power 8.  The conversion instructions are all Power 7.  */ + +#include // vector + +#define DEBUG 0 + +#if DEBUG +#include +#endif + +void abort (void); + +int main (void) +{ +  int i; +  vector int src_int = { 5, 17, 400, 9000 }; +  vector unsigned int src_uint = { 1, 20, 300, 4000 }; +  vector signed long long int src_sll = { 13, 513 }; +  vector unsigned long long int src_ull = { 27, 731 }; +  vector signed long long int srcB_sll = { 27, 739 }; +  vector unsigned long long int srcB_ull = { 19, 57 }; +  vector int result_int, expected_result_int; +  vector unsigned int result_uint, expected_result_uint; +  vector float src_f = { 3.1, -9.1, 20.9, -99.99}; +  vector float result_float, expected_result_float; +  vector double result_double, expected_result_double; + +  /* Test vector signed and unsigned int to float.  */ +  expected_result_float[0] = 5.0; +  expected_result_float[1] = 17.0; +  expected_result_float[2] = 400.0; +  expected_result_float[3] = 9000.0; + +  result_float = __builtin_altivec_float_sisf (src_int); + +  for (i = 0; i < 4; i++) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_float_sisf (src_uint) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif +    } + +  expected_result_float[0] = 1.0; +  expected_result_float[1] = 20.0; +  expected_result_float[2] = 300.0; +  expected_result_float[3] = 4000.0; + +  result_float = __builtin_altivec_uns_float_sisf (src_uint); + +  for (i = 0; i < 4; i++) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_uns_float_sisf (src_uint) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif +    } + +  /* Test vector signed and unsigned long long int to Double.  */ + +  /* Test even result elements.  */ +  expected_result_float[0] = 13.0; +  expected_result_float[1] = 0.0; +  expected_result_float[2] = 513.0; +  expected_result_float[3] = 0.0; + +  result_float = __builtin_vsx_floate_v2di(src_sll); + +  for (i = 0; i < 4; i = i + 2) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_floate_v2di (src_sll) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif +    } + +  expected_result_float[0] = 27.0; +  expected_result_float[1] = 0.0; +  expected_result_float[2] = 731.0; +  expected_result_float[3] = 0.0; + +  result_float = __builtin_vsx_uns_floate_v2di(src_ull); + +  for (i = 0; i < 4; i = i + 2) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_uns_floate_v2di (src_ull) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif + +    } + +  /* Test odd result elements.  */ +  expected_result_float[0] = 0.0; +  expected_result_float[1] = 13.0; +  expected_result_float[2] = 0.0; +  expected_result_float[3] = 513.0; + +  result_float = __builtin_vsx_floato_v2di(src_sll); + +  for (i = 1; i < 4; i = i + 2) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_floato_v2di (src_sll) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif + +    } + +  expected_result_float[0] = 0.0; +  expected_result_float[1] = 27.0; +  expected_result_float[2] = 0.0; +  expected_result_float[3] = 731.0; + +  result_float = __builtin_vsx_uns_floato_v2di(src_ull); + +  for (i = 1; i < 4; i = i + 2) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_uns_floato_v2di (src_ull) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif +    } + +  /* Test two source args.  */ +  expected_result_float[0] = 13.0; +  expected_result_float[1] = 513.0; +  expected_result_float[2] = 27.0; +  expected_result_float[3] = 739.0; + +  result_float = __builtin_vsx_float2_v2di(src_sll, srcB_sll); + +  for (i = 1; i < 4; i++) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_uns_float2_v2di (src_sll, src_sll) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif +    } +  expected_result_float[0] = 27.0; +  expected_result_float[1] = 731.0; +  expected_result_float[2] = 19.0; +  expected_result_float[3] = 57.0; + +  result_float = __builtin_vsx_uns_float2_v2di(src_ull, srcB_ull); + +  for (i = 1; i < 4; i++) +    { +      if (result_float[i] != expected_result_float[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_uns_float2_v2di (src_ull, src_ull) result doe not match expected output.\n"); +      printf ("  result_float[%d] = %f  ", i, result_float[i]); +      printf ("  expected result_float[%d] = %f\n", i, +          expected_result_float[i]); +    } +#else +        abort (); +#endif +    } + +  /* Test vector float to signed/unsigned vector int.  */ +  expected_result_int[0] = 3; +  expected_result_int[1] = -9; +  expected_result_int[2] = 20; +  expected_result_int[3] = -99; + +  result_int = __builtin_altivec_fix_sfsi(src_f); + +  for (i = 0; i < 4; i++) +    { +      if (result_int[i] != expected_result_int[i]) +#if DEBUG +    { +      printf ("ERROR, __builtin_altivec_fix_sfsi (src_f) result doe not match expected output.\n"); +      printf ("  result_int[%d] = %d  ", i, result_int[i]); +      printf ("  expected_result_int[%d] = %d\n", i, +          expected_result_int[i]); +    } +#else +        abort (); +#endif +    } + +  expected_result_uint[0] = 3; +  expected_result_uint[1] = 0; +  expected_result_uint[2] = 20; +  expected_result_uint[3] = 0; + +  result_uint = __builtin_altivec_fixuns_sfsi(src_f); + +  for (i = 0; i < 4; i++) +    { +      if (result_uint[i] != expected_result_uint[i]) +#if DEBUG +    {