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Wed, 07 Aug 2024 16:47:33 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 477GlW0c024291 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 7 Aug 2024 16:47:32 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 7 Aug 2024 09:47:32 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] aarch64/testsuite: Add testcases for recently fixed PRs Date: Wed, 7 Aug 2024 09:47:16 -0700 Message-ID: <20240807164716.736040-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: xWa-TjVUq8njtlAkfP1zGDPAaes3w5ah X-Proofpoint-GUID: xWa-TjVUq8njtlAkfP1zGDPAaes3w5ah X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-07_11,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 priorityscore=1501 adultscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxlogscore=851 clxscore=1015 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408070117 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org The commit for PR 116258, added a x86_64 specific testcase, I thought it would be a good idea to add an aarch64 testcase too. And since it also fixed VLA vectors too so add a SVE testcase. Pushed as obvious after a test for aarch64-linux-gnu. PR middle-end/116258 PR middle-end/116259 gcc/testsuite/ChangeLog: * gcc.target/aarch64/pr116258.c: New test. * gcc.target/aarch64/sve/pr116259-1.c: New test. Signed-off-by: Andrew Pinski --- gcc/testsuite/gcc.target/aarch64/pr116258.c | 17 +++++++++++++++++ .../gcc.target/aarch64/sve/pr116259-1.c | 12 ++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr116258.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c diff --git a/gcc/testsuite/gcc.target/aarch64/pr116258.c b/gcc/testsuite/gcc.target/aarch64/pr116258.c new file mode 100644 index 00000000000..e727ad4b72a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr116258.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#pragma GCC target "+nosve" + +#define vect16 __attribute__((vector_size(16))) +#define h(a) __builtin_assoc_barrier((a)) + + vect16 float f( vect16 float x, vect16 float vconstants0) +{ + vect16 float t = (x * (vconstants0[0])); + return (x + h(t)); +} + +/* { dg-final { scan-assembler-times "\\\[0\\\]" 1 } } */ +/* { dg-final { scan-assembler-not "dup\t" } } */ +/* { dg-final { scan-assembler-not "ins\t" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c new file mode 100644 index 00000000000..bb2eed4728c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr116259-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* PR middle-end/116259 */ + +#include + +/* PAREN_EXPR lowering for VLA vectors was ICEing. + It should not be lowered in a similar way as moves + are not lowered. */ +svfloat64_t f(svfloat64_t x) +{ + return __builtin_assoc_barrier(x); +}