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Peter Anvin" , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , "Philipp Stanner" CC: Stewart Hildebrand , , , Subject: [PATCH v3 1/8] x86/PCI: Improve code readability Date: Wed, 7 Aug 2024 11:17:10 -0400 Message-ID: <20240807151723.613742-2-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003440:EE_|SJ1PR12MB6076:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f95031e-be91-4d80-a35a-08dcb6f41119 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 23ZMbs6FFzQ5hX0DTMbhPoWQ7whMcmb7nnGX/k0YwjDzadDQTV/NpaTpSIz7qKoLYxtapCNPA8DeTkK5PRLxqLbzj7WPjoaYzgdyQrl1GgsVLTfZLhQ+bPta8yKjClSpvuJmlNZ+emEG1Br2OTm1uN3D2Op7lg2th1fIW9Yo/w2uObwYy4wIp97WrJ8TC4m6BGdwcH9VAyUzhDBFIuQVycmlNTsPjTkA0EDIUZNnhxuYRRNFB96CHe70w7GsKTj6fyvSIBHsm1KBExYhTqVWQI/dnH7wnPvHyY3lIk9Wid7jtC75iaCbCZYUWzaUuuM3q3NabisXNN2WFvC6/Qnm1HyWKRCfFCXcjDHhrYll7HNlfM2j1TdMtwTmdqljvZLSzB6l8TZFnzS4rDOejL9FaDnW7IyCxh/aUQIvfhV9bnCxf5ODlqzQtE6StgnpmdhTED9psQ0d6QPDoQi+mn6UzbiF51oP/o7+kWCgtd0HQuQtYH/ZYBn68d4W3Vo+P6UoD8HopkjQEVBxP3AAhg0WRtbxY2hgXCNNAG1cmBIEvouvT7TUZ6pbA9iT7jwip1W+ePoB8CWAPGRdd+UnPMSEUbD7px8EA4N7wOZn2ZiHNygHC6t7wEAcTnu8ehXoLpporV+CXB9KzgqI/okng6EuitpjBSzL4o8N+ZYNeHtj0xWxrFJLrqZ2U2SJKpftnmuRD5c/SfadWcD+HMauU14zPcUh4wZZM8pLBQj7x04y89uzAddxAMGUPN3mdqLYRMATuU4SmDLZjAPfRjUDH/298JZHTFF89wJcN4Q/EPIF/hrcXuRap2Hw8hWcUinxFZbjQtdsw+gf6kjAQOlafJVS1n+NW3icNhNZtWSRR1ae12q4Fypb9SP1ADh0oMt4nviOU8/N1q/BVHCXi00M5fDqVc7i5InK4ZXsa79ORxz6d66A203e7V+F8Z82vstWg/HR1IEkk+l2pvnkAVntcA7DLZVZ4BrG/lfqZd/JxrG/zpORvOecq/tdN33ozjbcjXYFX+zI/aBGY+9z0P/r8NaNEGxEqcEmVHubsj1aAJjt/kZScOozP5A7DLE259+a5JutzTSEDS2Cr2VWTbYtbROWqnoMX8j6QDmjNTn9bpq3wWNxIG0soF7peMgn3YI2gyKgGnJXoM5a9FDCAPNiY3y7rz3lbxIFrWP1KKs7jYPWu10W0Y7nenE/Pdg+Lyt96aFEB0ovIKboPm/hkqvyw5BoVR410hK0Dh7DyIheijJcqKDE9K8YxeQo7lByiVSmU7kKxDQKzvEpcuJZhsgiJLfLlPQCr/LVZFH/Lc3eYSgu1Aqz/T8lc7T1nrzWJ8wMPYkfyxWrHzyoGC7UcCIhVo32G9d7iihDmG6iAiPweGR/Hpu5vL9qbwXTWJUxWh17SPfo54x6SBF/0WOQamc5Gh7YoubIiWEjXfcTG2OBLhuPdMZ8JCh1UY/ObjWTk/QJy1gH X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:17:35.3842 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f95031e-be91-4d80-a35a-08dcb6f41119 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003440.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6076 The indentation in pcibios_allocate_dev_resources() is unusually deep. Improve that by moving some of its code to a new function, alloc_resource(). Take the opportunity to remove redundant information from dev_dbg(). Signed-off-by: Stewart Hildebrand Reviewed-by: Ilpo Järvinen --- v2->v3: * new subject (was: "x86/PCI: Move some logic to new function") * reword commit message (thanks Philipp) v1->v2: * new patch --- arch/x86/pci/i386.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index f2f4a5d50b27..3abd55902dbc 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -246,6 +246,25 @@ struct pci_check_idx_range { int end; }; +static void alloc_resource(struct pci_dev *dev, int idx, int pass) +{ + struct resource *r = &dev->resource[idx]; + + dev_dbg(&dev->dev, "BAR %d: reserving %pr (p=%d)\n", idx, r, pass); + + if (pci_claim_resource(dev, idx) < 0) { + if (r->flags & IORESOURCE_PCI_FIXED) { + dev_info(&dev->dev, "BAR %d %pR is immovable\n", + idx, r); + } else { + /* We'll assign a new address later */ + pcibios_save_fw_addr(dev, idx, r->start); + r->end -= r->start; + r->start = 0; + } + } +} + static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass) { int idx, disabled, i; @@ -271,23 +290,8 @@ static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass) disabled = !(command & PCI_COMMAND_IO); else disabled = !(command & PCI_COMMAND_MEMORY); - if (pass == disabled) { - dev_dbg(&dev->dev, - "BAR %d: reserving %pr (d=%d, p=%d)\n", - idx, r, disabled, pass); - if (pci_claim_resource(dev, idx) < 0) { - if (r->flags & IORESOURCE_PCI_FIXED) { - dev_info(&dev->dev, "BAR %d %pR is immovable\n", - idx, r); - } else { - /* We'll assign a new address later */ - pcibios_save_fw_addr(dev, - idx, r->start); - r->end -= r->start; - r->start = 0; - } - } - } + if (pass == disabled) + alloc_resource(dev, idx, pass); } if (!pass) { r = &dev->resource[PCI_ROM_RESOURCE]; From patchwork Wed Aug 7 15:17:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 1970118 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:17:41.2326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d1553af-f625-41fc-e303-08dcb6f4148e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9317 If alignment is requested for a device and all the BARs are already sufficiently aligned, there is no need to disable memory decoding for the device. Add a check for this scenario to save a PCI config space access. Also, there is no need to disable memory decoding if already disabled, since the bit in question (PCI_COMMAND_MEMORY) is a RW bit. Make the write conditional to save a PCI config space access. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * new subject (was: "PCI: don't clear already cleared bit") * don't disable memory decoding if alignment is not needed --- drivers/pci/pci.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index e3a49f66982d..acecdd6edd5a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6564,7 +6564,7 @@ static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev, return align; } -static void pci_request_resource_alignment(struct pci_dev *dev, int bar, +static bool pci_request_resource_alignment(struct pci_dev *dev, int bar, resource_size_t align, bool resize) { struct resource *r = &dev->resource[bar]; @@ -6572,17 +6572,17 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, resource_size_t size; if (!(r->flags & IORESOURCE_MEM)) - return; + return false; if (r->flags & IORESOURCE_PCI_FIXED) { pci_info(dev, "%s %pR: ignoring requested alignment %#llx\n", r_name, r, (unsigned long long)align); - return; + return false; } size = resource_size(r); if (size >= align) - return; + return false; /* * Increase the alignment of the resource. There are two ways we @@ -6625,6 +6625,8 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar, r->end = r->start + size - 1; } r->flags |= IORESOURCE_UNSET; + + return true; } /* @@ -6640,7 +6642,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) struct resource *r; resource_size_t align; u16 command; - bool resize = false; + bool resize = false, align_needed = false; /* * VF BARs are read-only zero according to SR-IOV spec r1.1, sec @@ -6662,12 +6664,21 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) return; } - pci_read_config_word(dev, PCI_COMMAND, &command); - command &= ~PCI_COMMAND_MEMORY; - pci_write_config_word(dev, PCI_COMMAND, command); + for (i = 0; i <= PCI_ROM_RESOURCE; i++) { + bool ret; - for (i = 0; i <= PCI_ROM_RESOURCE; i++) - pci_request_resource_alignment(dev, i, align, resize); + ret = pci_request_resource_alignment(dev, i, align, resize); + align_needed = align_needed || ret; + } + + if (!align_needed) + return; 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Wed, 7 Aug 2024 10:17:46 -0500 From: Stewart Hildebrand To: Bjorn Helgaas CC: Stewart Hildebrand , , Subject: [PATCH v3 3/8] PCI: Restore resource alignment Date: Wed, 7 Aug 2024 11:17:12 -0400 Message-ID: <20240807151723.613742-4-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|LV8PR12MB9405:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d20451f-6066-4a53-280c-08dcb6f418b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: GGKRK3zvl2UhbZ2KPr1ciNUk1c7qTAP2Fv1XrdmN0+fSG7ZHmGvXPSWtiNGLwQwbGra1LmvYRx+2I2IibPze7O7EhVwYOaUus0KfyRdv7k1EZpMho4KNJNA0IJL6cX2AAW5FhqGLBg3zF3NfG+nKxtzvt9erreLLitI0llaAYRtiIz0P9Yg2sLej+ny6m0M6F2lXNB+pvwjga8GotHkl1wTBnHeMf3A2SLOBvGNrBitifER+1HVQY5o2hu0VvLY93GqxIrjLfgWBA+L0OPK0dxJBaRt7JskRwRLEgtWeJyGXMV1AjmoXA9UjXarqpUG6pFgCQbIMvoQpvXPJc2/JoPPY6fRf+8FebDaaYeiyxojw65JXIAzfnXnCCjLKN2AaJDSpvZPdcG1YtsfjQl7uZ43HCbF3+mw51jvu/M4hww9tf5rPLTPj0UgcpnH4FyqAiCqSHncSoFfwY/UjnYk4aONtebTkXSYZQYO7oT0FDmcpZBqygkh42Mu15xb5cWvusxMB5lpzoIcK3OoKl37hhOhMwXkxsPIm/G0osaJEJTY6B8d+wxAh/jngQFRijiBI+vLwVjgBUzmQVaX2DnfuLbXU2yaz8nUuK61XnZzOk5d55nZoEuMox+9FPa0A6VRgjziTXwCE3s1LOJ2Hd1HmS65hnWevU+6PkJSKDGjE6I7nP/37V8KiJXpG+tWfdOnns9E7/5YD4SNAQbFPHaXwUMQnk0TTbmOofdENoAilE48DR/CZl9zDA3lYSMohWFMZVzvQz62ui7XrEqC3zs24OAKR7bCQxQrNg+azeJSSYOeerxNZJEzpmvh3V8ctLA/LRBmPOA8gduYrviabqknDz/UekaPDxVQqUM6jI9KX9+R4LalJZGnJUEnuUNp7VNHSk0gIKn+NIswRQ2zAq7b+TvymnyQpiR2575+d5vXaRkQDOY01kEN6EMWNb0awaPez8nGLSnQzcJeV+yRr6ZCMVtK00h8MXqBASTTj3X4btbnnzXta3s073SPfqNBv3GjVrbXaenxctfDAqn+STemJ8i7imPrJ5WoTahlGxSZ+95ucLFNdBNTAXdc3rmxBAUKk5DuWEGgrnik0+UEXiMp+hSBHyjVePGfe0wV7kPSgwBmeePj9NYPUw/HlKx29bHRGekP2oOrkZnYfzcn7O11736wW2u+BC6JQpqTP/CRuy+xxTXqR6CwfA8PvWLaINnVjXsFDood6ziw0APoagEhBKewY6Xu9xADBlFef0KWDBy4XFFZxbnHk4W+ETUh7/tbQFU0Ss0vh5y5TTwqCCPYD4O49YpQrGdWwic+BmeFF95Vc6kmytBv7yjzjAlZatdmozVJ3Bzn4MYny2EF37m9WXcpif0e4LmwhwM795ZD230DspJEwzdYkweS4XBbZQrL4SFLmIwRY18GsxR+1sviO3DXeULbmsP4YXAAZ4PG5Gak4IlBYTe4RNdnOYOFIfiTu X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:17:48.1737 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d20451f-6066-4a53-280c-08dcb6f418b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9405 Devices with alignment specified will lose their alignment in cases when the bridge resources have been released, e.g. due to insufficient bridge window size. Restore the alignment. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * capitalize subject text --- drivers/pci/setup-bus.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 23082bc0ca37..ab7510ce6917 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1594,6 +1594,23 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge, } } +static void restore_child_resource_alignment(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + struct pci_bus *b; + + pci_reassigndev_resource_alignment(dev); + + b = dev->subordinate; + if (!b) + continue; + + restore_child_resource_alignment(b); + } +} + #define PCI_RES_TYPE_MASK \ (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\ IORESOURCE_MEM_64) @@ -1648,6 +1665,8 @@ static void pci_bridge_release_resources(struct pci_bus *bus, r->start = 0; r->flags = 0; + restore_child_resource_alignment(bus); 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Wed, 7 Aug 2024 10:17:53 -0500 From: Stewart Hildebrand To: Bjorn Helgaas CC: Stewart Hildebrand , , Subject: [PATCH v3 4/8] PCI: Restore memory decoding after reallocation Date: Wed, 7 Aug 2024 11:17:13 -0400 Message-ID: <20240807151723.613742-5-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|PH0PR12MB8798:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ce2b8c4-72b3-43e6-c032-08dcb6f41c9d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:17:54.7049 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ce2b8c4-72b3-43e6-c032-08dcb6f41c9d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8798 Currently, the PCI subsystem unconditionally clears the memory decoding bit of devices with resource alignment specified. While drivers should call pci_enable_device() to enable memory decoding, some platforms have devices that expect memory decoding to be enabled even when no driver is bound to the device. It is assumed firmware enables memory decoding in these cases. For example, the vgacon driver uses the 0xb8000 buffer to display a console without any PCI involvement, yet, on some platforms, memory decoding must be enabled on the PCI VGA device in order for the console to be displayed properly. Restore the memory decoding bit after the resource has been reallocated. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * capitalize subject text * reword commit message Testing notes / how to check if your platform needs memory decoding enabled in order to use vgacon: 1. Boot your system with a monitor attached, without any driver bound to your PCI VGA device. You should see a console on your display. 2. Find the SBDF of your VGA device with lspci -v (00:01.0 in this example). 3. Disable memory decoding (replace 00:01.0 with your SBDF): $ sudo setpci -v -s 00:01.0 0x04.W=0x05 4. Type something to see if it appears on the console display 5. Re-enable memory decoding: $ sudo setpci -v -s 00:01.0 0x04.W=0x07 Relevant prior discussion at [1] [1] https://lore.kernel.org/linux-pci/20160906165652.GE1214@localhost/ --- drivers/pci/pci.c | 1 + drivers/pci/setup-bus.c | 25 +++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 3 files changed, 28 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index acecdd6edd5a..4b97d8d5c2d8 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6676,6 +6676,7 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &command); if (command & PCI_COMMAND_MEMORY) { + dev->dev_flags |= PCI_DEV_FLAGS_MEMORY_ENABLE; command &= ~PCI_COMMAND_MEMORY; pci_write_config_word(dev, PCI_COMMAND, command); } diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index ab7510ce6917..6847b251e19a 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -2131,6 +2131,29 @@ pci_root_bus_distribute_available_resources(struct pci_bus *bus, } } +static void restore_memory_decoding(struct pci_bus *bus) +{ + struct pci_dev *dev; + + list_for_each_entry(dev, &bus->devices, bus_list) { + struct pci_bus *b; + + if (dev->dev_flags & PCI_DEV_FLAGS_MEMORY_ENABLE) { + u16 command; + + pci_read_config_word(dev, PCI_COMMAND, &command); + command |= PCI_COMMAND_MEMORY; + pci_write_config_word(dev, PCI_COMMAND, command); + } + + b = dev->subordinate; + if (!b) + continue; + + restore_memory_decoding(b); + } +} + /* * First try will not touch PCI bridge res. * Second and later try will clear small leaf bridge res. @@ -2229,6 +2252,8 @@ void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus) goto again; dump: + restore_memory_decoding(bus); + /* Dump the resource on buses */ pci_bus_dump_resources(bus); } diff --git a/include/linux/pci.h b/include/linux/pci.h index 4246cb790c7b..74636acf152f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -245,6 +245,8 @@ enum pci_dev_flags { PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), /* Device does honor MSI masking despite saying otherwise */ PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12), + /* Firmware enabled memory decoding, to be restored if BAR is updated */ + PCI_DEV_FLAGS_MEMORY_ENABLE = (__force pci_dev_flags_t) (1 << 13), }; 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Peter Anvin" , Yongji Xie , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: Stewart Hildebrand , , , Subject: [PATCH v3 5/8] x86/PCI: Preserve IORESOURCE_STARTALIGN alignment Date: Wed, 7 Aug 2024 11:17:14 -0400 Message-ID: <20240807151723.613742-6-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|MW4PR12MB6756:EE_ X-MS-Office365-Filtering-Correlation-Id: 319bde24-8e79-4cc2-8d0f-08dcb6f420e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026|7416014; X-Microsoft-Antispam-Message-Info: 07LKOlNka9VkwSer+P7P7XRoP3I6uHq5zon40mUYRulUB8UYzN8l/OJP0bBnqms/p9RfS6M9keyKZZuO4AkhZAnNjbNMfQx0gAEYfTvoajQt6Rwk8Xli7bugqj08qINfAbdYZBm5aAoOBw2epSepMOgR21+Ukco+el8jf+utEAO8U40eDBAGD63GhkspDETgRWQ8PNCUAXJ7xgZb47GOtigAdpCQVACpwDJBHM27gYk2UME7u3Vl50nX7AL9UbC/MphEg1+3wrgg19uzS2jBzQkcJvYNvT5ETYm0nzCbGKtxk7/b1EdPxrMnQ9gkdeVjx6xJY8oX2O7HxatapfMPQ1h6oA8HiR9b6lnWG0wJl91eI461Hwh+MvIE3Y6eMC0GtL0uFs9af2k9bdouCL6SvF2nCXCzXWtTJvwJJ/AQPpRjCCglm/zIjMugsD5hajyzedd5WYcdyDQTlssOEZ5aLelHoeD/VrIIKywZ0Az0Qwh4od4zEZI9RutSLZbSZIzJQZtVLfJm9K0CdyRlWbuZQX2ZbVRnpXC1+GOjLgea/zL7ywRzvLK7MnhlE2LyW7LsgufbX2nQ/e6KEKDYJGs5PEOM6SiX4Oxd7XtXTo/nl2I4rq8gh9N3lbCf+AxJQSi1pehTZ9OD5BEp2cA7L9Or4BqSCM9qtKxeoXJmbVj2/l7J52Wnk4ijyUdvFTDQQzm0JN6rxd8c3Pih5Qb/wFaI9v4v9lkZRiyIL9/QP+ylwN2L1Kj7yaOwuERyutJMDnoOf0FZNKqG2Zuu8FOzEtXvx912gBoNpuRoHnkOCavEWpMKL/KkUNIJjCok7opZR2FReGBbxnbI266O3TEAChQvQPNmH7RLr92aIOQLHc1PpEkJf4A6JMLPV7ygKVcquFoL49iY9p7w0drJ309egpG1/15iqQhaTBYpMkO6z3polOXDw7KRta2Fdq5MZrStFHUBlt7NIpznhyEGBB2M++V5uWa5AE38djA34nixlvxobz6szGkNHukhHZ8on6xIee7bxQNI198MAupe5lBCaWsJ/4Tg/bbRs2EkYV9CMP32X2zWJW4VW7pErj0eyb55xOOeE5WobewKl35C8aczB4RYkktLGwcxuypvF72+J6Ed3+ACKm3b2fBqkhr3OYS3q4qK89GTL1NyyqXEmg12rIcdL7qMsgM07yi7Itp9GPVo19iNYMkSRb6ho01cGWiyvwka9o4DL+lA88t5+7y1Fx3dYMyJVQwzRZoczzjnCHKf2U/pJUtXsDyqm1jLiwpkhkfuQx6fG9QLbVTwxzqIMvGjgEiVD8NZltBw1MOZLUC/YynfAHoactTR47XlnRhdHK6+VcvaBJ2RWZE94fCKQuoPK/RvqveJPq9QHQSF23llYHeb9GvbCtAT6ga1vt1nl6Ni+54bqWjzsqJcfmtc78V8BhojZO0VHopHtFF5bVQhJByMdMgRal2hXsymu6eTIrWZ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:18:01.9045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 319bde24-8e79-4cc2-8d0f-08dcb6f420e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6756 There is a corner case in pcibios_allocate_dev_resources() where the IORESOURCE_STARTALIGN alignment of memory BAR resources gets overwritten. This does not affect bridge resources. The corner case is not yet possible to trigger on x86, but it will be possible once the default resource alignment changes, and memory BAR resources will start to use IORESOURCE_STARTALIGN. Account for IORESOURCE_STARTALIGN in preparation for changing the default resource alignment. Skip the pcibios_save_fw_addr() call since the resource doesn't contain a valid address when alignment has been requested. The impact of this is that we won't be able to restore the firmware allocated BAR, which does not meet alignment requirements anyway. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * capitalize subject text * clarify commit message * skip pcibios_save_fw_addr() call --- arch/x86/pci/i386.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index 3abd55902dbc..13d7f7ac3bde 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c @@ -256,7 +256,7 @@ static void alloc_resource(struct pci_dev *dev, int idx, int pass) if (r->flags & IORESOURCE_PCI_FIXED) { dev_info(&dev->dev, "BAR %d %pR is immovable\n", idx, r); - } else { + } else if (!(r->flags & IORESOURCE_STARTALIGN)) { /* We'll assign a new address later */ pcibios_save_fw_addr(dev, idx, r->start); r->end -= r->start; From patchwork Wed Aug 7 15:17:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 1970120 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Rao" , Thomas Zimmermann , Arnd Bergmann , "Sam Ravnborg" CC: Stewart Hildebrand , , , Subject: [PATCH v3 6/8] powerpc/pci: Preserve IORESOURCE_STARTALIGN alignment Date: Wed, 7 Aug 2024 11:17:15 -0400 Message-ID: <20240807151723.613742-7-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343E:EE_|CH2PR12MB4198:EE_ X-MS-Office365-Filtering-Correlation-Id: 9166e00d-17aa-4d2b-fd6f-08dcb6f42582 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: ERSb8i+uJZA7FSaFG4UpLyp1bA59gwJp22mhZGMHzGHQ6GFQPgGorrEtAYuqcYEutJ8pd4SPR5Aix6MwmjO9oK3iiu/0K43M8xtI+HmqRVxgZ2orEiSICszzVRf+GFxQhzfhh9F9yyCwpDxV8JnpXUav3w/izG0Ni3vpPDAnAAtYbxfVCK3Fxq+XqDzP4J7wcnkU/aLUyUP2eb+X0MktfzbaeELzt69wpm1xtl7Mq7ggRRnbBJC2moC6ld9U2CEykV5zlNkZrL8VO8AwxYMriMUthReF5Zf5aPplyJTqnPe8p6Yh1NumAa/vTW7PbGb2R1d0A0ZHgwE8qwXsVLHcjSh2fHkwNKkgKeS49vWyLQo/zGgX+Kor4lUq9LrZZ+baDpLnkdnMkyrtqd47RuX/6mo+FMFVhy/13CNEp0k/18F6+PSwg2dCBPVhhwdYYhlxcJX3yJER1A4l5mCxPGRNeWOUDZZLRNP9d2/xGXxZnWRFiHxYdy4UehSNytbuDEEPtk/XcC1QNJk03+wa9HjuyNbLLyPvjAeJ8pVFDx0DZWe7+2Yfw4apVu/XGNrg4kgHQBBdWGweNVc8c8j3/gmbj72ue+YAM4+T6T4nacwbbzOUd2dwO27bZ+QX4srccS0JsQH6iF+p07XnVHUR5XAxREAE6y4USm+3qk3h+HiJFWmdbL23FKOzFFcDIFqFw/eiLnhBU4GvXfRqM86MrQEXhbK1wlsHkQBzupZjWKE+MSwOtk1uuYv7Xs/hAQRwT0bCRA791PEy+5EtywUmEyOZl2ZNwRwSTbpju9foV8VNEpdb36zEep5OS8u/vde3e6ZFTwvtyZcuXaj5/lbR7nZfnfMKHKepLNw6EI0aQJ91nAusLqy/aJqCYD61rvwOrHRgcb+/DkuWip3FiHP2nEzWSlr+SdCtF1Sh93SmyKt3Fr/8oxpPIiUuOwdXsVrDUJ1s27vw+k4Tr5sM0UvIQUpUoj2JpsKG+DiM1nFddnUEtzVVw9D5d28gwi0SktCyd5mmM3O2QGOTxCFWgjSy1+NvxoXMeK9RW6zGfUcHjEmu6KBW/HUj04Iz/8pqwkeqSF+hPGSyPjs39Yc7IXzd9dlTQqIUY5oTOWL1CysmSyCCqng0oHc5I0unjwmp4W1ZxfrA5mikI8G3jcIS7aMGSaQlDTUnkvCzR1+47wlHbiSLHKjgmxVnLfwRm5maRUJVY/LdwnreJDdJd7bf8eKzh94kwzHPIsk9c1RLK/x3BJ7kY3EI7fhJnFrgzoBdc5ohjv3mcMH0TZmVO0VtsBuBevKX7gYVNbYPWmByW010ipyFFip9ivdxMW8ELzp5ZQaFisznIIPs3A53gREWO8plphrtNrJuinQYd8FEq6S+Gtk55WCGykCkpWSt0JAG1nAeJkr7fH0TpEAjxwaLxL8871joHBONVSWT1EaYdqwLOn0ro3Sou1WQx6zSaqd+XPpYhmHM X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:18:09.6291 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9166e00d-17aa-4d2b-fd6f-08dcb6f42582 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4198 There is a corner case in pcibios_allocate_resources()/alloc_resource() where the IORESOURCE_STARTALIGN alignment of memory BAR resources gets overwritten. This does not affect bridge resources. Account for IORESOURCE_STARTALIGN. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * new patch --- arch/powerpc/kernel/pci-common.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c index eac84d687b53..3f346ad641e0 100644 --- a/arch/powerpc/kernel/pci-common.c +++ b/arch/powerpc/kernel/pci-common.c @@ -1303,8 +1303,10 @@ static inline void alloc_resource(struct pci_dev *dev, int idx) pr_debug("PCI: parent is %p: %pR\n", pr, pr); /* We'll assign a new address later */ r->flags |= IORESOURCE_UNSET; - r->end -= r->start; - r->start = 0; + if (!(r->flags & IORESOURCE_STARTALIGN)) { + r->end -= r->start; + r->start = 0; + } } } From patchwork Wed Aug 7 15:17:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Hildebrand X-Patchwork-Id: 1970125 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:18:26.7036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f3c00629-51af-4df4-342a-08dcb6f42fa9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E63.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4168 As a follow-up to commit 0dde1c08d1b9 ("PCI: Don't reassign resources that are already aligned"), don't reassign already aligned resources that have requested alignment without resizing. Signed-off-by: Stewart Hildebrand --- v2->v3: * no change v1->v2: * capitalize subject text --- drivers/pci/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4b97d8d5c2d8..af34407f2fb9 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6584,6 +6584,9 @@ static bool pci_request_resource_alignment(struct pci_dev *dev, int bar, if (size >= align) return false; + if (!resize && (r->start > align) && !(r->start & (align - 1))) + return false; + /* * Increase the alignment of the resource. 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Wed, 7 Aug 2024 10:18:20 -0500 From: Stewart Hildebrand To: Bjorn Helgaas , =?utf-8?q?Ilpo_J=C3=A4rvinen?= CC: Stewart Hildebrand , , Subject: [PATCH v3 8/8] PCI: Align small BARs Date: Wed, 7 Aug 2024 11:17:17 -0400 Message-ID: <20240807151723.613742-9-stewart.hildebrand@amd.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240807151723.613742-1-stewart.hildebrand@amd.com> References: <20240807151723.613742-1-stewart.hildebrand@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: stewart.hildebrand@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343A:EE_|IA0PR12MB8421:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c9e4a61-4369-46eb-1628-08dcb6f42d09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 15:18:22.2519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c9e4a61-4369-46eb-1628-08dcb6f42d09 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8421 In this context, "small" is defined as less than max(SZ_4K, PAGE_SIZE). Issues observed when small BARs are not sufficiently aligned are: 1. Devices to be passed through (to e.g. a Xen HVM guest) with small BARs require each memory BAR to be page aligned. Currently, the only way to guarantee this alignment from a user perspective is to fake the size of the BARs using the pci=resource_alignment= option. This is a bad user experience, and faking the BAR size is not always desirable. For example, pcitest is a tool that is useful for PCI passthrough validation with Xen, but pcitest fails with a fake BAR size. 2. Devices with multiple small BARs could have the MSI-X tables located in one of its small BARs. This may lead to the MSI-X tables being mapped in the same 4k region as other data. The PCIe 6.1 specification (section 7.7.2 MSI-X Capability and Table Structure) says we probably should avoid that. To improve the user experience (i.e. don't require the user to specify pci=resource_alignment=), and increase conformance to PCIe spec, set the default minimum resource alignment of memory BARs to the greater of 4k or PAGE_SIZE. Quoting the comment in drivers/pci/pci.c:pci_request_resource_alignment(), there are two ways we can increase the resource alignment: 1) Increase the size of the resource. BARs are aligned on their size, so when we reallocate space for this resource, we'll allocate it with the larger alignment. This also prevents assignment of any other BARs inside the alignment region, so if we're requesting page alignment, this means no other BARs will share the page. The disadvantage is that this makes the resource larger than the hardware BAR, which may break drivers that compute things based on the resource size, e.g., to find registers at a fixed offset before the end of the BAR. 2) Retain the resource size, but use IORESOURCE_STARTALIGN and set r->start to the desired alignment. By itself this doesn't prevent other BARs being put inside the alignment region, but if we realign *every* resource of every device in the system, none of them will share an alignment region. Changing pcibios_default_alignment() results in the second method of alignment with IORESOURCE_STARTALIGN. The new default alignment may be overridden by arches by implementing pcibios_default_alignment(), or by the user on a per-device basis with the pci=resource_alignment= option (although this reverts to using IORESOURCE_SIZEALIGN). Signed-off-by: Stewart Hildebrand --- Preparatory patches in this series are prerequisites to this patch. v2->v3: * new subject (was: "PCI: Align small (<4k) BARs") * clarify 4k vs PAGE_SIZE in commit message v1->v2: * capitalize subject text * s/4 * 1024/SZ_4K/ * #include * update commit message * use max(SZ_4K, PAGE_SIZE) for alignment value --- drivers/pci/pci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index af34407f2fb9..efdd5b85ea8c 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "pci.h" DEFINE_MUTEX(pci_slot_mutex); @@ -6484,7 +6485,12 @@ struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev) resource_size_t __weak pcibios_default_alignment(void) { - return 0; + /* + * Avoid MSI-X tables being mapped in the same 4k region as other data + * according to PCIe 6.1 specification section 7.7.2 MSI-X Capability + * and Table Structure. + */ + return max(SZ_4K, PAGE_SIZE); } /*