From patchwork Wed Aug 7 02:11:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=ebehpE2d; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.199.223; helo=ny.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3185-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [147.75.199.223]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwn08dJz1ydt for ; Wed, 7 Aug 2024 12:12:25 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 9A6C11C220A6 for ; Wed, 7 Aug 2024 02:12:22 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 04A7918FDDE; Wed, 7 Aug 2024 02:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ebehpE2d" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2042.outbound.protection.outlook.com [40.107.220.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 964E715CD46; Wed, 7 Aug 2024 02:12:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.220.42 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996741; cv=fail; b=sHSzXgibkwJ6hO7xBIefG0e19sug0lIj7xa9Pr8nT62qnDu671mGDkN17XUQowbM1iK5tL4AdMvc4zlDfumePv7Oa4I+kzl27RzE1pVvAwi9M7DC2NeWUIr7eO7Mn6eAO2E2hJHi58DIpL1D8j1VX54dejO2afLmC0otPLfvuFs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996741; c=relaxed/simple; bh=oM4T3+/J8y2in2AFqLtrlN3CenDx5e712CjvISB+pAc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DsjtNM5gRuP9MmUT6Wc3+8rcQTiuEbRJ/YRprd7P0Iyj1eE8WpC3mgQHlZjWrYor6hmto9d0Z5/ShsN401vVC6rFSQsoR/8r7PLa/emuPjHZ+R83Ol2I0VrFXGVYnwS7c2XfquE8qWxM3Sg9Mcrc/Yjmx13t0OB6QVQxEaoj9jE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ebehpE2d; arc=fail smtp.client-ip=40.107.220.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=vYaxLGEaswLd2bS/VlXpA84+UU3Q3qYz/wgG8mTCfsE+4hE9DZALFuZytinc1nhMnR5mFdEos6QtobTgjV1e54CI+ja/+9C4Ub99kt22C0If1P3clRG2deXmR8hpb0ZRhzoKKsZoNT7pPeltxjNQnZ9g/Dbm6KEPWKzt/nla9pHsh+PJmYTvipuOqoMAhThY4Bwu/s3/qTurLUvKpKFzwTMXmEutb0wYJUq4YyV6VnjqHQAigNzF6p2UbWKritWcNf1pu8g17/XETdH81zIdhfTZRPZgJJwgXXFJSBt4o7NFA92J3XJOawzU3F/GLKppbDRZUmccP+VopnjoHYXtEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zGPuiMzEAn7Np2TvbJ8uX9Tve7sSyuQg4+G1wh6FYhI=; b=mbWcH99NOxn35rDeTQi1kOxe7w5k2a41lBCKdGHL2LWl99VR5MjNap//MkWspEe1XSYTDsn/7ds9TpCqSg8gA+kIUKBjhWZ3QE6q/p8O5xUcuuhJ4fGBa4wo4yy4FqKKYhvsV8djSD5qH22zI8fXCme2q/x2PejDKIvcuMLNk3JgNuynuJcJBwJwK+uLc1/ge+TqONdjHYGv3jw+m626Xyu61c5agHMCt4Xr84VM4z90boQL2kJhonyZG1ZkvOSJllg6tSLe05BoJrnKKAdPwqE82PjhDOMzL3BAGLRogasIylesrvdIrTxqcDMDx4LAstviymVSxTB4emQgOPJ1xA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zGPuiMzEAn7Np2TvbJ8uX9Tve7sSyuQg4+G1wh6FYhI=; b=ebehpE2dMrADeH/Pc6R2tjEyVJRfW9bU6X/iL0c78Xo2C/7fsXr1roYeLKNMXkVVSeOfs4zb6ihO2dc8XYregb4hE6l/yYQh6eLFgE9uP/xgWrEryJnEpZS68XrwnmCrQ5EibWhHY+HQTv3ympNI9zqU/+U5eYfWVP5qhU/F8WCXGwD/UokhlbrOgmqYkAFkL4Li6rX8+uKWpDmAE3HM0hdZh2dIaQDQ7kmy/cQzbCqwVeIY2Pzyqw+jYUJCVIzAaRlFDKVnp5BsQJFYvPDL8wlX7llVhNsX0lSDCRSgHeTRRaxo0dctD2/+5Azia04ym8JsTxvh7Xg3356vVxxk1g== Received: from BN9PR03CA0646.namprd03.prod.outlook.com (2603:10b6:408:13b::21) by PH7PR12MB5904.namprd12.prod.outlook.com (2603:10b6:510:1d8::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.26; Wed, 7 Aug 2024 02:12:16 +0000 Received: from BL6PEPF0001AB72.namprd02.prod.outlook.com (2603:10b6:408:13b:cafe::ae) by BN9PR03CA0646.outlook.office365.com (2603:10b6:408:13b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.28 via Frontend Transport; Wed, 7 Aug 2024 02:12:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF0001AB72.mail.protection.outlook.com (10.167.242.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Wed, 7 Aug 2024 02:12:15 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:11:58 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:11:58 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:11:57 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 1/9] iommu/arm-smmu-v3: Issue a batch of commands to the same cmdq Date: Tue, 6 Aug 2024 19:11:46 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB72:EE_|PH7PR12MB5904:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c3b0b9b-1598-42c8-ef9d-08dcb6865ba3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: ncxH5LvUhrPKxBm0Vw2h0tQbtcsAqzfJhh13rF2+F8JQGjfuJAZsrfbZXz8OKZAqBM35JlKQTZs9916nOjnu/lsaV+d3poQ17R81bXgLl7DIASF+BUhappQQVxppY3kIpwZEeC8+mxEn2B8Kedt7yLOoafnQx6UxhA8ovFCAtaeLC6rdzLpwnFqI0dA7iMpCIBml2BVx4YhV/+mE8LxFLVBks9RhwpSX5MNjqMkTKV9YdCutRkoUT2b2e6f5EdrPUzyuRudAeefcnJc3b5ZxP5pSqU+sD2JsO7k6xmUvbLqXD9IUB5oTTQRo63PGpYYSRrSMk8M8ZZtRJ3UhlE3IjG3TYH1Xv1EIdgMRNXG91Nyr7YmXRw3hODv11U7IOHP8yeyk9rGZuxHZiKhvjjLmpdo9SfUgTq57MKnvvqQNgfjR6htMKkd5ImGzLJvLTXQ+mfo2CLThsl/FoyGyPkYQBg+GZiFt2zAY6of7VL6oJmLLqXAdPBmIcL+73E0DNiiUwCxk9rdjBhgXAnSfTtFvPxWxIdLZxN5n+xEgwP0QghClBfFJEUOCwVyfD8tW0HaVm3M0N0oYLNRpNK9y9nw4Z8IBnZYGvniJBSrtQ4tcaV/AxaPHFpaTRytL9fngHdpgArbl4Aj/HrCasR6mXT3FUbRyX6YyK9nkdxV6bNDuSe2MV0cQNYCkUNKcX7CzZMvzl1PcAdnpc/Ybj8jOQsY8iMURMJ/cSGaOu2pg6dkhlSomyXmWwjQs+lz6PLip12TqjS4gzyofmhM0mq/YmxNGmPmXBS7f1UI0y+5RMTDyQExHOlDAnkn+s0BGerXTS+CYAZso7S996PKfBHWVevp1s0RC+lDLUbIa0aLC/4jsPp/dQzGjR4tbpQjhFYAtAgs7spKkPDRBuxD4ThXn7jPrqNfCKigheCxID7kDMk/zQ3K7ZA6JJgK1eFVMMnqN1z+sdZphoQpI3FaSw0vSCC4Lx0aQCIbXgEipZfz51wn+aHaI9p9B72Z3u7swHKQ5iWOvWvaHpsYZPEJzhRxf5cw6hq77jpT5/RCpndT16tieSYtZ9bZlDr/ZNJ5G0jXs07uWELiTec9l4+DJxuX2neCWdDq8kKowfQGqRl610gCo2Mx9j+p4gyZH/Soqyeb1dlKMrMjhfxe/+6H6y2YPPHQS+uFXug0TRPzDuJkbcWo76l0pDtqwG5QbPPxRe3FRcyUntVB96OjbQZ8VSzkrPoj6QhMLin7IwxpQmYC2FFz7RT3IZVZry/meih2si3MLc3Yxzvm80kXf24wkF+vuLjNPaulirjyiRFmZSR10QxLiQww1N9POAMGX/EQ8JjAhwilha6nDLPDweJQCCyXlOJPXBpZ0KhSr3byDShaj/VIiu5GBFteXZam7xkKNasGpmBZfqSu1dYVoOSP3OiOTinVZN7QjvC6mNXj/WmoghNjw8ydBHFC0QUWRkRXipU/dSqR4 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:15.7079 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c3b0b9b-1598-42c8-ef9d-08dcb6865ba3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5904 The driver calls in different places the arm_smmu_get_cmdq() helper, and it's fine to do so since the helper always returns the single SMMU CMDQ. However, with NVIDIA CMDQV extension or SMMU ECMDQ, there can be multiple cmdqs in the system to select one from. And either case requires a batch of commands to be issued to the same cmdq. Thus, a cmdq has to be decided in the higher-level callers. Add a cmdq pointer in arm_smmu_cmdq_batch structure, and decide the cmdq when initializing the batch. Pass its pointer down to the bottom function. Update __arm_smmu_cmdq_issue_cmd() accordingly for single command issuers. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 44 +++++++++++++-------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 29 insertions(+), 16 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index a31460f9f3d4..f409ead589ff 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -592,11 +592,11 @@ static void arm_smmu_cmdq_poll_valid_map(struct arm_smmu_cmdq *cmdq, /* Wait for the command queue to become non-full */ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { unsigned long flags; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); int ret = 0; /* @@ -627,11 +627,11 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { int ret = 0; struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); queue_poll_init(smmu, &qp); @@ -651,10 +651,10 @@ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, * Must be called with the cmdq lock held in some capacity. */ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { struct arm_smmu_queue_poll qp; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); u32 prod = llq->prod; int ret = 0; @@ -701,12 +701,13 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, } static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { if (smmu->options & ARM_SMMU_OPT_MSIPOLL) - return __arm_smmu_cmdq_poll_until_msi(smmu, llq); + return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); - return __arm_smmu_cmdq_poll_until_consumed(smmu, llq); + return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); } static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, @@ -743,13 +744,13 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, * CPU will appear before any of the commands from the other CPU. */ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, bool sync) { u64 cmd_sync[CMDQ_ENT_DWORDS]; u32 prod; unsigned long flags; bool owner; - struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); struct arm_smmu_ll_queue llq, head; int ret = 0; @@ -763,7 +764,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, while (!queue_has_space(&llq, n + sync)) { local_irq_restore(flags); - if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) + if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq)) dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); local_irq_save(flags); } @@ -839,7 +840,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, /* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */ if (sync) { llq.prod = queue_inc_prod_n(&llq, n); - ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); + ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq); if (ret) { dev_err_ratelimited(smmu->dev, "CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\n", @@ -874,7 +875,8 @@ static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, return -EINVAL; } - return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); + return arm_smmu_cmdq_issue_cmdlist( + smmu, arm_smmu_get_cmdq(smmu), cmd, 1, sync); } static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, @@ -889,6 +891,13 @@ static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); } +static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds) +{ + cmds->num = 0; + cmds->cmdq = arm_smmu_get_cmdq(smmu); +} + static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds, struct arm_smmu_cmdq_ent *cmd) @@ -897,12 +906,14 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, if (cmds->num == CMDQ_BATCH_ENTRIES - 1 && (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) { - arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); + arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, + cmds->num, true); cmds->num = 0; } if (cmds->num == CMDQ_BATCH_ENTRIES) { - arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, false); + arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, + cmds->num, false); cmds->num = 0; } @@ -919,7 +930,8 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds) { - return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmds, cmds->num, true); + return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, + cmds->num, true); } static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused, @@ -1170,7 +1182,7 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *master, }, }; - cmds.num = 0; + arm_smmu_cmdq_batch_init(smmu, &cmds); for (i = 0; i < master->num_streams; i++) { cmd.cfgi.sid = master->streams[i].id; arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); @@ -2021,7 +2033,7 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_master *master, arm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd); - cmds.num = 0; + arm_smmu_cmdq_batch_init(master->smmu, &cmds); for (i = 0; i < master->num_streams; i++) { cmd.atc.sid = master->streams[i].id; arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); @@ -2059,7 +2071,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, if (!atomic_read(&smmu_domain->nr_ats_masters)) return 0; - cmds.num = 0; + arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds); spin_lock_irqsave(&smmu_domain->devices_lock, flags); list_for_each_entry(master_domain, &smmu_domain->devices, @@ -2141,7 +2153,7 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, num_pages++; } - cmds.num = 0; + arm_smmu_cmdq_batch_init(smmu, &cmds); while (iova < end) { if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 14bca41a981b..c1454e9758c4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -570,6 +570,7 @@ struct arm_smmu_cmdq { struct arm_smmu_cmdq_batch { u64 cmds[CMDQ_BATCH_ENTRIES * CMDQ_ENT_DWORDS]; + struct arm_smmu_cmdq *cmdq; int num; }; From patchwork Wed Aug 7 02:11:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969762 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=EwAsMig1; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3184-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwl1XJcz1yfM for ; Wed, 7 Aug 2024 12:12:23 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id BAF23285B04 for ; Wed, 7 Aug 2024 02:12:21 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 38F5C18FDAB; Wed, 7 Aug 2024 02:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="EwAsMig1" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2053.outbound.protection.outlook.com [40.107.92.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A0EC3C092; Wed, 7 Aug 2024 02:12:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996741; cv=fail; b=smjLCh88Z/tCFB2gJJ/xByEPYAiyMZZbL29psAXOmKf4Z3GW8JR9PuBGhLt/9BV/+yAp2etVrWZqo2gtEe2pYss1VtUpZz0n773JBEablv7jBRtvUbQCLs80lYh7U9B5ZcCKMIxK4Hj5QxxWvoCIe2DXu4Kh8VI/KYmEcvoex7s= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996741; c=relaxed/simple; bh=9JVv5wpOW+KnXOu60yk5XUwKIouiVliwPUePTFLjkPs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g82o/TCgCzD0HrvJI789D+xftCOMADB8EEpgVSyoiXbWvPBCaZY6VisuSgzonDjZbxwWDpkVFwXVCMUYKMkXY1O303QRxHyCrPgHqa/Vw5dQ2GTyuvHbV78bXcso0GdulI90Qk5OO9WXWvVZh9beHluizyEwfz3Y9H+K+nDORLk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=EwAsMig1; arc=fail smtp.client-ip=40.107.92.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=n2UzBBLlY0zKTSC+5nYDvJpZdJZzqdF5koL/DC3MqwHH5JGRgNAFQOKWAZKw3g9IPWfDqgbBkz2ycUszlLDWeDPn4/kth6Q2kPzylFNexI9buARua22TmQ/YZAXrH4kk0ullhYSmMgJokNljwclwnh4IPRUIfWhs8/+7ZQ7HrVEGEY5HxtvWTI3AWHWgbAu7QEGPQXqMh1xXTmTt+EXSbDsKLSFB3vO36kOHI2fEc3yApKE77dzzZE0GgZ6DEyoTaXGESilRn36wY31vbHlHDBrdRIZpnMgYMGGaEL8wL9uz5Mn2kPtXC/9C3xPjB9+drQDIdN9uDkTAhpTGd1Jcrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xZytuDAePASyrbT69qaP95OOcwIh/3f/lQNIQzMbhhU=; b=qh4Jlx4D2RcoK1rLnKYnK+kGwCUO3SE1EAkjfGk81a7HzeddISRCWMI00LzfHfc+L4wWQ1qxHgczR8RyOVqP2bAykCC6VSozQ5PgYIBoRjYmhex57JJ+Bp2F3LBI9zPtYQqH6lkceYyO2EG8lQW0FYY+1tSZfjGoznf/giOK+25J3Zj+Rs+CN0S0SA/tV7ZlNqbSho0g/46rLk4IhtI+2FKE2MMxXb1g/MeuGGgqwTm2oJpLhGBDjF0n4vC89PW6ZLUXBEs54b0Na0aQD4/RkGAGjMqNyS3cJjJvoEkLf1l1ftwa32evGRZiJIfkHZgTHPMYhxRLkIEfFn9B/MwtRw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xZytuDAePASyrbT69qaP95OOcwIh/3f/lQNIQzMbhhU=; b=EwAsMig1fHIOI2pqmKhDql/FeFEdWEl40ACjAStKCUNJf+JR/IELbdC3R9IOxY/nzLeWxcJrrMrMf1ZHu9aT5+Sahgj0MicNiEUN3CQnPUzuRVr4UzdEoxez6/yN/5439bbAmklKHvhL5dvF7B3JJPBziyJryDsmUl9/Iy02pd+bDuPewNft9Pt5Pc++VreEVWPFG9hRAP1n0hE2lZkxCri0eXl63JphPSiNbbbaTfLGc0Z74pZCnMqSiXTX9jIW2OGjZYIHcYSM44sYteILUZLfrMVlhlsJ3dgKSq9gZge1aN5U50YAKYU6KU2KCDOwZTdhC/g0sqPhl7iWXn44bw== Received: from PH0PR07CA0011.namprd07.prod.outlook.com (2603:10b6:510:5::16) by SN7PR12MB6789.namprd12.prod.outlook.com (2603:10b6:806:26b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.22; Wed, 7 Aug 2024 02:12:14 +0000 Received: from SN1PEPF00036F3D.namprd05.prod.outlook.com (2603:10b6:510:5:cafe::76) by PH0PR07CA0011.outlook.office365.com (2603:10b6:510:5::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.12 via Frontend Transport; Wed, 7 Aug 2024 02:12:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3D.mail.protection.outlook.com (10.167.248.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Wed, 7 Aug 2024 02:12:13 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:00 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:11:59 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:11:58 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 2/9] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Date: Tue, 6 Aug 2024 19:11:47 -0700 Message-ID: <9e59a460c969357a98b3434ed5007ddf9381899b.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|SN7PR12MB6789:EE_ X-MS-Office365-Filtering-Correlation-Id: d9d8f44e-3594-4203-7728-08dcb6865a73 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: JlGxJVC3kBttyqQ4hkp3UXOuIq299k8XWlOyv2PWqjYeVjKntf45CDPRGt0V+4ppXxYHaGol2pIrIqDtEDcJ9cttBuPgWo/0+QyQapApvoJigJsAYrheYsx6rXyHaqq12jhHyTR73b6cJ5Fzw4hZVyg7XTtH0PcqH9qvx6fj5JV15olvxaNQaiyfvmBfDyc2v4nyH+VjVaKzLwDLxxd3skrl64HruV/pk58dAUk5KgBxmmrcmiHT4sl/zPze8kRptWeWr2DHtfchesD3jjw4t1nggkt0ufalHcul87Andyvku0X5TEp0ZA6LXWAzs0LobNEVFv9V5jDoaKRGF/uw2IV3dkjgVoys9cUsb56xG4UhRl9ylJkjTwQZgp3UJLLzH9JhmN4i7WfWJT75+Sii/n4OeXBDwxCpi8gWhIM/MBnQlsZ7kUQQ/saR+qNxhQL6oNd+3U28KfgrYOr1IyXaj15PNZNT+blOYMLibzqqMo/pqi0N2z4ULki7d/s2YdgbYC+fYt0YgZQEZtLFeoRIxCl5J+Je54dkjPjb3riqtLlL4I6Vp6QGkVH+vsk+Qo6XF4D+z1qSyublR+AzBD4uhanVW3AnSg6TV/bgWsLx/JmWetpWNiEUzIq7QDb9z1D4DI8b+qUy4J7Git5EJuT4CDPc2CrbovEcSXGXRIMKAaYtFt4hWOwdd8rcghoCTNVTbIkaCkkRt+gRXj8Rw51PEnbhg+NwUqIrjWzKBsle3jMvEZSs4fw5X+aw5Qwp/R1EcLPucT0G/JB7Qs+qYWOxN30Lbml+uUja0O1Y2swhvIiusEm6AknxeNnDGYUHv/U8AOWltAVxdS5N634x7rtz6gLYjc4xkfKNwKnFBAvx5VyZ8OmAcIkeqvW9JF5lQBwoi8DpQAXY85bDe90WnmcN3VtXgghPp/mOsyl/G1YRapsUpTLpQNGISeG9LJorOil1NpQIph0G6MLMKg/EtzWeSEK4BWgPz/tE3sotfSbSsUgaaR8W+wo4QESzFnQuo3UnA2QKAIrHHkklynuyqQ+nsi2nFD09wweSmI9/dizOeuI2VuRdBRb50doUANQ/6SbyhlG48zTAXyFhv4UF6ushUSzdHcMw0DTb55yVSqLEPjGnGuOyiP8xWqaUU8bD/hgTJVMQuQ7WXpwykOdedJ1Ua0DXKixZrviY+UMSBG/tTkEzpeB2e0ZTW1WjQKJ2kwgtBa7g+qhGgiRQxyjdgTD908Oqp+A0XWB+rnK3ql/z8vN1jxguxM38EtViA3pR2YeaC2yD6uTxTgsVPXEPFjVstdYrNn1BWef3DF2EybBaTrJrXCFz1yl7wXoGCZu9WEbG4ESRc/yRkilZ2Ng5rcglNHs/pagZGxVk28N0AG1WBhKR1tqZRFlBSD92nToJfH3XwUgMzCuIvpp8j/92dk2Vw84PWF8yj+B7ozPXsoGuxH5qU2mHisMP+pVr4GF7gKCs X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:13.7751 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9d8f44e-3594-4203-7728-08dcb6865a73 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6789 There is an existing arm_smmu_cmdq_build_sync_cmd() so the driver should call it at all places other than going through arm_smmu_cmdq_build_cmd() separately. This helps the following patch that adds a CS_NONE option. Note that this changes the type of CMD_SYNC in __arm_smmu_cmdq_skip_err, in ARM_SMMU_OPT_MSIPOLL=true case, from previously a non-MSI one to now an MSI one that is proven to still work using a hacking test: nvme: Adding to iommu group 10 nvme: --------hacking----------- arm-smmu-v3: unexpected global error reported (0x00000001), this could be serious arm-smmu-v3: CMDQ error (cons 0x01000022): Illegal command arm-smmu-v3: skipping command in error state: arm-smmu-v3: 0x0000000000000000 arm-smmu-v3: 0x0000000000000000 nvme: -------recovered---------- nvme nvme0: 72/0/0 default/read/poll queues nvme0n1: p1 p2 Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 -- 2 files changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f409ead589ff..f481d7be3d4e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -329,16 +329,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); break; - case CMDQ_OP_CMD_SYNC: - if (ent->sync.msiaddr) { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); - cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; - } else { - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); - } - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); - break; default: return -ENOENT; } @@ -354,20 +344,23 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_queue *q, u32 prod) { - struct arm_smmu_cmdq_ent ent = { - .opcode = CMDQ_OP_CMD_SYNC, - }; + cmd[1] = 0; + cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + return; + } /* * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI * payload, so the write will zero the entire command on that platform. */ - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { - ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * - q->ent_dwords * 8; - } - - arm_smmu_cmdq_build_cmd(cmd, &ent); + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); + cmd[1] |= (q->base_dma + Q_IDX(&q->llq, prod) * q->ent_dwords * 8) & + CMDQ_SYNC_1_MSIADDR_MASK; } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, @@ -384,9 +377,6 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, u64 cmd[CMDQ_ENT_DWORDS]; u32 cons = readl_relaxed(q->cons_reg); u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons); - struct arm_smmu_cmdq_ent cmd_sync = { - .opcode = CMDQ_OP_CMD_SYNC, - }; dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); @@ -420,7 +410,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_cmd(cmd, &cmd_sync); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index c1454e9758c4..6c5739f6b90f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -518,9 +518,6 @@ struct arm_smmu_cmdq_ent { } resume; #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u64 msiaddr; - } sync; }; }; From patchwork Wed Aug 7 02:11:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969766 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=q3ChGv0p; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3188-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwp6KRYz1yfh for ; Wed, 7 Aug 2024 12:12:26 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 969DF280CD8 for ; Wed, 7 Aug 2024 02:12:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 35DFF191F78; Wed, 7 Aug 2024 02:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="q3ChGv0p" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2083.outbound.protection.outlook.com [40.107.244.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A1BD191476; Wed, 7 Aug 2024 02:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.244.83 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996745; cv=fail; b=qGjGS8xdJd5VeSnMFctKRYIbidh1PL+D3Kiktet8lqIy9+fpz1L10q975Tb5dHwi0aELB+ehvcUxAE7cg54xXpgl3hDwk0zqMxnazGJudeV/glQmc0/H20mO5ut7yets+s950RHNTmfNWKSD60cx8GY3PJqcfuiH+/swjcH9GBA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996745; c=relaxed/simple; bh=mm9qShw1OpGuRfsK0+zQq3ap6LNaPDVAdVJnhmmhNYc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WJOn1POxW7eGgqCim0KFgnk+FQegKv/gRBtbkrxLFKsPjSgQemVZXfmNU4gctgqnvR4QuL7tifGgRwFH9VBpoVjZXDSGQ6vRhAE80NOTARmbRaJJV/hBpFdi7VlCaC3ftCCQaTEjyzJI1zHFdKnS07RLYXEugISUKJ0HDQdriZI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=q3ChGv0p; arc=fail smtp.client-ip=40.107.244.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ykR/av5vVnGUdhKzJACfW7HqTTl4Cjx8fuBqUXkJqCQW3JFR4kMLoeiV1jtaXrFsvocDC4+5q4VbP4/EZBymK4pN0Nv0SHlE1bR2nA1nnojUpqNkbHnr20CNm1Eacv3bcXepG4uiSET16d+nCKfsA0ev27tGh6zBdt9S9Eqronm93VLp0p14I65yRsaf9PIHD/0OBJqqsWeUDOC38ulPWAhRN1qyCrviLcbs2K5InhAzq7DEYvjYaXl5UhY8yTVvjgH+qDs1h/BjSSslSCLnUncV9DE3LkSnIAJbpDnuho2+QJCmDu4PO95kplb8fHuGgBb0AAk9GR6AfwC/NMoGFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MW+zoXnHQz1m/qt5hhvIW2ivhVGYSGhlLVjkDlQRqs0=; b=KqyMewwOF5ieGtOyucwUmw1+UgHwkyTaDsSBK3cr3KcSZrvxVSMMe7lBPXKL4RJiVBZ4Y9Cun8JhgJDmrklJnpf5hLWSJxKvs5/o/z/14dzvvWbF6cqVHzXrXJCIS5ls0jkr0KOeDs9yPrSVFAvTjxykOG52l/SYzOAv5n0tHqkbmcxR71yvqrxf5u1jcyMT2sp5Ce8epvdvKrEnhYjx5hKxDM21RqHBg2ZHt0jFcOv/N8EA9bj0iDA+CQK2BP/LxC1faNy1sWu0PJbOEeG+BAhE+pmgax9SAYIe5la8v/OAr8VQ+uGij3en8VStD1pQ20HleNV3KLusrT6f9Fagdw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MW+zoXnHQz1m/qt5hhvIW2ivhVGYSGhlLVjkDlQRqs0=; b=q3ChGv0pekp56PVrKf1A2Zd2fnbHrkiT4WgLqR33IJMMQhQptj7CH6FyHL8VA7saQNmk3mG17tSfXo//2XxEtyFfm6EQbIO8g4MwIGkygG15RWLQEkyU9c0Lv/tTp1FxWhJj8axsev+2PRKDipGkLbDZV3CGbn/tE8Furua9+pNYOIvV9nY8wI5tAzO4IYuW7qEvrmYS0yoM4gFacmRFgYbFMSPi9LJn9c71MRkuPShk8Wr4TSS8I5Rbayq7hUFgGUyndoWsURR+oPrKi9z5p2nf+nJZqqcKjSTCsHb3lNL/zKRAXBMumM1jdXkMkP7i0Qz/8ceoGlM0F7vDXkrPpg== Received: from BN8PR07CA0014.namprd07.prod.outlook.com (2603:10b6:408:ac::27) by BL1PR12MB5825.namprd12.prod.outlook.com (2603:10b6:208:394::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.26; Wed, 7 Aug 2024 02:12:18 +0000 Received: from BL6PEPF0001AB71.namprd02.prod.outlook.com (2603:10b6:408:ac:cafe::c3) by BN8PR07CA0014.outlook.office365.com (2603:10b6:408:ac::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.27 via Frontend Transport; Wed, 7 Aug 2024 02:12:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF0001AB71.mail.protection.outlook.com (10.167.242.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Wed, 7 Aug 2024 02:12:18 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:01 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:00 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:00 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 3/9] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_build_sync_cmd Date: Tue, 6 Aug 2024 19:11:48 -0700 Message-ID: <728977eae3b97466c4afe89111ab0543b0eeb59b.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB71:EE_|BL1PR12MB5825:EE_ X-MS-Office365-Filtering-Correlation-Id: 75286605-6d1f-4c68-128f-08dcb6865d0e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: fH/ZpPUvlUzZdzZpZGNNTT0ATGOZp7RL2R2/7OWxONQ7D4K3b35eCRn+N9TPHMou/2ZBGGTbTPnQR2R/xRgQduV73M5Jh4vF0uHtImAOhoVc3ltPU+3n5kjtP4F4GFyP9PdZDrDL8E/iSuhv+i68B5sJXLiMXDRL0Y3hru5iKL5nsQS5oRlX+rLLDYGPRhoxQi8kTRobRWqPPONWonMZwF2MvW3r3LrgeCQhyQRlklkfVb2hGwR+21W/YmP80pibN6kd482rhFBi1R3AXWs8DylkUmurFkqKQ/ILNaxlPAKy22XV8kXprp42VGXHo/wZXgDebHGTiK08BgguEI210VboVcVtli61r/3VlAlHq1Pytxnv0jEWtF0LIJjwKyOHmLfd2On0qKOMN/lzZUed5qYSXo+Bk7KGYOgN4ffs5eYTgWE18jn9Dn3rIhfVz+tcPUHbFZXWkTLntc0js7gKUFezULd1dJJvsSXLU4sdgOEILTvr9TK3B2CtmsFsh9xZ8WUXIe5jrpIChiHfTCeeT3590dUIHA46sCaEDiV1FhqJDSs8jhq5mjZTa/VGnStguMaMm8BdbGtMBZLgq+GE2dohYS/ed3PBKHUDiPGROrCHYAP2+fQvYT2scJrRnoN6nMda5L8BxEcXJ11CMzv4P236REUzNpDeT7/eAN2RbOn2Ezyy6DjBYcGTCh8JwH4lnWAPNL7QghqdwFggj5wjHSVth48vJNOfYTBBmabKpZf+KM6KPoqs3AuYkraTpQDb27X1tsjvQ1DoGghzS+Ik7I5uvov2YaHRVMDB4zW36YIPPe0UTwrPJLabgZJV2Rt+qRRt1T5ogNG08xJB64u2QRsPRT0gIjDqtkRGVldB6+ja+9SupYu5oIj9ypsOiODQtEesVI+JbdHCqKvxJOTCfYwkSxxDasGXvfxedJJsoNPb5Ns1ZLcJuaZA5RaIIk8W2PelK+Z1Rn283ME1lgBHH4R3nl1ARBymMDNHQxh+2nNXdvp5wvj35EcVSOTSJHfTyJtVH72HpLt0ksIUcXrEfFgGRB+CdFtGQw7QrowUbV0AzvdORqii6cqvBCcg77ewEPQnQWuCPqersnhYcUf9DHrp6ZTdfiqnMPHFV+v2WMWcWSl3iYdtUtiZ49d+1ZB49ZVRRyvA2q49oNtjidfdZB7ntDqG+/1fdl3Wb6rB7eAKDxtgycoAsu2/eTPO0p1bSomd6S2w9c60/g2l46XS9SAhA1UMplz/qMQ+pC1AyN4GUS4379GBlXuqfMtOzX8HJ8STQcNKhOs5p7ouKCslqx1Z7bng0Q7NTt0YPkjq9h4W3XhGr2dTznMPmLKgnfcCXNQEM6k+O17pBtmiblWXmZBGLbBU8HCvVSYOx8dTA0TIZlpKIbkE/fY7w2gthLOs5sujUE7dV7Axm3wekxarWquyCI5FJBFdZmp5pz09iUvFOvsMo2Ev91PYLgAZSw/9 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:18.0969 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 75286605-6d1f-4c68-128f-08dcb6865d0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB71.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5825 The CMDQV extension on NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC, v.s. standard SMMU CMDQ. Pass in the cmdq pointer directly, so the function can identify a different cmdq implementation. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f481d7be3d4e..d11362e9fc8a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -342,8 +342,10 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) } static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, u32 prod) + struct arm_smmu_cmdq *cmdq, u32 prod) { + struct arm_smmu_queue *q = &cmdq->q; + cmd[1] = 0; cmd[0] = FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CMD_SYNC) | FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | @@ -364,7 +366,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, } static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q) + struct arm_smmu_cmdq *cmdq) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -372,6 +374,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", [CMDQ_ERR_CERROR_ATC_INV_IDX] = "ATC invalidate timeout", }; + struct arm_smmu_queue *q = &cmdq->q; int i; u64 cmd[CMDQ_ENT_DWORDS]; @@ -410,14 +413,14 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); /* Convert the erroneous command into a CMD_SYNC */ - arm_smmu_cmdq_build_sync_cmd(cmd, smmu, q, cons); + arm_smmu_cmdq_build_sync_cmd(cmd, smmu, cmdq, cons); queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); } static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); + __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); } /* @@ -780,7 +783,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); if (sync) { prod = queue_inc_prod_n(&llq, n); - arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); + arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod); queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); /* From patchwork Wed Aug 7 02:11:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969764 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=bp/J4BE3; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3187-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwp3RX2z1yfM for ; Wed, 7 Aug 2024 12:12:26 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 0C9A2280217 for ; Wed, 7 Aug 2024 02:12:25 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A1EEC1917F8; Wed, 7 Aug 2024 02:12:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bp/J4BE3" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2077.outbound.protection.outlook.com [40.107.93.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A703F19049B; Wed, 7 Aug 2024 02:12:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.77 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996744; cv=fail; b=YvbWhxZW61WBIMfLzIVk2LBSFKzpl37hez2N9cswxQtoai3n5hEWMUoBlSV9Ji0d1zj2fv3tb6ZWbnSPXVkP+M4s4dzjGqVB/kq84wahIZdfHQFWCeaIlTE0oUjNJwZhKiAS27fvM/QOoRwWyMLav6iBEEO+oW7o7Dm09P3tMms= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996744; c=relaxed/simple; bh=FOtxfxaYAoIk8xIeO1iXUaPa5UG+9sm2MTVP87KN7e8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HxU8UPmaZoQjGZZ2/WohBsR4s6QWkuvGeQNqWlhPlkfSq3C8HkGt+Ae0y+rhsmmXtoo7uWR6vG9CTCE11tZ5/wX1svuaC/0Rhzjs8FMCc31PDmycf4oX1gHWLzhSUO7ywMLW45GiKImJK12lgWNTDWhI6sVx5s/ABm13Rac597c= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=bp/J4BE3; arc=fail smtp.client-ip=40.107.93.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=j6eqBUrCv37N5tzuNHtJ35SuLadlsE73zgck5unkwrtP6QpgO29pjZ7y388H8gRmIsqqluRhyeymvXhsqkDu2QhWO1buJE6H+SaCoF69joqIpkFo80d2dml0j39xXxHehmjY1p6caTojsIYHpOmmcDn26GcL2gK4O47B+8NrwtAs3nUjeBzdTFGUJLiKDYHFDRMqAefIOkxtJUNsQdYPsf1sPKhr0PCAWIQCDAtLe2Iwmaf94Y27mTvn5ZLxtxtRYK2uafqbgNGSSaOZXqPGqQmNrX00DdUz5oiZDFnGKDoTtDUFfoFfVKjTJHSyk7SQ0wo8yJ6ym9zyw/ahTBaGTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PH3fZGMEtUGhGnMQbl1O/tOUaALDMgL8C8OqKbkEp6Q=; b=oZ/o/d3vENs+g1uFx572K2gMyTK5v1uMIrYV+DkQsqorNfAvWi1/RstbtFsLpcHfxi1rhjKyRgT75LqUuOzsasgoGa367KjmF4QABlpX7Udke8Ko/G36RTcoufJvpBs+s/fVLmCuflLsS0mgub8/dEr/VhxRNaKsdA92G71qD4GuIFABguwVMdoUVzq8MUWea2KXcfQHYjaDE47zVm9hmvs7p1WzehmCM+Jcb0bz0OED3Y9zXDobSsCFriS10UFVuFjUT9NjMCD0qFE7gaBSi0sYucISY4GE/0bay9D+UAN5c/MGiDVNsISTzu5Hx5Aaxfx+B6SFUqxuBLODJ0Wpcg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PH3fZGMEtUGhGnMQbl1O/tOUaALDMgL8C8OqKbkEp6Q=; b=bp/J4BE3UIJKR/uqWsUhOdbGjwbkXwY4B/tUbDiPUZwKvJMbLmSEiLt9oWeqEqOhXefP6u/L9GILEK6dsbZFDcsSnKo7qXOGSk9enpWNjHAbxogFJGN2ld/fzlCgYkeOG6Nq76AxtfqwHrt9BQbdd205TSDnD7D3aFUH/AjHhFxxz8JVJqTk/a4Gkr50Xauh6gZMgrYERVifVJMtwndKXv74tyze8iGJLhAp04Cm4qgC9BPqdvckUaIWYvmgQwo4xK6hCxHbkFBUfqv5HN1kq1Kp7+dhETHsxOaPzeO3nXsk1ObREz+YjtutQA7Uc3n1CXN2qC2U5BBHkhsnd+nd5g== Received: from MN2PR20CA0034.namprd20.prod.outlook.com (2603:10b6:208:e8::47) by PH7PR12MB6811.namprd12.prod.outlook.com (2603:10b6:510:1b5::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.23; Wed, 7 Aug 2024 02:12:19 +0000 Received: from BL6PEPF0001AB76.namprd02.prod.outlook.com (2603:10b6:208:e8:cafe::5d) by MN2PR20CA0034.outlook.office365.com (2603:10b6:208:e8::47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.25 via Frontend Transport; Wed, 7 Aug 2024 02:12:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF0001AB76.mail.protection.outlook.com (10.167.242.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Wed, 7 Aug 2024 02:12:18 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:02 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:02 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:01 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 4/9] iommu/arm-smmu-v3: Pass in cmdq pointer to arm_smmu_cmdq_init Date: Tue, 6 Aug 2024 19:11:49 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB76:EE_|PH7PR12MB6811:EE_ X-MS-Office365-Filtering-Correlation-Id: ad4ba053-e0e6-400c-0d07-08dcb6865d7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: uv1ri9t4b7jK9nYR0EGvXxeAXB/O7ANEdYRCusa7RMCjEl+ToJKEFVJncqpZy1mNVAbsb2FvvtdpZBkJtRg7prwVIQYa+OCwYBwpwZjenUYHHXov/9FQG1drky6nCTBFdKNKwA9YniRV2un5rRr09paoXVfjyaKHjGQ38Suxbz/XNCD8FV524r0x6Pi1C6y9H03nNC2Xfd8fI/pRiWtXDTCjJ1qHpgAaICyqxB/Zi7u+Thp1QLZWJ3vfDO2NWYtjPKZpFGdNIbyM4ggQ15MS87nAd6nh9vhjfnw6yf6kzZuD/JFYpibNriZvC+raAfm9ZXwEgptGeLAZmgNJ01OE5YnpsDl1mQPo0EhZtEbgg1e9pNpRWhcZX3jKYeFDsON+xxuqeTs1UQ0+Z0V/A0noTLLNEJhEWJ1ABve3HKzOOAyC+OxQUQC7GtgLzTwSQLnafiePbPOnqDO135eJV4PGAcqhAg3OqVkIBizhLk1EZ2owfjYDu6G2PRwSSDX+XBPKSjsZsoCN0bNB8HpMJOW/xDP9S57LQsueBQzh8yJo8tNxzUDANtR/3yYUnpyKssDgGSClnFfyJQqqlh/LuHkMKKq52KNMJu8czTbHwV1LVFqBKIE4MO/iaRHqjqRaceswIvKBU0r5ejzEoz/VefQ1yES1oCDzyPUN3tXZ392bzQ+7jdOfLjolT3iMhxkrfno5OpCcZ/FV1TbRFTTSxLb3SinNNhsG8OT4/9CDiI+moURhBvoyOQrtBUuZL++VVyw5KxoxvlWPwkV0ncw+A8Hjsgu0BvbeWuLjyaA0edcsxGVcggYcr6KwyB6MG67iZUC1OWtA3yEz8m0m2E9duTjNHww8ckmDHwgYdPdgN+aPj84ICHICSV+vx7EZtP4nkbaqyTXuAxmXNvg5bRFmigW7Xfcw4M3bkiWSywSnfapI85+HlXVEvN/HcR/3zy8r+s7BaALp6dpFo0NvYPWU4tDeMium4cy5SgeAvnAuVkn03r9RdBNj5u2TGcVG/mbrFAWfbv40RudQDqDvrUl+l/y1RDqdV+vVuOKgpAlYbcqwjXaz3LjX4PI7+37cciFb/N7lqzxNAWCK79u/HFsqGdE+idcT3wjOCsJM2H7FAEEeEpzMjbKjSss3+cgkisdn0poVwhnhEAUlFq/1iUDv6Zq4iwxn/TWQ+Z6OVP2RypHDUybwWBP7Zq+4fIq7utBOg5Q8Ep1Ycac+J18sKjPhGs06mppcXsaMSNXoBx9M50OF39pd92GqUUz03sGund/4KdW7rSR+kxlgyfdsvWSZGMUG6EHzbujnmOwYXod6itS/M8fgTmsIrv8zw1fsOlh6bxtIRgF2SXj/UtYaKXzv0YTF3kiBufUF4DXPQLN+2OXtiXWg8GsZKiKbHHjAi4bPA/xoF7Lrw0ykjAghQZ97hhc7wN0RB/AkZ+QvH9BYsYzM9NjJd7ttod25x31tJAckMReD X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:18.8111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad4ba053-e0e6-400c-0d07-08dcb6865d7b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB76.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6811 So that this function can be used by other cmdqs than &smmu->cmdq only. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d11362e9fc8a..e664c40b14ae 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3555,9 +3555,9 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, return 0; } -static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) +static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) { - struct arm_smmu_cmdq *cmdq = &smmu->cmdq; unsigned int nents = 1 << cmdq->q.llq.max_n_shift; atomic_set(&cmdq->owner_prod, 0); @@ -3582,7 +3582,7 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (ret) return ret; - ret = arm_smmu_cmdq_init(smmu); + ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); if (ret) return ret; From patchwork Wed Aug 7 02:11:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969765 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=AZW1ZgOQ; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3186-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwp2p7nz1ydt for ; Wed, 7 Aug 2024 12:12:26 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 8BEEB1C220E2 for ; Wed, 7 Aug 2024 02:12:24 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EDE271917D1; Wed, 7 Aug 2024 02:12:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="AZW1ZgOQ" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2046.outbound.protection.outlook.com [40.107.92.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC3C190043; Wed, 7 Aug 2024 02:12:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.46 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996743; cv=fail; b=ZjkCOj9i0dGsvUXSLrEyv+5vX0swHxEM7cKIPdGZ9eQ2vmBsDT1lgCMb6Asj6xGnQmhwQtq0U/qNyaKdG3oNz9q8kTjyodRJz7eaMknLAvU1WEOWCV59PYOx6prFIobN34Tu7ZAW8EkX2OnmaS6oiipotxl9nkZ4yeGb7K14k8c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996743; c=relaxed/simple; bh=05h5kmXHey6y+aGU2U4EsCITU6D1QD6cGbX2bcb4Ui4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nxz0b4L82Rr3XW59PUnusQX5sELaHRf9fioFT7yHp5N8/NZCGRqtUM/jIVBbEcuWLQSM4elkPVpwLGgxvKTl80yryODz7Kbg3Aygv2EsJzXJypaBl9A4eKdu5Z6b8mQmIO4yL4HRuZ8kO+oxSCFKrFEO/ceFerHbJ8GvKAeHV+w= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=AZW1ZgOQ; arc=fail smtp.client-ip=40.107.92.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=e/5O7WAmn4YDihHnd96LP9XZmN1wrpLOJEfZGSmRVazU4XFoxS0j63FRh+TWiHTb7DCADyue0VAe3S4KOj0VG2dTcKUCJbNNmCcHNKSc6OufmMER8vhLPIh00QvtaL6HsDHvvCoHPvpDziJj3M8YVr3Y26OdDgJXWkJSfMbacquOjUaGwkXWLSyVoN3womaiKpKgzipxBBzoM+pXMMA4nUs1NkZACmgNx9ciUNkqs3hVuM0erK+PVKI1pk1qn1bXcwsPVG3pqzc8Dgtu1FLsGvRZ10GQsYLRHFQo+Q1XmJruuoXKByw05b4OW2cp/CowS14GcbiUoiUHHNK/ZOV5JA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=IPDubkbMqgbcv/zjTjwGcmhEwYLX+bEDSLRIn9Ad+Dk=; b=DWyx7TFafzsyVIqRqhS3qg3b12TzW7Tv+aVijm9KQuXc0zPL9GxWDB2JNX67i5AxiVr+hACSi9cix/ZPe/isItIp02KALV+amYsVhGA5cqkCRlOixgqByAwszUJT+TNHtURox6Um+CwX0pEHtiBeHX7aShihtLnOZKHMtojV/wHc2yN82CltikZ9REYFoEgdeJ7mUjWpOboSqSf86t9od/iA61GkB5CaIaYM4HsVzEwo0xzqhG3XzPhcGAtFwRYo69S/aPNIXSdnP0OcLCKvXUqXYYqVfae/RDjdOQEHs/rmrvUAlOh6+VJOKtepKcxCnR+tUBPQZOAU+H8s+C1TdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=IPDubkbMqgbcv/zjTjwGcmhEwYLX+bEDSLRIn9Ad+Dk=; b=AZW1ZgOQB97E8rHtp/daKWS4cggiIctdjWkD3YbNOCCYJ1SX5b4McQXHqtITDecYXl+V1RqBcI3yuRki3xRW8JiHBouOMswM6Llk3AB3iP0R60xhzcvn1faxtB94Q+DsPYhqWqPTzeyVSaJMSBgJgk2Waq5pDXbbUUcEPOiZJrzKY3UxumRKcm9F14VvBybdThpmz9LskY4IrNNZXtttTmRuqXuCrpINJNT2qLW+NZ2t1dB3ZWu+8q8v8Cvi3CMW5nSA7qDo+LO5SDn9s64iB+CkncBHx6IveFF8w0oOdW7JIlarb5ViVk5SQsfCcDmB7GiEvLjIfcDAK2fryaHUpA== Received: from PH0PR07CA0019.namprd07.prod.outlook.com (2603:10b6:510:5::24) by CY8PR12MB7147.namprd12.prod.outlook.com (2603:10b6:930:5d::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.34; Wed, 7 Aug 2024 02:12:18 +0000 Received: from SN1PEPF00036F3D.namprd05.prod.outlook.com (2603:10b6:510:5:cafe::20) by PH0PR07CA0019.outlook.office365.com (2603:10b6:510:5::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.27 via Frontend Transport; Wed, 7 Aug 2024 02:12:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3D.mail.protection.outlook.com (10.167.248.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Wed, 7 Aug 2024 02:12:18 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:03 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:03 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:02 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 5/9] iommu/arm-smmu-v3: Make symbols public for CONFIG_TEGRA241_CMDQV Date: Tue, 6 Aug 2024 19:11:50 -0700 Message-ID: <1972ecc4d24189a055728609f130430b1e1cdd75.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|CY8PR12MB7147:EE_ X-MS-Office365-Filtering-Correlation-Id: e68ec2b8-d20a-4806-8042-08dcb6865d05 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: 8Hf3sQxKEgWpBZoakR9BNY2YQurhvSuDBM35UOyHrKlti3C29tAHAeIsNt3OphZTjm4ddypx3xAkVRyzQa7JlCiUMJox+j38YOQGVHVEg2kXaTSqURCQc6/ezvItNP9LADhE1ndmg0E1Vv0unS1CDu04JzZdEo4fdD0uSU7xJ9Zf49z4b6V9sOVW6rEKoXzemcyiD8o1rB5hOHD7xfoIUrxni/eutNkMLS43RJo+de/aOImORXxZaQXXpi+t8LAlauS+jvfvYjKIKr6F3mzhkH/Y63autPSFN71T/vab1L7o7aKrjHG8ocHmLAK3t3EQT85WWDDShaLA5CuM7WylPZn591GjECJRtmpVSZCvBfkEs24EjGnUxfSLUI+AtRI80NiN12S3j4/RwjjsrNeClUXaSp6MbXE6kyWsXvYpkMMjLN8bd4wNnwP/NExm+o0NG5ZKIinwwbc5okUwCRppIfKDfTbfZYo3Nt/Xy8IfAL+r8Lwe4n7ZMP5ARpU6c5fnA5wrP1f5LGZUJjyNT6Rd73uNv6pfklopDOmv9wTBf+R+jyndQz8YrkytA4d3VHJkITE7WCe2Zc7W3aUsZFVfKtBthcOzIR7d4pR9An99lIb+0wzvMT+lA+bb+jxXyU3UAgi8bhokITWOamfbMtfYsXUpN3GaaALIhM9Q4yg0Nyg8i6PC7sN2TbyDTEZImrtcm5+R/eyZgiZBC/1sAT/3Nuz7ReN3itQVzBig7aIypxToDHRpbwQk+9KL42OBz3CgkT1RQ0tK2bNcHYciLAaITAMN1xXY6JtVP5mKgZg58ZCQo9MFcHsWZuKYs4PyCZ8ZAi/bpPWObo185/YtXmMxvyyjvwF9pX4yjUBObHeBk3qr5SA5GtYWDnVeV/knZjLoEPAigo7rTH9rkBxkFAx0btYeMfL+s5ejiowhJbqFx+qzXrztm2rJACZRsBTTE2tQtqsh52snSA8SEtIDdghwj5neLJP/hUigFBK6LjlEclPX7kSzegnB6XkbNapVDVcy8uWBIGxeBtm5t0ChQUWDFgMyYwOXnyjTCYEZ4UHISVS0TdwKf8/7db74gu6FAWxYSXrkUdryk3g6CmpRJmnDd8Kocc+n/sDw/6VxKCkB8+2/bAJdiQ+FCJVqHhNljyV/yZ/6uRuOBa/ZXy8QWa8ceD9fQEoSHeF0PHNNe7WvHkuQdcQglSbk+2noA94SbpW1JSOjnUdmrUxh8+Kda016Q9kiVgU1G6DxCt+dSFxegoaWxQlDdKr4GTbU4NnPHnvVOJhNSbGRHWJ7J1QzhaWjxrgWUK6nqbAh67nhjUN+pTUJabDecaOvDdrBJDdLpVuKBNpkm2MCneRx6H5q43TvqdNGRb1hT1cs96Zt+UzWqZ4ZJA/Wq9hwY1QTybxL+GSSmNcIOs/HpHzO8xBEuF6aqLY/rpEmZWE0NGhnRBDiGHZfdNIunNWt3XrvAvh/c9hZ X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:18.0875 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e68ec2b8-d20a-4806-8042-08dcb6865d05 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7147 The symbols __arm_smmu_cmdq_skip_err(), arm_smmu_init_one_queue(), and arm_smmu_cmdq_init() need to be used by the tegra241-cmdqv compilation unit in a following patch. Remove the static and put prototypes in the header. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 ++++++++---------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 +++++++++ 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index e664c40b14ae..df1149095860 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -365,8 +365,8 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, CMDQ_SYNC_1_MSIADDR_MASK; } -static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq) +void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) { static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", @@ -3512,12 +3512,10 @@ static struct iommu_dirty_ops arm_smmu_dirty_ops = { }; /* Probing and initialisation functions */ -static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, - struct arm_smmu_queue *q, - void __iomem *page, - unsigned long prod_off, - unsigned long cons_off, - size_t dwords, const char *name) +int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, void __iomem *page, + unsigned long prod_off, unsigned long cons_off, + size_t dwords, const char *name) { size_t qsz; @@ -3555,8 +3553,8 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, return 0; } -static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq) +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) { unsigned int nents = 1 << cmdq->q.llq.max_n_shift; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6c5739f6b90f..6c5dc2f10a33 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -813,6 +813,15 @@ void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, unsigned long iova, size_t size); +void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq); +int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, + struct arm_smmu_queue *q, void __iomem *page, + unsigned long prod_off, unsigned long cons_off, + size_t dwords, const char *name); +int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master); From patchwork Wed Aug 7 02:11:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969767 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=HP1lSA8c; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3189-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwv3rwKz1ydt for ; Wed, 7 Aug 2024 12:12:31 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 319AA2815B4 for ; Wed, 7 Aug 2024 02:12:30 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C4E0D197554; Wed, 7 Aug 2024 02:12:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="HP1lSA8c" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2087.outbound.protection.outlook.com [40.107.236.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBFB8194C95; Wed, 7 Aug 2024 02:12:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.236.87 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996749; cv=fail; b=Dc55qiABl+u3OsMSXiXEU868aSH1FUl7ftY4j7wom4zgTqpU78RCZBMKK6N95+UkWLASwf+1J8tSBPxGa8aqkW5zUUWzy3CYce3ypOIH7TsY8iaBkB5zfSx9of8VDtOAKSfzp14EwQhgsqG9DL6TuOAExvf9jlbOusFxfSnKgl4= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996749; c=relaxed/simple; bh=56pj4qWImdgyu9ACzYuTpl1/p2q1AfXhbxaKbb6CRpQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LnirqR896pzUYnhiAc0cu7hwS/FSm9/+YdB10muxgnwbwzIMZebUZyguQ4YBS2veMlbC8mcAPnCaTnLZyO6Y66qCc1VJG3aZhUSU/C/rbdRQb3M0XbeFFT5PnS9qoVaoBMwsWogp6rdAbAI1XvLrYLKBDrN1nkl04k9SJYDw6pE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=HP1lSA8c; arc=fail smtp.client-ip=40.107.236.87 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=hvx2IFQUhXttH9TZarvgjQmYs1BIrgMYfaior+yMiHxNVJ1rhpWIzSGzlTX+syBNw8BlhxE0/9PD2p9sO/ZSSYc/GN9izMoxJYaLlaP0DzSOgkkV380buvhjp4GlnKYp5J3e9LNmeW84/AqHe08SS7/wu6l1lffQgdpHi8GcaZJlgJ8TpHevgCsdbPc5xCEftOMaQKWXyK6SkGAeN2J8AkNN58vFTYKvIn1wjnbHIvVOnbz+moloX9Rv7D1wJYwviFPRkQixdXC02e1OipYVLFrSSxqV6HS9RgHoDZvWu61QI7BW/4dQ5jNc0B7NVsmyTBZtmLa6hc330eUu+F0GGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=phgPaY+yO+XDIG18DAq7MBrwAMSq1PcYMMpWjeM4jiI=; b=WF8rqV5I3QHrlpCDahoJbVDQb4tDIfMONbfkWu0udizRjeDTkTZn2VYiAJKouU0MhvbuFOtBiGrGuIXK2ff7lsXZQbncRKYbc9p0t0kc8J95jKM9Tu6G/p226emd1VdMWJX36rK6H+WVmGayJhbPxpC3D38MUvBKNvEL9CHHRDaku1pQdZrhxwVT8jhet+l9sAwYzZtT0Ny/+ima06QGxH00iGqKR42J8tGtAXYCyRpGuWEDrsH91y2OxgSoYw+1QBovn3/jdJckrsC1LCSgTVRta3E7XaBe/3x20WF8265SPx2Wc2NILXklvFY8rhFRRIDuovKqbfnXevIHaSA1Tg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=phgPaY+yO+XDIG18DAq7MBrwAMSq1PcYMMpWjeM4jiI=; b=HP1lSA8c9zXX5+9+4xA9IQm6aCeQU69n64uFw9OmbuSYMBzEVxcTGcTVXb3yVXrJ0amjJ2PsDGqW7jtpMTQxx+qFF2JQkCiZudJdLHAB3wDRakvRk1t4qxblvHzz2aMpSoiB4OHMzlKa80C0lq6fVpV1ypPnt/H6xyA8hjUyTf/MN0eI7MHlXsTGyd/p8L3j87ACTpgwTd3zFFehK9iy7fKFa5vTCKWy9x8Jcc5VyoUMYHeE3xMNO30xSYuV1QjZha+uXNeBrHF/rHuBmnRxO2LRHeaB07TreB3SsPLRgPU2LMmukcsWfTZKSMrgfXe8WzkFzsKOTAvISiRE12+nmA== Received: from PH0PR07CA0005.namprd07.prod.outlook.com (2603:10b6:510:5::10) by LV3PR12MB9235.namprd12.prod.outlook.com (2603:10b6:408:1a4::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.26; Wed, 7 Aug 2024 02:12:23 +0000 Received: from SN1PEPF00036F3D.namprd05.prod.outlook.com (2603:10b6:510:5:cafe::6f) by PH0PR07CA0005.outlook.office365.com (2603:10b6:510:5::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.13 via Frontend Transport; Wed, 7 Aug 2024 02:12:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3D.mail.protection.outlook.com (10.167.248.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Wed, 7 Aug 2024 02:12:22 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:04 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:04 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:03 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 6/9] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY Date: Tue, 6 Aug 2024 19:11:51 -0700 Message-ID: <716ac3e9d2564bbc47390160286a9ce1a1d85704.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3D:EE_|LV3PR12MB9235:EE_ X-MS-Office365-Filtering-Correlation-Id: c2e8a8bb-ec72-4e7e-7617-08dcb6865f84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: JHlJxQqZbGr4uVaLs4EdWIbR9nc6/T0XQI46J9VvbumSqo98xDKCNileH/pTPay/2LP3kOeWvHlUm0Xri+o5DskWhJDTOwv0JKiNFUV7/zltHfF0a0192I8nK1XPUhpTHzYT0v/cZr1txHNuKdMrlcquJJ7/ua6jav5BKqHjI90eZafKZuLmXZb9hIbxFfSlV6rho3PyAyjYTA0wyUI6lN/qEckGhecGYhSBK2c3la9deqM1rYRZ7//fSjLokLPFbC4l9AmAhETlx18++6O4Pdss4RQtige/Hm6B16nySSxgBP7v2Eb6YBZzlTexnFDJo/lNnRMBNHgW4p3q8kfv1f5xwxiSjOWOtpEVKl3ffXwQwba+xL9+J1theTh3GFK0ozTg/VxvSkI8X5Xz5xuNo2tsf8tRxCkOo6dQw/pRqjapxgmtnFUEVPWJ/Aqqdpy1XhhLCoiLmRaFUCy1mpsyS0ktGBxtouvEcS1BB371EpqcUFj7k2+xkzr3Q3jM8v1fQwJWuoUUcsoy8sSORXcmW4CjXGWaSa8eBrLZklu1grso+RFyD6VnXkVnChSS6BGMbgBLbv9lr5oBlakbgseSvKphPoTLx3BTsbJk6oPJ8hdNHiXWw2kS/vLelV6EDyqReYC3XUc3ojOjpXoZSrldCNNsCva9KQ/n+aQzeimmsHvjyeGyHD41+7MmZDL3zby79gS8ktieFLV0Ud7kDHASgaKJ2NhlgbvNYuAOlagt5Bu0YVeE84U8400Jwb2QGo1WdGO+9CXQTl1HIKKk7HSc5u2Q/tflECj6ABQ1OpxWVY+6KjG0vmGoDTXbzMyJhAf+KsCb+nnFXRtqwrVvIyACKQnu+r36VgUUObti5qtyKiCKq5SRnuAi1vBuNJzEUpFKsALN59UYtAjrpb55lz2e0l3Ru3KcEdncLwqRmRvsi8ItGmHlf5FeYZQn/E+3pejJw5U5RUF3ouAX0jnEXgSBOadsOCeNQTGq3iP+9PccUqegJ7Oyf7FvntQT8WEstj8boTVVq64Zpt3ippNVuqslSMzUlvGdG3V6JjWpiQvsvZiBK26at41nUndMYlPunBaFtiKqlmJr8dq25uq/81BDSAibN27WtUhGC9W0CVgiyKk2192I/fp+tl5z3vdsW1+0sPFRSxUJwHckwehfXSnasnmTBbSpirkr4OzFcAnJVVOJNcYGYPH5eJehZqPy5/GMffoJMXNkQu96fn7XnSOee++aOMYKQLLQuBAOBMhr6wmgtfe8FBVq8/UvvZ04iEmW9WGvm+Jqp+QfJgRw/SNEFFaK83fOdl2UhB5h8095PL4RftzrcrTdGafROaPbjarm/snIkEpre3BDGrduCC+sa2nFAOb8lLXbCgZ/2VhmE2HFbNiF78tOodFoQWNpXjr98p5LCwBWKqh37+iEa5zDG13CFkOVUZcroiQcmIYc5YZTA6iA/Kv+1+LllNsjv+VC X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:22.2750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2e8a8bb-ec72-4e7e-7617-08dcb6865f84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9235 The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the CS field of CMD_SYNC. Add a new SMMU option to accommodate that. Suggested-by: Will Deacon Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 ++++++++++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 +++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index df1149095860..e764236a9216 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -341,6 +341,15 @@ static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) return &smmu->cmdq; } +static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq) +{ + if (cmdq == &smmu->cmdq) + return false; + + return smmu->options & ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY; +} + static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, u32 prod) { @@ -351,6 +360,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); + if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) { + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); + return; + } + if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); return; @@ -697,7 +711,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, struct arm_smmu_cmdq *cmdq, struct arm_smmu_ll_queue *llq) { - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && + !arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6c5dc2f10a33..71818f586036 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -658,10 +658,11 @@ struct arm_smmu_device { #define ARM_SMMU_FEAT_HD (1 << 22) u32 features; -#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) -#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) -#define ARM_SMMU_OPT_MSIPOLL (1 << 2) -#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_MSIPOLL (1 << 2) +#define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) +#define ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY (1 << 4) u32 options; struct arm_smmu_cmdq cmdq; From patchwork Wed Aug 7 02:11:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969768 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=WyMajqkU; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3190-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtww4r3gz1ydt for ; Wed, 7 Aug 2024 12:12:32 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 6B494283163 for ; Wed, 7 Aug 2024 02:12:31 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EDBCC197A6B; Wed, 7 Aug 2024 02:12:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="WyMajqkU" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2083.outbound.protection.outlook.com [40.107.92.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFA1CBE6F; Wed, 7 Aug 2024 02:12:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.83 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996749; cv=fail; b=b2SttnlURtkSEzURwKnTLELAYOiSj35gTTJXzTKWfgStNtKShTy9VmdvL/ssbh01nlbOb5IH5t+wcZrC5OYTMmWu9F4wG10S0u4jVnZBZWiKz29u9XHSRWrCIXYxKbRYjXR0fkY6n8b4R01TeWLu2F3vlhLdhrs1G/I4xspChlk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996749; c=relaxed/simple; bh=Ak1RQZ3NCchBLSzeVr1nTkZsjb+7NyPvHd4OnlWvgKk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RbJrFl9Dv0FGpSlvBeua7oUNAdIy5WXmQbYFj12TND0k1QbH1/ZQzcpwk41rNbdp1uUuYwkPs4TA51Hgw2ZjoHE4QsVtqpgsdIHlkQQJ6IyjJtAt2hJaAU3CDxLhy3TpehSTLcDz08hHTaGzkIG1y7eOEowrQzi51qUjLCb82/8= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=WyMajqkU; arc=fail smtp.client-ip=40.107.92.83 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EALP/PC047J/rIyn+1999fgpe24fmLCcrtIf2APSHucA6YluvLGWZh8+1ph041/X2dEsjmV6hsTtXmdjkHvMkW5MnNl1VDRMKEqUp5IsVLU6emU1B6/mxPegAZYmbxdIox9lLyeWK3psh4cQKsOiVPzsjgLW5eILEFIYd+JzsktdoqStMExrLuq+X/LTA4zHDliWlwEebMwl4ElPTqb3eF9KbikkCSv8FX+QAWZfyQkoqzTTQZQVuk6ESSnBXt/scFwOiZWZ5hTYNUHD2vaUzAmrsrI63JLhnLLewHwnVdwJxESY3GCQ1v2Au3dGwuF8bR76ZqDd3Tk2MV4Yg1A3lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PaTqD6GVnBngTTPeqFmyn3fgvm6Z8fAbprgFssFM/WQ=; b=HVF6nPlK3mS+vH2wnCyha8QAJNjMxRMeOxds95VVD92z7xGMyyt3dRHEOuvOKJJYRU6qzz9077pkbDGheSeaW490G3UcYEC283XM68gMJKB8flfQYkPL5JXSjuLNQCn/HA+7yZQac5V4Li4dp2CPBq9wE1V9qV6PXZRFXmsErzkS8cEaQqP03+jTNt96gMX6WQALEteBBd3MOtYffPN2JSr4fFv8Fweoo8+On6W+0WWTzCfbF9hGeGj2xuI9jjLofMNYWl3dlTfjDKeYfzWMkROAvjqJGi/U3L+fiGT2hkvjI0shg6ePrhLWrqbUlzecCdNdTSesR5I1yMeE69BFog== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PaTqD6GVnBngTTPeqFmyn3fgvm6Z8fAbprgFssFM/WQ=; b=WyMajqkUzGg6/47z/r72BBATb7rYKBNLPfKayZ+8axb2h0PG/v+gde3+8/RwnX0jognPzF84qQ9v7RO3yJq9iAoWYwEn6VoLg5qhuEtMjdYN2EGy3Rz+A46VEljq4lNs4P04t4bqgi11PFJ6LfusQVMQ9eVozyc07fKkLXAHdZdjhMbJzBD7dr8FOhwcyCiQffCL5YL6VQbA4R8p90ycJxAh/X8I13nJo1QDZoVP39xbrTVDWIYhkv5GfIz2Q5f92IQg9xIPVkqQxL0OEgyk4/avWQt/DXgQUgZivuhkpNJna4/bwn0CIscUSWDN9+5+xkf7MP2ZAZUUzE9gY7NSZg== Received: from SA1P222CA0172.NAMP222.PROD.OUTLOOK.COM (2603:10b6:806:3c3::28) by IA1PR12MB8407.namprd12.prod.outlook.com (2603:10b6:208:3d9::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.27; Wed, 7 Aug 2024 02:12:24 +0000 Received: from SN1PEPF00036F3C.namprd05.prod.outlook.com (2603:10b6:806:3c3:cafe::92) by SA1P222CA0172.outlook.office365.com (2603:10b6:806:3c3::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.22 via Frontend Transport; Wed, 7 Aug 2024 02:12:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3C.mail.protection.outlook.com (10.167.248.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Wed, 7 Aug 2024 02:12:23 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:05 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:05 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:04 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 7/9] iommu/arm-smmu-v3: Add struct arm_smmu_impl Date: Tue, 6 Aug 2024 19:11:52 -0700 Message-ID: <8f6fd78b4c4358e65e9d171d90aa4a3dac392f09.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3C:EE_|IA1PR12MB8407:EE_ X-MS-Office365-Filtering-Correlation-Id: d637e5a5-5df8-40ab-9db9-08dcb686605b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: kMb/ryLbNYxpT0ivf8XkwyGlWUWo1PaUNThxqutSV8Dtk+aRpYVV+x2LR0Zt2i09YCF4reKfp6eINecXVxnfyMg4Wz42hijjDqAWZjon1wVeQTs049ZykwWgOQXeyvlDgjLepn/YQNgifXBwQFj0h2AKQZPg0OLU47l8h1DB5nuAv1YXb9eehJFpgVHUN11EbzBfokSisPqMdRjQg4yGi6SGbFkxnWuGK9NwYNM3rjn4JFYi0AfMRZ08lKSLGGYcsaiaTFkVpawiFcy6JgMCEpNJ0E0S3k12VU1ttkWDdLZsJ3gVUXAFvqP5q3ydir24G12tO5BQTHCoQq9/0d+xlIfu4IwbgqG6tmEwlm3x5wnRyNd0HXwGjRbGHWafK1veqj2G6U16T7JGMkjIeoEGyTKf/IFzLSgU12rhBkUiZNfp3nOEfCcZ3BAkY60LaYyHKRuxT+poeceAm9wOI4UL+l4KwiNk7iB52kpJkZHeKmdUsXNMqCJ0VAoFQA2/RMQZiwGc4SwKRWgE98Q8pwrVfoHQxp0wzxOm6IgPg/FQ56UU0Jk/ai0BJPi7CynRlGFGl7K7czhjmvIyLSObZN71ykj+mf0owEb6qVZss19L/fR7AiY+PRQaYtBKSvfWUKYXCbc0TUYdACm16xnchJWah0edO5GAoWo5ZTMd19zDd4+FGYSx6g61+9RTXIzqzizG+rBTDAn1t6LuzkGUj4+adYbK8JPLYmxyH9af3QFAThR1xKBR1SWRDr6flXaZxDTtS44+kLxjsWp/10nj9wmKAstQbB23wp9udrROVNPdyKVZ1leDGTxuwsYtqD/r4kpZKjSSmg0l6eCbTqGH1dFiXTqpzz4BaHRQe2SF/m2rzuU6vjFQKJmFqn6UPnQy/IV+XaTQQr86o7cMhfoSksnfLQMHXOBU/iUqdNL5tFSyXko1jCR3DKsOl0ktbrFSzYcouisRzbTVIHT3pG4zjIWfDQ8Mx6PrNsIGOLvSdzY56ohHBqBqvLQYItbT1mljRnmbsHhKV4MWMPTWFzY0F20VW/cIu+G9yCsgMzwiTqGhyPRdOlxw4Z/R7SDAjShXJ3ERV0zPKFL+r2zue/qYayWNHJ53td2u3uNPYwMJ5NIpqDxpaZ8VGqqCPo/RJcjTa9tM4y3fcdgcWSKeHxQNDhPK5B4yyLJ8veQKaJtIjjUjc5WU77C2Y5q35ZsB/aHOFKF+k2omv5e/O3AMUhU/ZuyuWvf5CIdZRdVldEiE1yeHgGSJtKmaHP2rxOzFCd8VZj94Iq6jUcOhhVoB6FLp+LjFnOK/SsNMPEhA+G5RI6aisV2nuZ2877FTr8MkN6jtB7wEWBv8A4bxiGolFDqvZ/TeFkqV4srAClbEAKblPZVixinCN9e6pzxdwLTyzPhW0G15bCm5a0qUEy1RkXa2bPCg3vxjJNdr//jOg4cUB0uCgi0NE3bBvoFPhVKEruKGZh6H X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:23.6695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d637e5a5-5df8-40ab-9db9-08dcb686605b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8407 NVIDIA Tegra241 implemented SMMU in a slightly different way that supports a CMDQV extension feature as a secondary CMDQ for virtualization cases. Mimicing the arm-smmu (v2) driver, introduce a new struct arm_smmu_impl to accommodate impl routines. Suggested-by: Will Deacon Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 67 +++++++++++++++++---- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 19 ++++++ 2 files changed, 74 insertions(+), 12 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index e764236a9216..18d940c65e2c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -338,7 +338,12 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) { - return &smmu->cmdq; + struct arm_smmu_cmdq *cmdq = NULL; + + if (smmu->impl && smmu->impl->get_secondary_cmdq) + cmdq = smmu->impl->get_secondary_cmdq(smmu); + + return cmdq ?: &smmu->cmdq; } static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, @@ -4044,6 +4049,14 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + if (smmu->impl && smmu->impl->device_reset) { + ret = smmu->impl->device_reset(smmu); + if (ret) { + dev_err(smmu->dev, "failed to reset impl\n"); + return ret; + } + } + return 0; } @@ -4347,8 +4360,23 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); } -static int arm_smmu_device_acpi_probe(struct platform_device *pdev, - struct arm_smmu_device *smmu) +static struct arm_smmu_device * +arm_smmu_impl_acpi_probe(struct arm_smmu_device *smmu, + struct acpi_iort_node *node) +{ + /* + * DSDT might hold some SMMU extension, so we have no option but to go + * through the ACPI tables unconditionally. On success, this returns a + * copy of smmu struct holding an impl pointer. Otherwise, an impl may + * choose to return an ERR_PTR as an error out, or to return the pass- + * in smmu pointer as a fallback to the standard SMMU. + */ + return arm_smmu_impl_acpi_dsdt_probe(smmu, node); +} + +static struct arm_smmu_device * +arm_smmu_device_acpi_probe(struct platform_device *pdev, + struct arm_smmu_device *smmu) { struct acpi_iort_smmu_v3 *iort_smmu; struct device *dev = smmu->dev; @@ -4372,18 +4400,20 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, smmu->features |= ARM_SMMU_FEAT_HA; } - return 0; + return arm_smmu_impl_acpi_probe(smmu, node); } #else -static inline int arm_smmu_device_acpi_probe(struct platform_device *pdev, - struct arm_smmu_device *smmu) +static struct arm_smmu_device * +arm_smmu_device_acpi_probe(struct platform_device *pdev, + struct arm_smmu_device *smmu) { - return -ENODEV; + return ERR_PTR(-ENODEV); } #endif -static int arm_smmu_device_dt_probe(struct platform_device *pdev, - struct arm_smmu_device *smmu) +static struct arm_smmu_device * +arm_smmu_device_dt_probe(struct platform_device *pdev, + struct arm_smmu_device *smmu) { struct device *dev = &pdev->dev; u32 cells; @@ -4401,7 +4431,7 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |= ARM_SMMU_FEAT_COHERENCY; - return ret; + return ret ? ERR_PTR(ret) : smmu; } static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu) @@ -4453,6 +4483,14 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); } +static void arm_smmu_impl_remove(void *data) +{ + struct arm_smmu_device *smmu = data; + + if (smmu->impl && smmu->impl->device_remove) + smmu->impl->device_remove(smmu); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -4467,10 +4505,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev) smmu->dev = dev; if (dev->of_node) { - ret = arm_smmu_device_dt_probe(pdev, smmu); + smmu = arm_smmu_device_dt_probe(pdev, smmu); } else { - ret = arm_smmu_device_acpi_probe(pdev, smmu); + smmu = arm_smmu_device_acpi_probe(pdev, smmu); } + if (IS_ERR(smmu)) + return PTR_ERR(smmu); + + ret = devm_add_action_or_reset(dev, arm_smmu_impl_remove, smmu); if (ret) return ret; @@ -4560,6 +4602,7 @@ static void arm_smmu_device_remove(struct platform_device *pdev) { struct arm_smmu_device *smmu = platform_get_drvdata(pdev); + arm_smmu_impl_remove(smmu); iommu_device_unregister(&smmu->iommu); iommu_device_sysfs_remove(&smmu->iommu); arm_smmu_device_disable(smmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 71818f586036..38d4a84e2c82 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -14,6 +14,9 @@ #include #include +struct arm_smmu_device; +struct acpi_iort_node; + /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 #define IDR0_ST_LVL GENMASK(28, 27) @@ -627,9 +630,25 @@ struct arm_smmu_strtab_cfg { u32 strtab_base_cfg; }; +struct arm_smmu_impl { + int (*device_reset)(struct arm_smmu_device *smmu); + void (*device_remove)(struct arm_smmu_device *smmu); + struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu); +}; + +static inline struct arm_smmu_device * +arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu, + struct acpi_iort_node *node) +{ + return smmu; +} + /* An SMMUv3 instance */ struct arm_smmu_device { struct device *dev; + /* An SMMUv3 implementation */ + const struct arm_smmu_impl *impl; + void __iomem *base; void __iomem *page1; From patchwork Wed Aug 7 02:11:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969770 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=XRhYcVPt; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3192-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [IPv6:2604:1380:4601:e00::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtx03Ymxz1ydt for ; Wed, 7 Aug 2024 12:12:36 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 1E5781F240AC for ; Wed, 7 Aug 2024 02:12:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 673F619885B; Wed, 7 Aug 2024 02:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="XRhYcVPt" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2053.outbound.protection.outlook.com [40.107.237.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D615194149; Wed, 7 Aug 2024 02:12:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.53 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996752; cv=fail; b=EkFNIzg0+Toha+5VMPd/9udMfSCt5jZBUeC52zHnAzpZfDdTRWuI6AchwEf5v82Y/9zzecxxEgfmaERgwS3gLV2JIk5juPynmbqKmmHgYgD0Mcqfm3dj5cM1HDG8lcKKJszFOx1m1+W0gJsZSZsi8XNuUkt1saHS7GwFqDk4odM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996752; c=relaxed/simple; bh=MyvECmgCkXnkz+DsZoMPJ40zJsh1fsND8RSFUyOR8Ks=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mgZc0LPz95veNJA3e8hw6oHvaBQXeQz+lMwzKcYL5oeYY7JqNdFIReVdttIKRPYjPH8PDpIayg3bQkoECDl4hRjSBm4c5Ymrf4fLyhzNIINCQ3DUBd75W51opczx9+TgZbVQAcrfRE2zLZohjfc/xcUrzbQuS1T4XXslV9nuiYY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=XRhYcVPt; arc=fail smtp.client-ip=40.107.237.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ohj8Jif268Ue/1osFikv35+GJ76FKn3eg6KnVw6DcvAGWPCCPYEda2kHzKRvsFZuw9Z4tV9Eb3i6fwOs0hpGNQyjh7xH+iwEDgiajQX1ME0s4y5GnyZcoUZ35U2tbjP67VWAFWIETAmBkYwyR3A/7LpXSFwe8IGXQXtOlJzrDbaAilee2XbSmA5D4W4Z6y0ljBAJ3XBQa8BAFvLErr20IIgnrhXcKi+u92Li7yhX4QYIjo28z/urq2JaETBRmt65nKvWO2B/pSXi7cRRoFFJ2yIoWp4YrHGGKhOcO32s4Ha+d/WSicPJatS1CPRlgMv3OtJeaxGBvkq/cfIZgoBKGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SyRo4T+3kvIdolccNm0t0jO930+KSpfrvTclW1NZCMA=; b=HKa482BmWvYkgdkC0SwOPqkw8PzKtKvvzO0O+2xZ7M693laPLarMz40Z0oN7cv5tn7jIHwMtwMTcu6KsKOvaZoUtbWH0HcD5Xc3uqs2VRamaK38BpGB39T9uJbSzGEQSsBRFuVsyTZqw0wK/q0jQV32389IwwOMwWph6doVkeL18MaIespXolz4QtwVCKLzfxqn1vbmhoMipXICrxquSRwvpOJfFUKz2hRF2Nl0MSg+kYXK3AJ1FGba8tk1SWEe5w9Hpk7BsgzpgLWq6S6DfwV69gYFtzKvkJPLWfhLYyNe6tVABV5AyPI7LI1v9detP6gX1wol0PpL6Jxc0zJNIbA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SyRo4T+3kvIdolccNm0t0jO930+KSpfrvTclW1NZCMA=; b=XRhYcVPtrAo7TxbaWHXa8MlXHRuL1SooEGdtpthK1SX0/jRUgA6SNAuJNFB5J7TPTkJFqz0h4J6rwDXwy7b2wgqBcrz9C9pWeJZKAEd+5Jx9rzVJZ/TsjI8fcRHb5oebSj9EnOfUZgJaJ86slg0RB7+LG2S0FC2TQ9sWmVPukogDjCZb46v0ryZVUPn8SO2WcigGr2NhxxPsgdoAkhkcOsnzhXJMw5S8a+P2t83PKPkDb6RzVrjrbN2ouT5rdYS1EGYWh1i3HXjl4w/6B64ShjLw9R3jXrH1kNrTFtWsR4/Ws1y4EHRE/07ru4+l6uVuoX1QjVQNEVOSA2bOlE9wtA== Received: from MN2PR03CA0002.namprd03.prod.outlook.com (2603:10b6:208:23a::7) by IA1PR12MB6625.namprd12.prod.outlook.com (2603:10b6:208:3a3::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.21; Wed, 7 Aug 2024 02:12:25 +0000 Received: from BL6PEPF0001AB77.namprd02.prod.outlook.com (2603:10b6:208:23a:cafe::6e) by MN2PR03CA0002.outlook.office365.com (2603:10b6:208:23a::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.27 via Frontend Transport; Wed, 7 Aug 2024 02:12:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF0001AB77.mail.protection.outlook.com (10.167.242.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Wed, 7 Aug 2024 02:12:24 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:06 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:06 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:05 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 8/9] iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV Date: Tue, 6 Aug 2024 19:11:53 -0700 Message-ID: <849c17b97ae0a38db1cee949db2488e4045666df.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB77:EE_|IA1PR12MB6625:EE_ X-MS-Office365-Filtering-Correlation-Id: ff764a0b-66cd-4196-fb71-08dcb686612e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: /wALlqXEn5N8xLscl5ObUTAaVvWU7M9q+aCkv/RtPkxT+izBxOM20ATI7u9pmRqGuLRAhUiNpBxBp1GdZHnIct0BM1Tom/uvJ0oqTOp02TXl6KHwHPQxaTfaUmtkQWzWnugdx79xZviueS6TETun4Y5nRaQfrNCC5ItbIyCnPlHOt6eGvy2HHXZpfYqaxRAFnWP+uAagDtAUJg2X/Xya7iJFJcGqLqrWPIGwrYY8XTrETMe0HCn5gnugFXSfCD157qzYbG9eQZT4VkepOKCnMzlNrJEE0GVh5D7e/ia/TdqehXXd8vklFgvsICJO8p3RGut4f5jop0tLiuHgTEiX9u+dGsb1g+DEHjJUVBzHlng+IJ2xX99lIUPQKWBP4/wM+akB6L/Cfd9MTxhONVhif0JEujlfJr6V/icd9C8yzpisfapkClEbZIGpuM9zTW1RMPZvMEwzNkTqML1hWyJ/imDIYxcVn21422KU54v/+Ay114bINYdtfZ0HJhJ94/BH+lxHW2HjMcYxVyv6IHXb1IPNzYj9lf+rL6sEuKxkx0jYMAyP1XqSS/5/wbrTv8hyvMy3nF5tmbhxHq+d2UyOZ9VIrrlbP2akvyCUjXto3wrLvowyW8bsi0fBQ6+q9wM8Cr4gLKgpUKVcLKhl4FApb5lR+eNTeshNNZ3Jye782HdrF9AhxWSs+iJpUwSAUg38ZByaAjubMHM81zumuinM50zJmCmLAW8ekNTOzgHf55nAM3hULO+pYaRAP/9lv7H7xDD7Ky4tafBHH6JhvBXzh4W6Tv1wZ5VWzb18sf2TEn147Dz4ZNCjSASWWFfBtYifc6p0swMR5rOZmAdNaLfJCUfd/YJRwl8TibFb3FPclPXszSUkIsfAtatYddWBKqcUPrRsx77IwRfI9Tra8mXOq27MC0Q95f6/uU4FPPxpaNzVs6FtzjLpNF/NapOSioRs8OCpMDcqbGcjm+6xu/lc0nvvV/EH/OSJnUnkOWQdXki6uD9pL78mCOm+YWsJqRXNeIZY6pECVr1qhWGzKQG1/Lmh9aZGAGaCoaQLrR3k5bo/2h1WqieMdOWwFbtUi0MzTEUsFE0lHafdHe6/zPMfdy0i1EUjITgOwBVIuZsCg7V9z+LCIz61S0O7tz1r4Y+QbnGOZSFLFaLgxeux+aULeumRrGkA0rUIhpUlCbHQuF/7KS6hi0aERR/cdRUwkYSA8MUhz8iwWFrkR6+oB/miJxDah4w10bcHHXjhpl0cKWit+7viKZBA7APt0sKNA4480koYPlyUIKXAX5VsIq9p2YguNzata2EFypoDdYfaE20MDeZgqIWj/4SWnT3/NxPywe6pA7jV0Fy6yGg4cd6b6VPh2JtrUfbMfjBi5Sk9mmve3ONDH5+cILDirdzWep1H4T+fwX57MHoztGAu348SACVzh3yoDgeIU35lc1y3wCW3YG9lm7f8CnoBwKRUtDs8 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:24.9922 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff764a0b-66cd-4196-fb71-08dcb686612e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6625 From: Nate Watterson NVIDIA's Tegra241 Soc has a CMDQ-Virtualization (CMDQV) hardware, extending the standard ARM SMMU v3 IP to support multiple VCMDQs with virtualization capabilities. In terms of command queue, they are very like a standard SMMU CMDQ (or ECMDQs), but only support CS_NONE in the CS field of CMD_SYNC. Add a new tegra241-cmdqv driver, and insert its structure pointer into the existing arm_smmu_device, and then add related function calls in the SMMUv3 driver to interact with the CMDQV driver. In the CMDQV driver, add a minimal part for the in-kernel support: reserve VINTF0 for in-kernel use, and assign some of the VCMDQs to the VINTF0, and select one VCMDQ based on the current CPU ID to execute supported commands. This multi-queue design for in-kernel use gives some limited improvements: up to 20% reduction of invalidation time was measured by a multi-threaded DMA unmap benchmark, compared to a single queue. The other part of the CMDQV driver will be user-space support that gives a hypervisor running on the host OS to talk to the driver for virtualization use cases, allowing VMs to use VCMDQs without trappings, i.e. no VM Exits. This is designed based on IOMMUFD, and its RFC series is also under review. It will provide a guest OS a bigger improvement: 70% to 90% reductions of TLB invalidation time were measured by DMA unmap tests running in a guest, compared to nested SMMU CMDQ (with trappings). As the initial version, the CMDQV driver only supports ACPI configurations. Signed-off-by: Nate Watterson Reviewed-by: Jason Gunthorpe Co-developed-by: Nicolin Chen Signed-off-by: Nicolin Chen --- MAINTAINERS | 1 + drivers/iommu/Kconfig | 11 + drivers/iommu/arm/arm-smmu-v3/Makefile | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 9 + .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 868 ++++++++++++++++++ 5 files changed, 890 insertions(+) create mode 100644 drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c diff --git a/MAINTAINERS b/MAINTAINERS index 8766f3e5e87e..54d4df1d8311 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22472,6 +22472,7 @@ M: Thierry Reding R: Krishna Reddy L: linux-tegra@vger.kernel.org S: Supported +F: drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c F: drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c F: drivers/iommu/tegra* diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index a82f10054aec..22addaedf64d 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -424,6 +424,17 @@ config ARM_SMMU_V3_KUNIT_TEST Enable this option to unit-test arm-smmu-v3 driver functions. If unsure, say N. + +config TEGRA241_CMDQV + bool "NVIDIA Tegra241 CMDQ-V extension support for ARM SMMUv3" + depends on ACPI + help + Support for NVIDIA CMDQ-Virtualization extension for ARM SMMUv3. The + CMDQ-V extension is similar to v3.3 ECMDQ for multi command queues + support, except with virtualization capabilities. + + Say Y here if your system is NVIDIA Tegra241 (Grace) or it has the same + CMDQ-V extension. endif config S390_IOMMU diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile index 355173d1441d..dc98c88b48c8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/Makefile +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile @@ -2,5 +2,6 @@ obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o arm_smmu_v3-y := arm-smmu-v3.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o +arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o obj-$(CONFIG_ARM_SMMU_V3_KUNIT_TEST) += arm-smmu-v3-test.o diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 38d4a84e2c82..367f5e160af4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -636,10 +636,19 @@ struct arm_smmu_impl { struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu); }; +#ifdef CONFIG_TEGRA241_CMDQV +struct arm_smmu_device * +tegra241_cmdqv_acpi_dsdt_probe(struct arm_smmu_device *smmu, + struct acpi_iort_node *node); +#endif + static inline struct arm_smmu_device * arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu, struct acpi_iort_node *node) { +#ifdef CONFIG_TEGRA241_CMDQV + smmu = tegra241_cmdqv_acpi_dsdt_probe(smmu, node); +#endif return smmu; } diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c new file mode 100644 index 000000000000..c1e85c95fb99 --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -0,0 +1,868 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2021-2024 NVIDIA CORPORATION & AFFILIATES. */ + +#define dev_fmt(fmt) "tegra241_cmdqv: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm-smmu-v3.h" + +#define TEGRA241_CMDQV_HID "NVDA200C" + +/* CMDQV register page base and size defines */ +#define TEGRA241_CMDQV_CONFIG_BASE (0) +#define TEGRA241_CMDQV_CONFIG_SIZE (SZ_64K) +#define TEGRA241_VCMDQ_PAGE0_BASE (TEGRA241_CMDQV_CONFIG_BASE + SZ_64K) +#define TEGRA241_VCMDQ_PAGE1_BASE (TEGRA241_VCMDQ_PAGE0_BASE + SZ_64K) +#define TEGRA241_VINTF_PAGE_BASE (TEGRA241_VCMDQ_PAGE1_BASE + SZ_64K) + +/* CMDQV global base regs */ +#define TEGRA241_CMDQV_CONFIG 0x0000 +#define CMDQV_EN BIT(0) + +#define TEGRA241_CMDQV_PARAM 0x0004 +#define CMDQV_NUM_VINTF_LOG2 GENMASK(11, 8) +#define CMDQV_NUM_VCMDQ_LOG2 GENMASK(7, 4) + +#define TEGRA241_CMDQV_STATUS 0x0008 +#define CMDQV_ENABLED BIT(0) + +#define TEGRA241_CMDQV_VINTF_ERR_MAP 0x0014 +#define TEGRA241_CMDQV_VINTF_INT_MASK 0x001C +#define TEGRA241_CMDQV_CMDQ_ERR_MAP(m) (0x0024 + 0x4*(m)) + +#define TEGRA241_CMDQV_CMDQ_ALLOC(q) (0x0200 + 0x4*(q)) +#define CMDQV_CMDQ_ALLOC_VINTF GENMASK(20, 15) +#define CMDQV_CMDQ_ALLOC_LVCMDQ GENMASK(7, 1) +#define CMDQV_CMDQ_ALLOCATED BIT(0) + +/* VINTF base regs */ +#define TEGRA241_VINTF(v) (0x1000 + 0x100*(v)) + +#define TEGRA241_VINTF_CONFIG 0x0000 +#define VINTF_HYP_OWN BIT(17) +#define VINTF_VMID GENMASK(16, 1) +#define VINTF_EN BIT(0) + +#define TEGRA241_VINTF_STATUS 0x0004 +#define VINTF_STATUS GENMASK(3, 1) +#define VINTF_ENABLED BIT(0) + +#define TEGRA241_VINTF_LVCMDQ_ERR_MAP_64(m) \ + (0x00C0 + 0x8*(m)) +#define LVCMDQ_ERR_MAP_NUM_64 2 + +/* VCMDQ base regs */ +/* -- PAGE0 -- */ +#define TEGRA241_VCMDQ_PAGE0(q) (TEGRA241_VCMDQ_PAGE0_BASE + 0x80*(q)) + +#define TEGRA241_VCMDQ_CONS 0x00000 +#define VCMDQ_CONS_ERR GENMASK(30, 24) + +#define TEGRA241_VCMDQ_PROD 0x00004 + +#define TEGRA241_VCMDQ_CONFIG 0x00008 +#define VCMDQ_EN BIT(0) + +#define TEGRA241_VCMDQ_STATUS 0x0000C +#define VCMDQ_ENABLED BIT(0) + +#define TEGRA241_VCMDQ_GERROR 0x00010 +#define TEGRA241_VCMDQ_GERRORN 0x00014 + +/* -- PAGE1 -- */ +#define TEGRA241_VCMDQ_PAGE1(q) (TEGRA241_VCMDQ_PAGE1_BASE + 0x80*(q)) +#define VCMDQ_ADDR GENMASK(47, 5) +#define VCMDQ_LOG2SIZE GENMASK(4, 0) +#define VCMDQ_LOG2SIZE_MAX 19 + +#define TEGRA241_VCMDQ_BASE 0x00000 +#define TEGRA241_VCMDQ_CONS_INDX_BASE 0x00008 + +/* VINTF logical-VCMDQ pages */ +#define TEGRA241_VINTFi_PAGE0(i) (TEGRA241_VINTF_PAGE_BASE + SZ_128K*(i)) +#define TEGRA241_VINTFi_PAGE1(i) (TEGRA241_VINTFi_PAGE0(i) + SZ_64K) +#define TEGRA241_VINTFi_LVCMDQ_PAGE0(i, q) \ + (TEGRA241_VINTFi_PAGE0(i) + 0x80*(q)) +#define TEGRA241_VINTFi_LVCMDQ_PAGE1(i, q) \ + (TEGRA241_VINTFi_PAGE1(i) + 0x80*(q)) + +/* MMIO helpers */ +#define REG_CMDQV(_cmdqv, _regname) \ + ((_cmdqv)->base + TEGRA241_CMDQV_##_regname) +#define REG_VINTF(_vintf, _regname) \ + ((_vintf)->base + TEGRA241_VINTF_##_regname) +#define REG_VCMDQ_PAGE0(_vcmdq, _regname) \ + ((_vcmdq)->page0 + TEGRA241_VCMDQ_##_regname) +#define REG_VCMDQ_PAGE1(_vcmdq, _regname) \ + ((_vcmdq)->page1 + TEGRA241_VCMDQ_##_regname) + + +static bool disable_cmdqv; +module_param(disable_cmdqv, bool, 0444); +MODULE_PARM_DESC(disable_cmdqv, + "This allows to disable CMDQV HW and use default SMMU internal CMDQ."); + +static bool bypass_vcmdq; +module_param(bypass_vcmdq, bool, 0444); +MODULE_PARM_DESC(bypass_vcmdq, + "This allows to bypass VCMDQ for debugging use or perf comparison."); + +/** + * struct tegra241_vcmdq - Virtual Command Queue + * @idx: Global index in the CMDQV + * @lidx: Local index in the VINTF + * @enabled: Enable status + * @cmdqv: Parent CMDQV pointer + * @vintf: Parent VINTF pointer + * @cmdq: Command Queue struct + * @page0: MMIO Page0 base address + * @page1: MMIO Page1 base address + */ +struct tegra241_vcmdq { + u16 idx; + u16 lidx; + + bool enabled; + + struct tegra241_cmdqv *cmdqv; + struct tegra241_vintf *vintf; + struct arm_smmu_cmdq cmdq; + + void __iomem *page0; + void __iomem *page1; +}; + +/** + * struct tegra241_vintf - Virtual Interface + * @idx: Global index in the CMDQV + * @enabled: Enable status + * @cmdqv: Parent CMDQV pointer + * @lvcmdqs: List of logical VCMDQ pointers + * @base: MMIO base address + */ +struct tegra241_vintf { + u16 idx; + + bool enabled; + + struct tegra241_cmdqv *cmdqv; + struct tegra241_vcmdq **lvcmdqs; + + void __iomem *base; +}; + +/** + * struct tegra241_cmdqv - CMDQ-V for SMMUv3 + * @smmu: SMMUv3 device + * @base: MMIO base address + * @irq: IRQ number + * @num_vintfs: Total number of VINTFs + * @num_vcmdqs: Total number of VCMDQs + * @num_lvcmdqs_per_vintf: Number of logical VCMDQs per VINTF + * @vintf_ids: VINTF id allocator + * @vintfs: List of VINTFs + */ +struct tegra241_cmdqv { + struct arm_smmu_device smmu; + + void __iomem *base; + int irq; + + /* CMDQV Hardware Params */ + u16 num_vintfs; + u16 num_vcmdqs; + u16 num_lvcmdqs_per_vintf; + + struct ida vintf_ids; + + struct tegra241_vintf **vintfs; +}; + +/* Config and Polling Helpers */ + +static inline int tegra241_cmdqv_write_config(struct tegra241_cmdqv *cmdqv, + void __iomem *addr_config, + void __iomem *addr_status, + u32 regval, const char *header, + bool *out_enabled) +{ + bool en = regval & BIT(0); + int ret; + + writel(regval, addr_config); + ret = readl_poll_timeout(addr_status, regval, + en ? regval & BIT(0) : !(regval & BIT(0)), + 1, ARM_SMMU_POLL_TIMEOUT_US); + if (ret) + dev_err(cmdqv->smmu.dev, "%sfailed to %sable, STATUS=0x%08X\n", + header, en ? "en" : "dis", regval); + if (out_enabled) + WRITE_ONCE(*out_enabled, regval & BIT(0)); + return ret; +} + +static inline int cmdqv_write_config(struct tegra241_cmdqv *cmdqv, u32 regval) +{ + return tegra241_cmdqv_write_config(cmdqv, + REG_CMDQV(cmdqv, CONFIG), + REG_CMDQV(cmdqv, STATUS), + regval, "CMDQV: ", NULL); +} + +static inline int vintf_write_config(struct tegra241_vintf *vintf, u32 regval) +{ + char header[16]; + + snprintf(header, 16, "VINTF%u: ", vintf->idx); + return tegra241_cmdqv_write_config(vintf->cmdqv, + REG_VINTF(vintf, CONFIG), + REG_VINTF(vintf, STATUS), + regval, header, &vintf->enabled); +} + +static inline char *lvcmdq_error_header(struct tegra241_vcmdq *vcmdq, + char *header, int hlen) +{ + WARN_ON(hlen < 32); + if (WARN_ON(!vcmdq->vintf)) + return ""; + snprintf(header, hlen, "VINTF%u: VCMDQ%u/LVCMDQ%u: ", + vcmdq->vintf->idx, vcmdq->idx, vcmdq->lidx); + return header; +} + +static inline int vcmdq_write_config(struct tegra241_vcmdq *vcmdq, u32 regval) +{ + char header[32], *h = lvcmdq_error_header(vcmdq, header, 32); + + return tegra241_cmdqv_write_config(vcmdq->cmdqv, + REG_VCMDQ_PAGE0(vcmdq, CONFIG), + REG_VCMDQ_PAGE0(vcmdq, STATUS), + regval, h, &vcmdq->enabled); +} + +/* ISR Functions */ + +static void tegra241_vintf0_handle_error(struct tegra241_vintf *vintf) +{ + int i; + + for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) { + u64 map = readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + + while (map) { + unsigned long lidx = __ffs64(map) - 1; + struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx]; + u32 gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)); + + __arm_smmu_cmdq_skip_err(&vintf->cmdqv->smmu, &vcmdq->cmdq); + writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN)); + map &= ~BIT_ULL(lidx); + } + } +} + +static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) +{ + struct tegra241_cmdqv *cmdqv = (struct tegra241_cmdqv *)devid; + void __iomem *reg_vintf_map = REG_CMDQV(cmdqv, VINTF_ERR_MAP); + char err_str[256]; + u64 vintf_map; + + /* Use readl_relaxed() as register addresses are not 64-bit aligned */ + vintf_map = (u64)readl_relaxed(reg_vintf_map + 0x4) << 32 | + (u64)readl_relaxed(reg_vintf_map); + + snprintf(err_str, sizeof(err_str), + "vintf_map: %016llx, vcmdq_map %08x:%08x:%08x:%08x", vintf_map, + readl_relaxed(REG_CMDQV(cmdqv, CMDQ_ERR_MAP(3))), + readl_relaxed(REG_CMDQV(cmdqv, CMDQ_ERR_MAP(2))), + readl_relaxed(REG_CMDQV(cmdqv, CMDQ_ERR_MAP(1))), + readl_relaxed(REG_CMDQV(cmdqv, CMDQ_ERR_MAP(0)))); + + dev_warn(cmdqv->smmu.dev, "unexpected error reported. %s\n", err_str); + + /* Handle VINTF0 and its LVCMDQs */ + if (vintf_map & BIT_ULL(0)) { + tegra241_vintf0_handle_error(cmdqv->vintfs[0]); + vintf_map &= ~BIT_ULL(0); + } + + return IRQ_HANDLED; +} + +/* Command Queue Function */ + +static struct arm_smmu_cmdq * +tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) +{ + struct tegra241_cmdqv *cmdqv = + container_of(smmu, struct tegra241_cmdqv, smmu); + struct tegra241_vintf *vintf = cmdqv->vintfs[0]; + struct tegra241_vcmdq *vcmdq; + u16 lidx; + + if (READ_ONCE(bypass_vcmdq)) + return NULL; + + /* Use SMMU CMDQ if VINTF0 is uninitialized */ + if (!READ_ONCE(vintf->enabled)) + return NULL; + + /* + * Select a LVCMDQ to use. Here we use a temporal solution to + * balance out traffic on cmdq issuing: each cmdq has its own + * lock, if all cpus issue cmdlist using the same cmdq, only + * one CPU at a time can enter the process, while the others + * will be spinning at the same lock. + */ + lidx = smp_processor_id() % cmdqv->num_lvcmdqs_per_vintf; + vcmdq = vintf->lvcmdqs[lidx]; + if (!vcmdq || !READ_ONCE(vcmdq->enabled)) + return NULL; + return &vcmdq->cmdq; +} + +/* HW Reset Functions */ + +static void tegra241_vcmdq_hw_deinit(struct tegra241_vcmdq *vcmdq) +{ + char header[32], *h = lvcmdq_error_header(vcmdq, header, 32); + u32 gerrorn, gerror; + + if (vcmdq_write_config(vcmdq, 0)) { + dev_err(vcmdq->cmdqv->smmu.dev, + "%sGERRORN=0x%X, GERROR=0x%X, CONS=0x%X\n", h, + readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)), + readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)), + readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, CONS))); + } + writel_relaxed(0, REG_VCMDQ_PAGE0(vcmdq, PROD)); + writel_relaxed(0, REG_VCMDQ_PAGE0(vcmdq, CONS)); + writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, BASE)); + writeq_relaxed(0, REG_VCMDQ_PAGE1(vcmdq, CONS_INDX_BASE)); + + gerrorn = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)); + gerror = readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)); + if (gerror != gerrorn) { + dev_warn(vcmdq->cmdqv->smmu.dev, + "%suncleared error detected, resetting\n", h); + writel(gerror, REG_VCMDQ_PAGE0(vcmdq, GERRORN)); + } + + dev_dbg(vcmdq->cmdqv->smmu.dev, "%sdeinited\n", h); +} + +static int tegra241_vcmdq_hw_init(struct tegra241_vcmdq *vcmdq) +{ + char header[32], *h = lvcmdq_error_header(vcmdq, header, 32); + int ret; + + /* Reset VCMDQ */ + tegra241_vcmdq_hw_deinit(vcmdq); + + /* Configure and enable VCMDQ */ + writeq_relaxed(vcmdq->cmdq.q.q_base, REG_VCMDQ_PAGE1(vcmdq, BASE)); + + ret = vcmdq_write_config(vcmdq, VCMDQ_EN); + if (ret) { + dev_err(vcmdq->cmdqv->smmu.dev, + "%sGERRORN=0x%X, GERROR=0x%X, CONS=0x%X\n", h, + readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERRORN)), + readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, GERROR)), + readl_relaxed(REG_VCMDQ_PAGE0(vcmdq, CONS))); + return ret; + } + + dev_dbg(vcmdq->cmdqv->smmu.dev, "%sinited\n", h); + return 0; +} + +static void tegra241_vintf_hw_deinit(struct tegra241_vintf *vintf) +{ + u16 lidx; + + for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) + tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + vintf_write_config(vintf, 0); +} + +static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) +{ + u32 regval; + u16 lidx; + int ret; + + /* Reset VINTF */ + tegra241_vintf_hw_deinit(vintf); + + /* Configure and enable VINTF */ + regval = FIELD_PREP(VINTF_HYP_OWN, hyp_own); + writel(regval, REG_VINTF(vintf, CONFIG)); + + ret = vintf_write_config(vintf, regval | VINTF_EN); + if (ret) + return ret; + + for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { + if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) { + ret = tegra241_vcmdq_hw_init(vintf->lvcmdqs[lidx]); + if (ret) { + tegra241_vintf_hw_deinit(vintf); + return ret; + } + } + } + + return 0; +} + +static int tegra241_cmdqv_hw_reset(struct arm_smmu_device *smmu) +{ + struct tegra241_cmdqv *cmdqv = + container_of(smmu, struct tegra241_cmdqv, smmu); + u16 qidx, lidx, idx; + u32 regval; + int ret; + + /* Reset CMDQV */ + regval = readl_relaxed(REG_CMDQV(cmdqv, CONFIG)); + ret = cmdqv_write_config(cmdqv, regval & ~CMDQV_EN); + if (ret) + return ret; + ret = cmdqv_write_config(cmdqv, regval | CMDQV_EN); + if (ret) + return ret; + + /* Assign preallocated global VCMDQs to each VINTF as LVCMDQs */ + for (idx = 0, qidx = 0; idx < cmdqv->num_vintfs; idx++) { + for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { + regval = FIELD_PREP(CMDQV_CMDQ_ALLOC_VINTF, idx); + regval |= FIELD_PREP(CMDQV_CMDQ_ALLOC_LVCMDQ, lidx); + regval |= CMDQV_CMDQ_ALLOCATED; + writel_relaxed(regval, + REG_CMDQV(cmdqv, CMDQ_ALLOC(qidx++))); + } + } + + return tegra241_vintf_hw_init(cmdqv->vintfs[0], true); +} + +/* VCMDQ Resource Helpers */ + +static void tegra241_vcmdq_free_smmu_cmdq(struct tegra241_vcmdq *vcmdq) +{ + struct arm_smmu_queue *q = &vcmdq->cmdq.q; + size_t nents = 1 << q->llq.max_n_shift; + size_t qsz = nents << CMDQ_ENT_SZ_SHIFT; + + if (!q->base) + return; + dmam_free_coherent(vcmdq->cmdqv->smmu.dev, qsz, q->base, q->base_dma); +} + +static int tegra241_vcmdq_alloc_smmu_cmdq(struct tegra241_vcmdq *vcmdq) +{ + struct arm_smmu_device *smmu = &vcmdq->cmdqv->smmu; + struct arm_smmu_cmdq *cmdq = &vcmdq->cmdq; + struct arm_smmu_queue *q = &cmdq->q; + char name[16]; + int ret; + + snprintf(name, 16, "vcmdq%u", vcmdq->idx); + + q->llq.max_n_shift = VCMDQ_LOG2SIZE_MAX; + + /* Use the common helper to init the VCMDQ, and then... */ + ret = arm_smmu_init_one_queue(smmu, q, vcmdq->page0, + TEGRA241_VCMDQ_PROD, TEGRA241_VCMDQ_CONS, + CMDQ_ENT_DWORDS, name); + if (ret) + return ret; + + /* ...override q_base to write VCMDQ_BASE registers */ + q->q_base = q->base_dma & VCMDQ_ADDR; + q->q_base |= FIELD_PREP(VCMDQ_LOG2SIZE, q->llq.max_n_shift); + + return arm_smmu_cmdq_init(smmu, cmdq); +} + +/* VINTF Logical VCMDQ Resource Helpers */ + +static void tegra241_vintf_deinit_lvcmdq(struct tegra241_vintf *vintf, u16 lidx) +{ + vintf->lvcmdqs[lidx] = NULL; +} + +static int tegra241_vintf_init_lvcmdq(struct tegra241_vintf *vintf, u16 lidx, + struct tegra241_vcmdq *vcmdq) +{ + struct tegra241_cmdqv *cmdqv = vintf->cmdqv; + u16 idx = vintf->idx; + + vcmdq->idx = idx * cmdqv->num_lvcmdqs_per_vintf + lidx; + vcmdq->lidx = lidx; + vcmdq->cmdqv = cmdqv; + vcmdq->vintf = vintf; + vcmdq->page0 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE0(idx, lidx); + vcmdq->page1 = cmdqv->base + TEGRA241_VINTFi_LVCMDQ_PAGE1(idx, lidx); + + vintf->lvcmdqs[lidx] = vcmdq; + return 0; +} + +static void tegra241_vintf_free_lvcmdq(struct tegra241_vintf *vintf, u16 lidx) +{ + struct tegra241_vcmdq *vcmdq = vintf->lvcmdqs[lidx]; + char header[32]; + + tegra241_vcmdq_free_smmu_cmdq(vcmdq); + tegra241_vintf_deinit_lvcmdq(vintf, lidx); + + dev_dbg(vintf->cmdqv->smmu.dev, + "%sdeallocated\n", lvcmdq_error_header(vcmdq, header, 32)); + kfree(vcmdq); +} + +static struct tegra241_vcmdq * +tegra241_vintf_alloc_lvcmdq(struct tegra241_vintf *vintf, u16 lidx) +{ + struct tegra241_cmdqv *cmdqv = vintf->cmdqv; + struct tegra241_vcmdq *vcmdq; + char header[32]; + int ret; + + vcmdq = kzalloc(sizeof(*vcmdq), GFP_KERNEL); + if (!vcmdq) + return ERR_PTR(-ENOMEM); + + ret = tegra241_vintf_init_lvcmdq(vintf, lidx, vcmdq); + if (ret) + goto free_vcmdq; + + /* Build an arm_smmu_cmdq for each LVCMDQ */ + ret = tegra241_vcmdq_alloc_smmu_cmdq(vcmdq); + if (ret) + goto deinit_lvcmdq; + + dev_dbg(cmdqv->smmu.dev, + "%sallocated\n", lvcmdq_error_header(vcmdq, header, 32)); + return vcmdq; + +deinit_lvcmdq: + tegra241_vintf_deinit_lvcmdq(vintf, lidx); +free_vcmdq: + kfree(vcmdq); + return ERR_PTR(ret); +} + +/* VINTF Resource Helpers */ + +static void tegra241_cmdqv_deinit_vintf(struct tegra241_cmdqv *cmdqv, u16 idx) +{ + kfree(cmdqv->vintfs[idx]->lvcmdqs); + ida_free(&cmdqv->vintf_ids, idx); + cmdqv->vintfs[idx] = NULL; +} + +static int tegra241_cmdqv_init_vintf(struct tegra241_cmdqv *cmdqv, u16 max_idx, + struct tegra241_vintf *vintf) +{ + + u16 idx; + int ret; + + ret = ida_alloc_max(&cmdqv->vintf_ids, max_idx, GFP_KERNEL); + if (ret < 0) + return ret; + idx = ret; + + vintf->idx = idx; + vintf->cmdqv = cmdqv; + vintf->base = cmdqv->base + TEGRA241_VINTF(idx); + + vintf->lvcmdqs = kcalloc(cmdqv->num_lvcmdqs_per_vintf, + sizeof(*vintf->lvcmdqs), GFP_KERNEL); + if (!vintf->lvcmdqs) { + ida_free(&cmdqv->vintf_ids, idx); + return -ENOMEM; + } + + cmdqv->vintfs[idx] = vintf; + return ret; +} + +/* Remove Helpers */ + +static void tegra241_vintf_remove_lvcmdq(struct tegra241_vintf *vintf, u16 lidx) +{ + tegra241_vcmdq_hw_deinit(vintf->lvcmdqs[lidx]); + tegra241_vintf_free_lvcmdq(vintf, lidx); +} + +static void tegra241_cmdqv_remove_vintf(struct tegra241_cmdqv *cmdqv, u16 idx) +{ + struct tegra241_vintf *vintf = cmdqv->vintfs[idx]; + u16 lidx; + + /* Remove LVCMDQ resources */ + for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) + if (vintf->lvcmdqs[lidx]) + tegra241_vintf_remove_lvcmdq(vintf, lidx); + + /* Remove VINTF resources */ + tegra241_vintf_hw_deinit(vintf); + + dev_dbg(cmdqv->smmu.dev, "VINTF%u: deallocated\n", vintf->idx); + tegra241_cmdqv_deinit_vintf(cmdqv, idx); + kfree(vintf); +} + +static void tegra241_cmdqv_remove(struct arm_smmu_device *smmu) +{ + struct tegra241_cmdqv *cmdqv = + container_of(smmu, struct tegra241_cmdqv, smmu); + u16 idx; + + /* Remove VINTF resources */ + for (idx = 0; idx < cmdqv->num_vintfs; idx++) { + if (cmdqv->vintfs[idx]) { + /* Only vintf0 should remain at this stage */ + WARN_ON(idx > 0); + tegra241_cmdqv_remove_vintf(cmdqv, idx); + } + } + + /* Remove cmdqv resources */ + ida_destroy(&cmdqv->vintf_ids); + + if (cmdqv->irq > 0) + free_irq(cmdqv->irq, cmdqv); + iounmap(cmdqv->base); + kfree(cmdqv->vintfs); +} + +static struct arm_smmu_impl tegra241_cmdqv_impl = { + .get_secondary_cmdq = tegra241_cmdqv_get_cmdq, + .device_reset = tegra241_cmdqv_hw_reset, + .device_remove = tegra241_cmdqv_remove, +}; + +/* Probe Functions */ + +static int tegra241_cmdqv_acpi_is_memory(struct acpi_resource *res, void *data) +{ + struct resource_win win; + + return !acpi_dev_resource_address_space(res, &win); +} + +static int tegra241_cmdqv_acpi_get_irqs(struct acpi_resource *ares, void *data) +{ + struct resource r; + int *irq = data; + + if (*irq <= 0 && acpi_dev_resource_interrupt(ares, 0, &r)) + *irq = r.start; + return 1; /* No need to add resource to the list */ +} + +static struct resource * +tegra241_cmdqv_find_acpi_resource(struct arm_smmu_device *smmu, + struct acpi_iort_node *node, int *irq) +{ + struct device *dev = smmu->dev; + struct list_head resource_list; + struct resource_entry *rentry; + struct resource *res = NULL; + struct acpi_device *adev; + const char *match_uid; + int ret; + + if (acpi_disabled) + return NULL; + + /* Look for a device in the DSDT whose _UID matches the SMMU node ID */ + match_uid = kasprintf(GFP_KERNEL, "%u", node->identifier); + adev = acpi_dev_get_first_match_dev(TEGRA241_CMDQV_HID, match_uid, -1); + kfree(match_uid); + + if (!adev) + return NULL; + + dev_info(dev, "found companion CMDQV device, %s\n", + dev_name(&adev->dev)); + + INIT_LIST_HEAD(&resource_list); + ret = acpi_dev_get_resources(adev, &resource_list, + tegra241_cmdqv_acpi_is_memory, NULL); + if (ret < 0) { + dev_err(dev, "failed to get memory resource: %d\n", ret); + goto put_dev; + } + + rentry = list_first_entry_or_null(&resource_list, + struct resource_entry, node); + if (!rentry) { + dev_err(dev, "failed to get memory resource entry\n"); + goto free_list; + } + + /* Caller must free the res */ + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + goto free_list; + + *res = *rentry->res; + + acpi_dev_free_resource_list(&resource_list); + + INIT_LIST_HEAD(&resource_list); + + if (irq) + ret = acpi_dev_get_resources(adev, &resource_list, + tegra241_cmdqv_acpi_get_irqs, irq); + if (ret < 0 || !irq || *irq <= 0) + dev_warn(dev, "no interrupt. errors will not be reported\n"); + +free_list: + acpi_dev_free_resource_list(&resource_list); +put_dev: + put_device(&adev->dev); + + return res; +} + +struct dentry *cmdqv_debugfs_dir; + +static struct arm_smmu_device * +tegra241_cmdqv_probe(struct arm_smmu_device *smmu, + struct resource *res, int irq) +{ + struct tegra241_cmdqv *cmdqv = NULL; + struct tegra241_vintf *vintf; + void __iomem *base; + u32 regval; + int lidx; + int ret; + + base = ioremap(res->start, resource_size(res)); + if (IS_ERR(base)) { + dev_err(smmu->dev, "failed to ioremap: %ld\n", PTR_ERR(base)); + goto iounmap; + } + + regval = readl(base + TEGRA241_CMDQV_CONFIG); + if (disable_cmdqv) { + dev_info(smmu->dev, "Detected disable_cmdqv=true\n"); + writel(regval & ~CMDQV_EN, base + TEGRA241_CMDQV_CONFIG); + goto iounmap; + } + + cmdqv = devm_krealloc(smmu->dev, smmu, sizeof(*cmdqv), GFP_KERNEL); + if (!cmdqv) + goto iounmap; + smmu = &cmdqv->smmu; + + cmdqv->irq = irq; + cmdqv->base = base; + + if (cmdqv->irq > 0) { + ret = request_irq(irq, tegra241_cmdqv_isr, 0, + "tegra241-cmdqv", cmdqv); + if (ret) { + dev_err(smmu->dev, "failed to request irq (%d): %d\n", + cmdqv->irq, ret); + goto iounmap; + } + } + + regval = readl_relaxed(REG_CMDQV(cmdqv, PARAM)); + cmdqv->num_vintfs = 1 << FIELD_GET(CMDQV_NUM_VINTF_LOG2, regval); + cmdqv->num_vcmdqs = 1 << FIELD_GET(CMDQV_NUM_VCMDQ_LOG2, regval); + cmdqv->num_lvcmdqs_per_vintf = cmdqv->num_vcmdqs / cmdqv->num_vintfs; + + cmdqv->vintfs = kcalloc(cmdqv->num_vintfs, + sizeof(*cmdqv->vintfs), GFP_KERNEL); + if (!cmdqv->vintfs) + goto free_irq; + + ida_init(&cmdqv->vintf_ids); + + vintf = kzalloc(sizeof(*vintf), GFP_KERNEL); + if (!vintf) + goto destroy_ids; + + /* Init VINTF0 for in-kernel use */ + ret = tegra241_cmdqv_init_vintf(cmdqv, 0, vintf); + if (ret) { + dev_err(smmu->dev, "failed to init vintf0: %d\n", ret); + goto free_vintf; + } + + /* Preallocate logical VCMDQs to VINTF0 */ + for (lidx = 0; lidx < cmdqv->num_lvcmdqs_per_vintf; lidx++) { + struct tegra241_vcmdq *vcmdq; + + vcmdq = tegra241_vintf_alloc_lvcmdq(vintf, lidx); + if (IS_ERR(vcmdq)) + goto free_lvcmdq; + } + +#ifdef CONFIG_IOMMU_DEBUGFS + if (!cmdqv_debugfs_dir) { + cmdqv_debugfs_dir = + debugfs_create_dir("tegra241_cmdqv", iommu_debugfs_dir); + debugfs_create_bool("bypass_vcmdq", 0644, + cmdqv_debugfs_dir, &bypass_vcmdq); + } +#endif + + cmdqv->smmu.impl = &tegra241_cmdqv_impl; + cmdqv->smmu.options |= ARM_SMMU_OPT_SECONDARY_CMDQ_CS_NONE_ONLY; + + return &cmdqv->smmu; + +free_lvcmdq: + for (lidx--; lidx >= 0; lidx--) + tegra241_vintf_free_lvcmdq(vintf, lidx); + tegra241_cmdqv_deinit_vintf(cmdqv, vintf->idx); +free_vintf: + kfree(vintf); +destroy_ids: + ida_destroy(&cmdqv->vintf_ids); + kfree(cmdqv->vintfs); +free_irq: + if (cmdqv->irq > 0) + free_irq(cmdqv->irq, cmdqv); +iounmap: + iounmap(base); + dev_info(smmu->dev, "Falling back to standard SMMU CMDQ\n"); + return smmu; +} + +struct arm_smmu_device * +tegra241_cmdqv_acpi_dsdt_probe(struct arm_smmu_device *smmu, + struct acpi_iort_node *node) +{ + struct resource *res; + int irq; + + /* Keep the pointer smmu intact if !res */ + res = tegra241_cmdqv_find_acpi_resource(smmu, node, &irq); + if (!res) + return smmu; + + smmu = tegra241_cmdqv_probe(smmu, res, irq); + kfree(res); + return smmu; +} From patchwork Wed Aug 7 02:11:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 1969769 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256 header.s=selector2 header.b=SBCEpVFF; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=linux-tegra+bounces-3191-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Wdtwy3fYhz1ydt for ; Wed, 7 Aug 2024 12:12:34 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id B60DA1C2209A for ; Wed, 7 Aug 2024 02:12:32 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A36D818FDCC; Wed, 7 Aug 2024 02:12:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="SBCEpVFF" X-Original-To: linux-tegra@vger.kernel.org Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2059.outbound.protection.outlook.com [40.107.92.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B5E8197512; Wed, 7 Aug 2024 02:12:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996751; cv=fail; b=VKKPMoJIUJWH+Xa0G+89lT0W0NR7X9BUyTRtmOhMJ2f2tPfdXYMEIgwDFUusihcuup77VFbmJcUimO6yV0VrJis6q008A8MIEluvWG0lziGsTAJymFIbWSQLeR40WmXaG7WW4M+mzo+z9KgHoIo0eEMppruoeN0zt+Xf7vGKPAE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722996751; c=relaxed/simple; bh=IZ5JTqVCgypSWHwf4Zzu1bGCNuC+QEpQ6F6AMwpGqT4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BlwwPQmeIuu4R1KEyJwGdY8rfoi4Dx14oPVacYsrB2N2WllK0/WssX5jXGDGpFGM5C66YeTC8aAGGFNSQxsL09CUkS2fek3pVH0gghHSy4ihCXl2Ylez1S4tCxyWQtbi4GQOqcW5OisMF4DS03epGr6YRF27duoegq6qgqDj/sI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=SBCEpVFF; arc=fail smtp.client-ip=40.107.92.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=L98TkQrQ3uQlKXbpgAsmItEgXym02C6L7kT8qnKd46Z1K7dhyopgRS6W3diReK4Kr98LSVaD2fzYA5Vijt6/kIeQFGsPmvC5x/Pu/aQcqV+6en3c2kYcpHfi1gMyTAt8wp52LN8Fy6ZPsFw5XFpCHvx2SCqA7n1KCCCrRYGl1VlE9A6IE/K8behEBeqC7nfV61LnxIdO0yG9bYZ17dyZ27vq5M9saF7bTBmUy6jc5B2DQOHHaas/L0WM0mR/1f/P5wOk9Ovjfu6V3L0yG8wpS4wqfSSHUTPDuU2MsNhtBlpF/yDm28XMPDfE88RDnFYIkH92qjuvehjVFlKJknAYYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zrpYVZQgaJzBIbY7T5XauWjoxxatf5Mp4XTTwRlRP/s=; b=ZG89IacdP7QN5YJfxtuxPpcd9AV4FbSW2dQpVWxut46qmmsQKTc1l8wqN9oHKP8juUbWRbsK1G6dJtDRMYG4YiOTvV7WfOJW7bNZ/Jok5dFoJfMg8hNk3CZqum77oKSupFX2zX1wcpdSReaJf4BY8B8/xtjWZdmyqEfiAqtAtIk2sPpNkDViMJ0y3YD9XBObznFtagfb1ztsY7sZSCQ07rM4MaUGuooyYTCL6oDpWPcrNNWkKXHgBo26lp0mEpIpaZ3Frmx3H9HjYMxNIhEZ7wchTRr+nwSLXSb0dMtxhHsUl2r++/tdXKsVHvMF2+gg7iL7PAjthR7yYTPGvIB23g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zrpYVZQgaJzBIbY7T5XauWjoxxatf5Mp4XTTwRlRP/s=; b=SBCEpVFFnLObtqPuROb78rCgTgJJsGKjomB9cz3ATyK44BhNwtsViaPPvd5Y3/1Wn2PqwyZf7jU0EP5Mcvg64wzzHJ8quNnK7vDxj5gaK9OdCVNccQCVyn2cv9yuF0HYtb2j8p+3eBxKC64XPRnCzAI8QaOe+DyCNfCHnrJ/kQXK+I1i1lnDdcJOjDJhisdhYPR0S/DyufzzPHlcCqR0kVAvm2vT/CeS81GABHu1TXrIgymGNf6bfeEohTUYH4EJOl/1PTh1EoVjDfHWDqKSL97BCwFlIodYlQyd7xUzYCcKRIO42wGn9UE8dmjgN1HuNCgrGKZtH0z+r6hv2irdhQ== Received: from PH7PR10CA0016.namprd10.prod.outlook.com (2603:10b6:510:23d::8) by IA0PR12MB8862.namprd12.prod.outlook.com (2603:10b6:208:48e::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7807.25; Wed, 7 Aug 2024 02:12:25 +0000 Received: from SN1PEPF00036F3F.namprd05.prod.outlook.com (2603:10b6:510:23d:cafe::76) by PH7PR10CA0016.outlook.office365.com (2603:10b6:510:23d::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.13 via Frontend Transport; Wed, 7 Aug 2024 02:12:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00036F3F.mail.protection.outlook.com (10.167.248.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Wed, 7 Aug 2024 02:12:25 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:08 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 6 Aug 2024 19:12:07 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Tue, 6 Aug 2024 19:12:06 -0700 From: Nicolin Chen To: CC: , , , , , , , , , Subject: [PATCH v11 9/9] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Date: Tue, 6 Aug 2024 19:11:54 -0700 Message-ID: <153fb887cf4bf6318c6f313a4be9b40a25a24e7d.1722993435.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3F:EE_|IA0PR12MB8862:EE_ X-MS-Office365-Filtering-Correlation-Id: 77224e20-6fc4-4563-779f-08dcb6866141 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: xfqEr86p82Pyei4DOExo1qLb7XeSnUEK58nZUiZAUiuehJDbAckd8nlBG03uI3HIUEvja0xxrEDkI8ot7mChpXqn4+unlrmZ54DHq78NwjsLSi001n9WVF0nwG/xrDYyAqkC68PVgVT5HlIh336hFqlvzi8M5iFgzbM4mFvtXMUciKoyKZRjqzIYZ4aXDXEVKLBK5RMi5Wi2bz3y4rrgqom2CmjjBt5Hxc6aD4AKgdGlxi5znSTIZhPvune4+8Hwxgm69/yXZQSGYCGIZzWi1M6nYzY5+KtJjSYndCDXQQ/fIb+GI1doyEUIh9xwdqIhB3MX39uR2gNfiIA73U9efXTz4TtSqJenEev/JjcjtRFsyG80Kif0TPixNkSY7ZOejbBnqZBHyDQzMhTXjxYFGAntihHd/MDdToU0s0xD95gsyOlcGd7pkNX0LBfGR8gVdBByLifqqxX9rEhs4eF7+TXTL8b7mpA4/ylOmNyDB7pGjFtU7s/wDTlVoQJPIdtUH8EAfn69C/RhbZvxVPE9gcvsR5g5DavZoyqZtDm4qZwJqvDpbTicwqVZK4xvnMXD5Sh4OjEtSIX5vitNhsSvVTjMuVAP5jM0akHRzVJr5kTTjWlB7cpoKU/Y0l1yQsuGz6f8egrslJzkV2b/i3AhUdMu8S+fftpIyR+W971beGMmoXn3krju9AIwQO2k051su3Q9wvvvfBly6/Kho28Rl9Hu8d24FrAvHQ29MmVQ9NE5iF2lguSqWDY2RXug0ocSOzQavON3/aMUW7rmWpq9WGIdC1cF8LOEXRtq9W8j3uyzSl5EIyiIvQmLHr4LElAn+LiICOjedIm/65JvxTGADz3t/omo2D3lp/DiF2Ht/DGktMHm/t15LmPv4J1ulXyipQTB9RpCIuYE0GJUWHuyokA080Tczujp7P2OWqGZIr5kGYIx+Kp7hmZ0mTM06r8SYWu11g158d3+4rvqupHuyesun7zjV/B0+jCflXHsZQb0dsG+b8pRAa2THQ389HqiiZyhQVAve/Xi5iD2H+9MTyCA1EH5xjlE0BMFEXfNC5JISA63loxTvALoXJgpPcwXddIB2WRZQz7ZZuE6U0WrrneXcETXqx/uKr1LioHwy4GsLV77DGQ+q5yyxUY1/VClVec3vpN0JR93T7efrn8vGC9pvEI50B1qY06+LPpnDH92g6P3QlPB3QMU9KnYzErN7BTU6AeeSw1T1BAn2t2zGhGg+ar3sTSTj/caoAmZ3TXCqTbvT3j/ivLdzeh/hRqCZPnHjyo9NrwmucpVxAUbwSC+Eg2krpuQAweGIKKveLpiwIRYCQMaPLFqo7okQZZyCAefAr8o46ldEX0DWGvFD8+wRTbVkp6UeUYFSAmIWlj26FgiTSt+KG9iZsqxPj9xd1hf1MIkCjHoYBeQWGueTDlRAnfJzg1JYZdF1xEBgwU2iMYWSjLwN9Auzn2gjDx/ X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2024 02:12:25.1914 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77224e20-6fc4-4563-779f-08dcb6866141 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8862 When VCMDQs are assigned to a VINTF owned by a guest (HYP_OWN bit unset), only TLB and ATC invalidation commands are supported by the VCMDQ HW. So, add a new helper to scan the input cmd to make sure it is supported when selecting a queue, though this assumes that SMMUv3 driver will only add the same type of commands into an arm_smmu_cmdq_batch as it does today. Note that the guest VM shouldn't have HYP_OWN bit being set regardless of guest kernel driver writing it or not, i.e. the hypervisor running in the host OS should wire this bit to zero when trapping a write access to this VINTF_CONFIG register from a guest kernel. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 +++++++----- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +- .../iommu/arm/arm-smmu-v3/tegra241-cmdqv.c | 35 ++++++++++++++++++- 3 files changed, 49 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 18d940c65e2c..8ff8e264d5e7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -336,12 +336,13 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) return 0; } -static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) +static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu, + u8 opcode) { struct arm_smmu_cmdq *cmdq = NULL; if (smmu->impl && smmu->impl->get_secondary_cmdq) - cmdq = smmu->impl->get_secondary_cmdq(smmu); + cmdq = smmu->impl->get_secondary_cmdq(smmu, opcode); return cmdq ?: &smmu->cmdq; } @@ -889,7 +890,7 @@ static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, } return arm_smmu_cmdq_issue_cmdlist( - smmu, arm_smmu_get_cmdq(smmu), cmd, 1, sync); + smmu, arm_smmu_get_cmdq(smmu, ent->opcode), cmd, 1, sync); } static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, @@ -905,10 +906,13 @@ static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, } static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq_batch *cmds) + struct arm_smmu_cmdq_batch *cmds, + u8 opcode) { + WARN_ON_ONCE(!opcode); + cmds->num = 0; - cmds->cmdq = arm_smmu_get_cmdq(smmu); + cmds->cmdq = arm_smmu_get_cmdq(smmu, opcode); } static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, @@ -1195,7 +1199,7 @@ static void arm_smmu_sync_cd(struct arm_smmu_master *master, }, }; - arm_smmu_cmdq_batch_init(smmu, &cmds); + arm_smmu_cmdq_batch_init(smmu, &cmds, CMDQ_OP_CFGI_CD); for (i = 0; i < master->num_streams; i++) { cmd.cfgi.sid = master->streams[i].id; arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); @@ -2046,7 +2050,7 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_master *master, arm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd); - arm_smmu_cmdq_batch_init(master->smmu, &cmds); + arm_smmu_cmdq_batch_init(master->smmu, &cmds, CMDQ_OP_ATC_INV); for (i = 0; i < master->num_streams; i++) { cmd.atc.sid = master->streams[i].id; arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); @@ -2084,7 +2088,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, if (!atomic_read(&smmu_domain->nr_ats_masters)) return 0; - arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds); + arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, CMDQ_OP_ATC_INV); spin_lock_irqsave(&smmu_domain->devices_lock, flags); list_for_each_entry(master_domain, &smmu_domain->devices, @@ -2166,7 +2170,7 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, num_pages++; } - arm_smmu_cmdq_batch_init(smmu, &cmds); + arm_smmu_cmdq_batch_init(smmu, &cmds, cmd->opcode); while (iova < end) { if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 367f5e160af4..c7f34a5c31f3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -633,7 +633,8 @@ struct arm_smmu_strtab_cfg { struct arm_smmu_impl { int (*device_reset)(struct arm_smmu_device *smmu); void (*device_remove)(struct arm_smmu_device *smmu); - struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu); + struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu, + u8 opcode); }; #ifdef CONFIG_TEGRA241_CMDQV diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c index c1e85c95fb99..c20e54aeec99 100644 --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -144,6 +144,7 @@ struct tegra241_vcmdq { * struct tegra241_vintf - Virtual Interface * @idx: Global index in the CMDQV * @enabled: Enable status + * @hyp_own: Owned by hypervisor (in-kernel) * @cmdqv: Parent CMDQV pointer * @lvcmdqs: List of logical VCMDQ pointers * @base: MMIO base address @@ -152,6 +153,7 @@ struct tegra241_vintf { u16 idx; bool enabled; + bool hyp_own; struct tegra241_cmdqv *cmdqv; struct tegra241_vcmdq **lvcmdqs; @@ -301,8 +303,25 @@ static irqreturn_t tegra241_cmdqv_isr(int irq, void *devid) /* Command Queue Function */ +static bool tegra241_vintf_support_cmd(struct tegra241_vintf *vintf, u8 opcode) +{ + /* Hypervisor-owned VINTF can execute any command in its VCMDQs */ + if (READ_ONCE(vintf->hyp_own)) + return true; + + /* Guest-owned VINTF must check against the list of supported CMDs */ + switch (opcode) { + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_ATC_INV: + return true; + default: + return false; + } +} + static struct arm_smmu_cmdq * -tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) +tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu, u8 opcode) { struct tegra241_cmdqv *cmdqv = container_of(smmu, struct tegra241_cmdqv, smmu); @@ -317,6 +336,10 @@ tegra241_cmdqv_get_cmdq(struct arm_smmu_device *smmu) if (!READ_ONCE(vintf->enabled)) return NULL; + /* Unsupported CMD go for smmu->cmdq pathway */ + if (!tegra241_vintf_support_cmd(vintf, opcode)) + return NULL; + /* * Select a LVCMDQ to use. Here we use a temporal solution to * balance out traffic on cmdq issuing: each cmdq has its own @@ -406,12 +429,22 @@ static int tegra241_vintf_hw_init(struct tegra241_vintf *vintf, bool hyp_own) tegra241_vintf_hw_deinit(vintf); /* Configure and enable VINTF */ + /* + * Note that HYP_OWN bit is wired to zero when running in guest kernel, + * whether enabling it here or not, as !HYP_OWN cmdq HWs only support a + * restricted set of supported commands. + */ regval = FIELD_PREP(VINTF_HYP_OWN, hyp_own); writel(regval, REG_VINTF(vintf, CONFIG)); ret = vintf_write_config(vintf, regval | VINTF_EN); if (ret) return ret; + /* + * As being mentioned above, HYP_OWN bit is wired to zero for a guest + * kernel, so read it back from HW to ensure that reflects in hyp_own + */ + vintf->hyp_own = !!(VINTF_HYP_OWN & readl(REG_VINTF(vintf, CONFIG))); for (lidx = 0; lidx < vintf->cmdqv->num_lvcmdqs_per_vintf; lidx++) { if (vintf->lvcmdqs && vintf->lvcmdqs[lidx]) {