From patchwork Fri Aug 2 01:00:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 1968084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WZnkm1rDFz1ybX for ; Fri, 2 Aug 2024 11:07:59 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C1163858D20 for ; Fri, 2 Aug 2024 01:07:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id D745F3858D20 for ; Fri, 2 Aug 2024 01:07:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D745F3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D745F3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722560853; cv=none; b=Ucup14rWu5qSdVVc+D210YVNiZBPJRzDU1se+JXCYuUku77m/HGhYvDsvHXSTAwD29VhDexO7Oih5yNSpOJf5fdnE/Zg8WnUBDr5cV2skYr8CgF0mt7xknJft9R6IYjWu4u9PwudwKhF5AbC2Coj1BXFI0zjRVo6+j+ucpcgU9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722560853; c=relaxed/simple; bh=a1508fJYJVx8MH/pb9/hvMfZWkQ1G6vKepW1L3TXnY4=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=w4Ozel+6l3uuVXNMqGbHs+p09ludVEYjc5Sfs8YGj55j8PBopBpbhOS1V6EwfycnMO/suD8D+pR9FoizJA39g5ASCbyGbaNAw//kzcr+Opg4HtbsoXp/YjDyff9aFFc6mE+55KA4AGS1aKAbpArFol+LJv6xwk5u5BpIgG8Ewwc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dxh+lHMaxmgTIGAA--.20360S3; Fri, 02 Aug 2024 09:07:20 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by front1 (Coremail) with SMTP id qMiowMBxLsdCMaxm1_0KAA--.54322S2; Fri, 02 Aug 2024 09:07:15 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH v2] LoongArch: Use iorn and andn standard pattern names. Date: Fri, 2 Aug 2024 09:00:33 +0800 Message-Id: <20240802010032.25138-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: qMiowMBxLsdCMaxm1_0KAA--.54322S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Ar1Uur17Ar4kKw1fAryruFX_yoWfAr1xpr ZrCa1vy3y8JFs2g3WkAay5Xw1Ygr17Gr47Zay3Zr9Fya1jqw17X3W0kFZIqF17Xw4ruryS va1rW3WUXFZFk3gCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkjb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I 8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AK xVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64 vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8G jcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0xvE2I x0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK 8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I 0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UNvtZUUUUU= X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org R15-1890 introduced new optabs iorc and andc, and its corresponding internal functions BIT_{ANDC,IORC}, and if targets defines such optabs for vector modes. And in r15-2258 the iorc and andc were renamed to iorn and andn. So we changed the andn and iorn implementation templates to the standard template names. --- v1 -> v2: - Fixed bugs with the [x]vandn implementation in the previous version. - Add testcases. ---- gcc/ChangeLog: * config/loongarch/lasx.md (xvandn3): Rename to ... (andn3): This. (xvorn3): Rename to ... (iorn3): This. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v): Defined as the modified name. (CODE_FOR_lsx_vorn_v): Likewise. (CODE_FOR_lasx_xvandn_v): Likewise. (CODE_FOR_lasx_xvorn_v): Likewise. (loongarch_expand_builtin_insn): When the builtin function to be called is __builtin_lasx_xvandn or __builtin_lsx_vandn, swap the two operands. * config/loongarch/loongarch.md (n): Rename to ... (n3): This. * config/loongarch/lsx.md (vandn3): Rename to ... (andn3): This. (vorn3): Rename to ... (iorn3): This. gcc/testsuite/ChangeLog: * gcc.target/loongarch/lasx-andn-iorn.c: New test. * gcc.target/loongarch/lsx-andn-iorn.c: New test. --- gcc/config/loongarch/lasx.md | 10 +++---- gcc/config/loongarch/loongarch-builtins.cc | 10 ++++--- gcc/config/loongarch/loongarch.md | 8 +++--- gcc/config/loongarch/lsx.md | 10 +++---- .../gcc.target/loongarch/lasx-andn-iorn.c | 11 ++++++++ .../gcc.target/loongarch/lsx-andn-iorn.c | 28 +++++++++++++++++++ 6 files changed, 59 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c create mode 100644 gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 7bd61f8ed5b..ca523880683 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -2716,12 +2716,12 @@ (define_insn "lasx_vext2xv_d_b" (set_attr "mode" "V4DI")]) ;; Extend loongson-sx to loongson-asx. -(define_insn "xvandn3" +(define_insn "andn3" [(set (match_operand:LASX 0 "register_operand" "=f") - (and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f")) - (match_operand:LASX 2 "register_operand" "f")))] + (and:LASX (not:LASX (match_operand:LASX 2 "register_operand" "f")) + (match_operand:LASX 1 "register_operand" "f")))] "ISA_HAS_LASX" - "xvandn.v\t%u0,%u1,%u2" + "xvandn.v\t%u0,%u2,%u1" [(set_attr "type" "simd_logic") (set_attr "mode" "")]) @@ -4637,7 +4637,7 @@ (define_insn "lasx_xvssrlrn__" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) -(define_insn "xvorn3" +(define_insn "iorn3" [(set (match_operand:ILASX 0 "register_operand" "=f") (ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f")) (match_operand:ILASX 1 "register_operand" "f")))] diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index fbe46833c9b..cf92770de30 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d -#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3 -#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3 +#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3 +#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3 #define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2 #define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2 #define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2 @@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) #define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si #define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di -#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3 -#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3 +#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3 +#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3 #define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2 #define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2 #define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2 @@ -2858,6 +2858,7 @@ loongarch_expand_builtin_insn (enum insn_code icode, unsigned int nops, case CODE_FOR_lsx_vpickod_b: case CODE_FOR_lsx_vpickod_h: case CODE_FOR_lsx_vpickod_w: + case CODE_FOR_lsx_vandn_v: case CODE_FOR_lasx_xvilvh_b: case CODE_FOR_lasx_xvilvh_h: case CODE_FOR_lasx_xvilvh_w: @@ -2878,6 +2879,7 @@ loongarch_expand_builtin_insn (enum insn_code icode, unsigned int nops, case CODE_FOR_lasx_xvpickod_b: case CODE_FOR_lasx_xvpickod_h: case CODE_FOR_lasx_xvpickod_w: + case CODE_FOR_lasx_xvandn_v: /* Swap the operands 1 and 2 for interleave operations. Built-ins follow convention of ISA, which have op1 as higher component and op2 as lower component. However, the VEC_PERM op in tree and vec_concat in RTL diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 459ad30b9bb..1db8ce9f34b 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1668,13 +1668,13 @@ (define_insn "*norsi3_internal" [(set_attr "type" "logical") (set_attr "mode" "SI")]) -(define_insn "n" +(define_insn "n3" [(set (match_operand:X 0 "register_operand" "=r") (neg_bitwise:X - (not:X (match_operand:X 1 "register_operand" "r")) - (match_operand:X 2 "register_operand" "r")))] + (not:X (match_operand:X 2 "register_operand" "r")) + (match_operand:X 1 "register_operand" "r")))] "" - "n\t%0,%2,%1" + "n\t%0,%1,%2" [(set_attr "type" "logical") (set_attr "mode" "")]) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 454cda47876..6bdf4fe43f5 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -2344,12 +2344,12 @@ (define_insn_and_split "vec_concatv4sf" } [(set_attr "mode" "V4SF")]) -(define_insn "vandn3" +(define_insn "andn3" [(set (match_operand:LSX 0 "register_operand" "=f") - (and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f")) - (match_operand:LSX 2 "register_operand" "f")))] + (and:LSX (not:LSX (match_operand:LSX 2 "register_operand" "f")) + (match_operand:LSX 1 "register_operand" "f")))] "ISA_HAS_LSX" - "vandn.v\t%w0,%w1,%w2" + "vandn.v\t%w0,%w2,%w1" [(set_attr "type" "simd_logic") (set_attr "mode" "")]) @@ -3028,7 +3028,7 @@ (define_insn "lsx_vssrlrn__" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) -(define_insn "vorn3" +(define_insn "iorn3" [(set (match_operand:ILSX 0 "register_operand" "=f") (ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f")) (match_operand:ILSX 1 "register_operand" "f")))] diff --git a/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c b/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c new file mode 100644 index 00000000000..4aa5f19a650 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c @@ -0,0 +1,11 @@ +#define N 8 + +#include "./lsx-andn-iorn.c" + +/* { dg-do compile } */ +/* { dg-options "-O2 -mlasx -ftree-vectorize" } */ + +/* We should produce a BIT_ANDC and BIT_IORC here. */ + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c b/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c new file mode 100644 index 00000000000..7bceccd37d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/lsx-andn-iorn.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mlsx -ftree-vectorize" } */ + +#ifndef N +#define N 4 +#endif + +extern float a[N], b[N]; +extern int c[N], d[N]; + +void +bar1 (void) +{ + for (int i = 0; i < N; i++) + d[i] = a[i] > b[i] ? 0 : c[i]; +} + +void +bar2 (void) +{ + for (int i = 0; i < N; i++) + d[i] = a[i] > b[i] ? c[i]: -1; +} + +/* We should produce a BIT_ANDC and BIT_IORC here. */ + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */