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X-CSE-ConnectionGUID: IuDbmmwESfuQIxneaN6S6g== X-CSE-MsgGUID: GvqNxxbPTJ6pXgqa50Tjlw== X-IronPort-AV: E=McAfee;i="6700,10204,11150"; a="20373951" X-IronPort-AV: E=Sophos;i="6.09,253,1716274800"; d="scan'208";a="20373951" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2024 00:49:20 -0700 X-CSE-ConnectionGUID: BxDsT0s1SPiLyk16eKq91g== X-CSE-MsgGUID: 3Cc0xErlSIy5XN5pAGJGNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,253,1716274800"; d="scan'208";a="59795608" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa003.jf.intel.com with ESMTP; 01 Aug 2024 00:49:17 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 17600100569E; Thu, 1 Aug 2024 15:49:16 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 1/1] Initial support for AVX10.2 Date: Thu, 1 Aug 2024 15:47:13 +0800 Message-Id: <20240801074713.3677507-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240801074713.3677507-1-haochen.jiang@intel.com> References: <20240801074713.3677507-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Handle avx10.2. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_2_256_SET): New. (OPTION_MASK_ISA2_AVX10_2_512_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_256_UNSET): Add OPTION_MASK_ISA2_AVX10_2_256_UNSET. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Add OPTION_MASK_ISA2_AVX10_2_512_UNSET. (OPTION_MASK_ISA2_AVX10_2_256_UNSET): New. (OPTION_MASK_ISA2_AVX10_2_512_UNSET): Ditto. (ix86_handle_option): Handle avx10.2-256 and avx10.2-512. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_2_256 and FEATURE_AVX10_2_512. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for avx10.2-256 and avx10.2-512. * config/i386/i386-c.cc (ix86_target_macros_internal): Define __AVX10_2_256__ and __AVX10_2_512__. * config/i386/i386-isa.def (AVX10_2): Add DEF_PTA(AVX10_2_256) and DEF_PTA(AVX10_2_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.2-256 and -mavx10.2-512. (ix86_valid_target_attribute_inner_p): Handle avx10.2-256 and avx10.2-512. * config/i386/i386.opt: Add option -mavx10.2, -mavx10.2-256 and -mavx10.2-512. * config/i386/i386.opt.urls: Regenerated. * doc/extend.texi: Document avx10.2, avx10.2-256 and avx10.2-512. * doc/invoke.texi: Document -mavx10.2, -mavx10.2-256 and -mavx10.2-512. * doc/sourcebuild.texi: Document target avx10.2, avx10.2-256, avx10.2-512. gcc/testsuite/ChangeLog: * g++.dg/other/i386-2.C: Ditto. * g++.dg/other/i386-3.C: Ditto. * gcc.target/i386/sse-12.c: Ditto. * gcc.target/i386/sse-13.c: Ditto. * gcc.target/i386/sse-14.c: Ditto. * gcc.target/i386/sse-22.c: Ditto. * gcc.target/i386/sse-23.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 6 ++++ gcc/common/config/i386/i386-common.cc | 43 ++++++++++++++++++++++++-- gcc/common/config/i386/i386-cpuinfo.h | 2 ++ gcc/common/config/i386/i386-isas.h | 3 ++ gcc/config/i386/i386-c.cc | 4 +++ gcc/config/i386/i386-isa.def | 2 ++ gcc/config/i386/i386-options.cc | 7 ++++- gcc/config/i386/i386.opt | 15 +++++++++ gcc/config/i386/i386.opt.urls | 9 ++++++ gcc/doc/extend.texi | 15 +++++++++ gcc/doc/invoke.texi | 17 ++++++++-- gcc/doc/sourcebuild.texi | 9 ++++++ gcc/testsuite/g++.dg/other/i386-2.C | 9 +++--- gcc/testsuite/g++.dg/other/i386-3.C | 9 +++--- gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-- gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- 19 files changed, 140 insertions(+), 22 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 2ae77d335d2..2ae383eb6ab 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -1006,6 +1006,9 @@ get_available_features (struct __processor_model *cpu_model, if (ebx & bit_AVX10_256) switch (version) { + case 2: + set_feature (FEATURE_AVX10_2_256); + /* Fall through. */ case 1: set_feature (FEATURE_AVX10_1_256); break; @@ -1016,6 +1019,9 @@ get_available_features (struct __processor_model *cpu_model, if (ebx & bit_AVX10_512) switch (version) { + case 2: + set_feature (FEATURE_AVX10_2_512); + /* Fall through. */ case 1: set_feature (FEATURE_AVX10_1_512); break; diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index e38b1b22ffb..fb744319b05 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -122,6 +122,11 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256 #define OPTION_MASK_ISA2_AVX10_1_512_SET \ (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512) +#define OPTION_MASK_ISA2_AVX10_2_256_SET \ + (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_2_256) +#define OPTION_MASK_ISA2_AVX10_2_512_SET \ + (OPTION_MASK_ISA2_AVX10_1_512_SET | OPTION_MASK_ISA2_AVX10_2_256_SET \ + | OPTION_MASK_ISA2_AVX10_2_512) /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -307,8 +312,12 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR #define OPTION_MASK_ISA2_AVX10_1_256_UNSET \ - (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET) -#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512 + (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET \ + | OPTION_MASK_ISA2_AVX10_2_256_UNSET) +#define OPTION_MASK_ISA2_AVX10_1_512_UNSET \ + (OPTION_MASK_ISA2_AVX10_1_512 | OPTION_MASK_ISA2_AVX10_2_512_UNSET) +#define OPTION_MASK_ISA2_AVX10_2_256_UNSET OPTION_MASK_ISA2_AVX10_2_256 +#define OPTION_MASK_ISA2_AVX10_2_512_UNSET OPTION_MASK_ISA2_AVX10_2_512 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -1370,6 +1379,36 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx10_2_256: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_256_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_256_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_256_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_256_UNSET; + } + return true; + + case OPT_mavx10_2_512: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_512_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_512_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_2_512_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_512_UNSET; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index ccc6deb6385..b573166e806 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -267,6 +267,8 @@ enum processor_features FEATURE_USER_MSR, FEATURE_AVX10_1_256, FEATURE_AVX10_1_512, + FEATURE_AVX10_2_256, + FEATURE_AVX10_2_512, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 2a092f740bb..a7c7e6318fe 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -186,4 +186,7 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1") ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256") ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512") + ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2") + ISA_NAMES_TABLE_ENTRY("avx10.2-256", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2-256") + ISA_NAMES_TABLE_ENTRY("avx10.2-512", FEATURE_AVX10_2_512, P_NONE, "-mavx10.2-512") ISA_NAMES_TABLE_END diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 403475d5b6b..72435fe568b 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -737,6 +737,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__APX_F__"); if (ix86_apx_inline_asm_use_gpr32) def_or_undef (parse_in, "__APX_INLINE_ASM_USE_GPR32__"); + if (isa_flag2 & OPTION_MASK_ISA2_AVX10_2_256) + def_or_undef (parse_in, "__AVX10_2_256__"); + if (isa_flag2 & OPTION_MASK_ISA2_AVX10_2_512) + def_or_undef (parse_in, "__AVX10_2_512__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 61983f86439..bfb33ba0543 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -121,3 +121,5 @@ DEF_PTA(USER_MSR) DEF_PTA(EVEX512) DEF_PTA(AVX10_1_256) DEF_PTA(AVX10_1_512) +DEF_PTA(AVX10_2_256) +DEF_PTA(AVX10_2_512) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 1c8f7835af2..f423455b363 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -260,7 +260,9 @@ static struct ix86_target_opts isa2_opts[] = { "-mevex512", OPTION_MASK_ISA2_EVEX512 }, { "-musermsr", OPTION_MASK_ISA2_USER_MSR }, { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 }, - { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 } + { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 }, + { "-mavx10.2-256", OPTION_MASK_ISA2_AVX10_2_256 }, + { "-mavx10.2-512", OPTION_MASK_ISA2_AVX10_2_512 } }; static struct ix86_target_opts isa_opts[] = { @@ -1126,6 +1128,9 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256), IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256), IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512), + IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2_256), + IX86_ATTR_ISA ("avx10.2-256", OPT_mavx10_2_256), + IX86_ATTR_ISA ("avx10.2-512", OPT_mavx10_2_512), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 7d63d9abd95..7700799817c 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1377,3 +1377,18 @@ mavx10.1 Target Alias(mavx10.1-256) Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX10.1 built-in functions and code generation. + +mavx10.2-256 +Target Mask(ISA2_AVX10_2_256) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +AVX10.1 and AVX10.2 built-in functions and code generation. + +mavx10.2-512 +Target Mask(ISA2_AVX10_2_512) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +AVX10.1-512 and AVX10.2-512 built-in functions and code generation. + +mavx10.2 +Target Alias(mavx10.2-256) +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +AVX10.1 and AVX10.2 built-in functions and code generation. diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls index 9384b0b3187..fc70616a31d 100644 --- a/gcc/config/i386/i386.opt.urls +++ b/gcc/config/i386/i386.opt.urls @@ -604,3 +604,12 @@ UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512) mavx10.1 UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1) +mavx10.2-256 +UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2-256) + +mavx10.2-512 +UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2-512) + +mavx10.2 +UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2) + diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 66c99ef7a66..9057bfa8bbe 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7412,6 +7412,21 @@ Enable/disable the generation of the AVX10.1 instructions. @itemx no-avx10.1-512 Enable/disable the generation of the AVX10.1 512 bit instructions. +@cindex @code{target("avx10.2")} function attribute, x86 +@item avx10.2 +@itemx no-avx10.2 +Enable/disable the generation of the AVX10.2 instructions. + +@cindex @code{target("avx10.2-256")} function attribute, x86 +@item avx10.2-256 +@itemx no-avx10.2-256 +Enable/disbale the generation of the AVX10.2 instructions. + +@cindex @code{target("avx10.2-512")} function attribute, x86 +@item avx10.2-512 +@itemx no-avx10.2-512 +Enable/disable the generation of the AVX10.2 512 bit instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 9fb0925ed29..31ea8497d28 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1479,7 +1479,8 @@ See RS/6000 and PowerPC Options. -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf --musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 +-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2 -mavx10.2-256 +-mavx10.2-512 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -35681,6 +35682,15 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex mavx10.1-512 @itemx -mavx10.1-512 +@need 200 +@opindex mavx10.2 +@itemx -mavx10.2 +@need 200 +@opindex mavx10.2-256 +@itemx -mavx10.2-256 +@need 200 +@opindex mavx10.2-512 +@itemx -mavx10.2-512 These switches enable the use of instructions in the MMX, SSE, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, @@ -35691,8 +35701,9 @@ WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX512VNNI, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, -SM4, APX_F, USER_MSR, AVX10.1 or CLDEMOTE extended instruction sets. Each has -a corresponding @option{-mno-} option to disable use of these instructions. +SM4, APX_F, USER_MSR, AVX10.1, AVX10.2 or CLDEMOTE extended instruction sets. +Each has a corresponding @option{-mno-} option to disable use of these +instructions. These extensions are also available as built-in functions: see @ref{x86 Built-in Functions}, for details of the functions enabled and diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 66c4206bfc2..2864a345ca7 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2581,6 +2581,15 @@ Target supports the execution of @code{avx10.1} instructions. @item avx10.1-512 Target supports the execution of @code{avx10.1-512} instructions. +@item avx10.2 +Target supports the execution of @code{avx10.2} instructions. + +@item avx10.2-256 +Target supports the execution of @code{avx10.2} instructions. + +@item avx10.2-512 +Target supports the execution of @code{avx10.2-512} instructions. + @item avx2 Target supports compiling @code{avx2} instructions. diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C index 3f3df902b56..5a4005c063c 100644 --- a/gcc/testsuite/g++.dg/other/i386-2.C +++ b/gcc/testsuite/g++.dg/other/i386-2.C @@ -1,12 +1,11 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512cd -msha -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, - popcntintrin.h, fmaintrin.h, pkuintrin.h, avx5124fmapsintrin.h, - avx5124vnniwintrin.h, avx512vpopcntdqintrin.h gfniintrin.h - avx512bitalgintrin.h, avx512vp2intersectintrin.h, tsxldtrkintrin.h, - amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h, + popcntintrin.h, fmaintrin.h, pkuintrin.h, avx512vpopcntdqintrin.h, + gfniintrin.h, avx512bitalgintrin.h, avx512vp2intersectintrin.h, + tsxldtrkintrin.h, amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h, avx512vp2intersectvlintrin.h and mm_malloc.h.h are usable with -O -pedantic-errors. */ diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C index 50df2d71715..51977ae6159 100644 --- a/gcc/testsuite/g++.dg/other/i386-3.C +++ b/gcc/testsuite/g++.dg/other/i386-3.C @@ -1,12 +1,11 @@ /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512cd -msha -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512" } */ /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, - popcntintrin.h, fmaintrin.h, pkuintrin.h, avx5124fmapsintrin.h, - avx5124vnniwintrin.h, avx512vpopcntdqintrin.h gfniintrin.h - avx512bitalgintrin.h, avx512vp2intersectintrin.h, tsxldtrkintrin.h, - amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h, + popcntintrin.h, fmaintrin.h, pkuintrin.h, avx512vpopcntdqintrin.h, + gfniintrin.h, avx512bitalgintrin.h, avx512vp2intersectintrin.h, + tsxldtrkintrin.h, amxtileintrin.h, amxint8intrin.h, amxbf16intrin.h, avx512vp2intersectvlintrin.h and mm_malloc.h are usable with -O -fkeep-inline-functions. */ diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c index a14652bab6a..fbc39c58554 100644 --- a/gcc/testsuite/gcc.target/i386/sse-12.c +++ b/gcc/testsuite/gcc.target/i386/sse-12.c @@ -3,7 +3,7 @@ popcntintrin.h gfniintrin.h and mm_malloc.h are usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512cd -msha -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512" } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index 567c01d7b50..a4ed83665dc 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512cd -msha -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c index 880633f2413..cbe91bf5fb3 100644 --- a/gcc/testsuite/gcc.target/i386/sse-14.c +++ b/gcc/testsuite/gcc.target/i386/sse-14.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512cd -msha -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2-512" } */ /* { dg-add-options bind_pic_locally } */ #include diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c index bd44e851da0..73367c0d207 100644 --- a/gcc/testsuite/gcc.target/i386/sse-22.c +++ b/gcc/testsuite/gcc.target/i386/sse-22.c @@ -103,7 +103,7 @@ #ifndef DIFFERENT_PRAGMAS -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512cd,sha,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512") #endif /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef DIFFERENT_PRAGMAS -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512cd,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4") +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512") #endif #include test_1 (_cvtss_sh, unsigned short, float, 1) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 8ccc194ef27..9201298a9a8 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -824,6 +824,6 @@ /* sm3intrin.h */ #define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1) -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512cd,sha,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4") +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2-512") #include