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X-Microsoft-Antispam-Message-Info: LdnogwXBDhJIaWKS1nupdOhgxtkENnZ3ffdUFNZHmQVcOmnnuzTolEOwjypoKxKYmfWgVTpGu85G7aIPEy/KMGJEplLFL2OGcClxp8w+ELNMAmQVmmOCmXv95tJLuEaMkihVN2g8gW949yezhKDaB++88dWSkkJRO/kg5W0nd0Rhi2Gtn8rfPELkGsJOUF2Q4ho+kOoRqa25NFZ3NUq9U9c8ZmmkJF1+WqRBic05q+92NZWUvRFYJSiqlIuCw303KGQHHK0aMf5ulbkD0Yp3+QvhviMujjNUzsXYRggTozRaAzTOY6gTTY7pU3UtevjznWIjm0GLaAIFtpGXqwaF8l3RmOHedZY1936cnvrYZaIFsIzDQuKvaBYK+TnJZlzHMA77XrPbYXQoWT8MFFz+TWwqyMcNfcx6ql7jVXRryUnloMt+k+aXdP2eSKbyYe5nJD8ihlq8E2BYZBGPQ0ru72j6oFrmnjMlbisM7STlGB4l6cBA1vOjHUXRkSQDQkIzou6AxPYmyZj6Cs5ArukWbianNCDXssxvKqM6yN1IyYZpl35QGsaFrEVszi5RbuJIl9GjY39TDaGoe+htMwkOQuKwHift5PJtNSxxIpC8WG1rlas14oyV+F7j9cRUFKhmhFIfqRcoR9WGQ+tUGfzape7dhBqj8wkbDPldNaWmi9sItxsqthwOvD3zpYvGsIJPV3Ol3v/UO6qeHroBBEZ3Iclg/MnpUaTvssefeiqSBl9u151iQeyz2w8n/Y4qLoR2gHUGF9T3OU7MTIiN36QUMLtFtyPs0y3QI30rk+aiGvQp6OLVvZQr2r3qB+NpsxwvggYGhGukPRWF1bXmX5EJBfhQ8mZ/sfIxcHHYrYLUaf05aPKh8JJ8zNhZugkc/OrRWPHCQpabV+gHuCTPYVNQeCD8i4kmlOkR5uCoSkHffLEqRX1KWSPXmFNY38n4IAm92Z3A/V42UejSXG2GhKJ7bjLiTWsjrDtCyt1DhGtwVjnK45R0vcvi3J733zAMsCB3SS7VnGCfG/12hnh/F/sXLcldod4psDbdEZRdOW+DxUcYp6vh2MIA1kxXJ9eR1cZ1v2j9VFdxpO+tRXTyMmZW5+KHnVFfPAAP/4hpoOQow1GcYJAI70Fy1Nwt/Hinn2RZnGrWsmMaC15BbsmhFx4LMQmwFBQYkiMSD5VZ1FITJKd5C8y+c6OjzHDOl8yLSdc2ioTLzpz5OgATceA5FJFYzv6FLYxWAqpb5lZXXg6SwP8zo379hUljo39XtMjGwhB2zgbjE4gGZYeDTcVVUODHuNs6gOGL6NroppkDmvdbS69sID52AGeW6q51g5PvDyQWVJT7fEOw9B8pwrbVBtPD9tqj949pT/OYqfuNG64/QdJ7NsLS7Y+olPzlkio8B9tZpsrai8ObRG/9mF1hbm4ZTWfRAafZzSP0rHUgXzcFL6JdZW4YZJyGyzopIKz/uAld X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2024 03:34:53.5732 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c4a8e52-7064-4897-8f24-08dcb1dae834 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9219 The current __arm_lpae_unmap() function calls dma_sync() on individual PTEs after clearing them. Overall unmap performance can be improved by around 25% for large buffer sizes by combining the syncs for adjacent leaf entries. Optimize the unmap time by clearing all the leaf entries and issuing a single dma_sync() for them. Below is detailed analysis of average unmap latency(in us) with and without this optimization obtained by running dma_map_benchmark for different buffer sizes. UnMap Latency(us) Size Without With % gain with optimiztion optimization optimization 4KB 3 3 0 8KB 4 3.8 5 16KB 6.1 5.4 11.48 32KB 10.2 8.5 16.67 64KB 18.5 14.9 19.46 128KB 35 27.5 21.43 256KB 67.5 52.2 22.67 512KB 127.9 97.2 24.00 1MB 248.6 187.4 24.62 2MB 65.5 65.5 0 4MB 119.2 119 0.17 Signed-off-by: Ashish Mhetre --- Changes in V2: - Updated the commit message to be imperative. - Fixed ptep at incorrect index getting cleared for non-leaf entries. --- drivers/iommu/io-pgtable-arm.c | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index f5d9fd1f45bf..32401948b980 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -274,13 +274,15 @@ static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries, sizeof(*ptep) * num_entries, DMA_TO_DEVICE); } -static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg) +static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_cfg *cfg, int num_entries) { + int i; - *ptep = 0; + for (i = 0; i < num_entries; i++) + ptep[i] = 0; if (!cfg->coherent_walk) - __arm_lpae_sync_pte(ptep, 1, cfg); + __arm_lpae_sync_pte(ptep, num_entries, cfg); } static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, @@ -635,9 +637,10 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, unsigned long iova, size_t size, size_t pgcount, int lvl, arm_lpae_iopte *ptep) { + bool gather_queued; arm_lpae_iopte pte; struct io_pgtable *iop = &data->iop; - int i = 0, num_entries, max_entries, unmap_idx_start; + int i = 0, j = 0, num_entries, max_entries, unmap_idx_start; /* Something went horribly wrong and we ran out of page table */ if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) @@ -652,28 +655,33 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, /* If the size matches this level, we're in the right place */ if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { max_entries = ARM_LPAE_PTES_PER_TABLE(data) - unmap_idx_start; + gather_queued = iommu_iotlb_gather_queued(gather); num_entries = min_t(int, pgcount, max_entries); - while (i < num_entries) { - pte = READ_ONCE(*ptep); + /* Find and handle non-leaf entries */ + for (i = 0; i < num_entries; i++) { + pte = READ_ONCE(ptep[i]); if (WARN_ON(!pte)) break; - __arm_lpae_clear_pte(ptep, &iop->cfg); - if (!iopte_leaf(pte, lvl, iop->fmt)) { + __arm_lpae_clear_pte(&ptep[i], &iop->cfg, 1); + /* Also flush any partial walks */ io_pgtable_tlb_flush_walk(iop, iova + i * size, size, ARM_LPAE_GRANULE(data)); __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data)); - } else if (!iommu_iotlb_gather_queued(gather)) { - io_pgtable_tlb_add_page(iop, gather, iova + i * size, size); } - - ptep++; - i++; } + /* Clear the remaining entries */ + if (i) + __arm_lpae_clear_pte(ptep, &iop->cfg, i); + + if (!gather_queued) + for (j = 0; j < i; j++) + io_pgtable_tlb_add_page(iop, gather, iova + j * size, size); + return i * size; } else if (iopte_leaf(pte, lvl, iop->fmt)) { /* From patchwork Thu Aug 1 03:34:32 2024 Content-Type: text/plain; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Aug 2024 03:34:54.9369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58137d62-c4d0-4eea-9853-08dcb1dae910 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000011.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7909 Gather can be NULL when unmap is called for freeing old table while mapping. If it's NULL then there is no need to add page for syncing the TLB. Signed-off-by: Ashish Mhetre --- include/linux/iommu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 4d47f2c33311..2a28c1ef8517 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -928,6 +928,9 @@ static inline void iommu_iotlb_gather_add_page(struct iommu_domain *domain, struct iommu_iotlb_gather *gather, unsigned long iova, size_t size) { + if (!gather) + return; + /* * If the new page is disjoint from the current range or is mapped at * a different granularity, then sync the TLB so that the gather