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Mon, 29 Jul 2024 05:08:01 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5011320049; Mon, 29 Jul 2024 05:07:59 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 51A3920040; Mon, 29 Jul 2024 05:07:58 +0000 (GMT) Received: from genoa.aus.stglabs.ibm.com (unknown [9.40.192.157]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 29 Jul 2024 05:07:58 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V7 1/3] split complicate 64bit constant to memory Date: Mon, 29 Jul 2024 13:07:55 +0800 Message-Id: <20240729050757.2500551-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Aww5wEuALYAo-70-f2T4_wLh840vflem X-Proofpoint-ORIG-GUID: Mw8-xWetglWVHKGXQEdy2gcgyHK734UN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_03,2024-07-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 adultscore=0 malwarescore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407290032 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, Sometimes, a complicated constant is built via 3(or more) instructions. Generally speaking, it would not be as fast as loading it from the constant pool (as the discussions in PR63281): "ld" is one instruction. If consider "address/toc" adjust, we may count it as 2 instructions. And "pld" may need fewer cycles. Adding --param=rs6000-min-insns-constant-in-pool helps to control the instruction number threshold for different scenarios. As known, because the constant is load from memory by this patch, so this functionality may affect the cache missing. While, IMHO, this patch would be still do the right thing. Compare with the previous version: This patch serie adds one more patch to tune the threshold for power10. Boostrap & regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu Guo) PR target/63281 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Split constant to memory for -m64. * config/rs6000/rs6000.opt (rs6000-min-insns-constant-in-pool): New parameter. gcc/testsuite/ChangeLog: * gcc.target/powerpc/const_anchors.c: Test final-rtl. * gcc.target/powerpc/parall_5insn_const.c: Add option --param=rs6000-min-insns-constant-in-pool=5 to keep the original test. * gcc.target/powerpc/pr106550.c: Likewise. * gcc.target/powerpc/pr106550_1.c: Likewise. * gcc.target/powerpc/pr93012.c: Likewise. * gcc.target/powerpc/pr87870.c: Update instruction counts. * gcc.target/powerpc/pr63281.c: New test. --- gcc/config/rs6000/rs6000.cc | 19 +++++++++++++++++++ gcc/config/rs6000/rs6000.opt | 5 +++++ .../gcc.target/powerpc/const_anchors.c | 5 +++-- .../gcc.target/powerpc/parall_5insn_const.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr106550.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr106550_1.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr63281.c | 11 +++++++++++ gcc/testsuite/gcc.target/powerpc/pr87870.c | 5 ++++- gcc/testsuite/gcc.target/powerpc/pr93012.c | 2 +- 9 files changed, 46 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr63281.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 2046a831938..ec384e87868 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10240,6 +10240,25 @@ rs6000_emit_set_const (rtx dest, rtx source) c = sext_hwi (c, 32); emit_move_insn (lo, GEN_INT (c)); } + + /* Use base_reg_operand to avoid spliting "r0=xxx" to "r0=[r0+off]" + after RA when reusing the DEST register to build the value. */ + else if ((can_create_pseudo_p () || base_reg_operand (dest, mode)) + && num_insns_constant (source, mode) + > rs6000_min_insns_constant_in_pool + && TARGET_64BIT) + { + rtx sym = force_const_mem (mode, source); + if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) + && use_toc_relative_ref (XEXP (sym, 0), mode)) + { + rtx toc = create_TOC_reference (XEXP (sym, 0), dest); + sym = gen_const_mem (mode, toc); + set_mem_alias_set (sym, get_TOC_alias_set ()); + } + + emit_move_insn (dest, sym); + } else rs6000_emit_set_long_const (dest, c); break; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index e8ca70340df..a1c0d1e89c5 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -679,3 +679,8 @@ default value is 4. Target Undocumented Joined UInteger Var(rs6000_vect_unroll_reduc_threshold) Init(1) Param When reduction factor computed for a loop exceeds the threshold specified by this parameter, prefer to unroll this loop. The default value is 1. + +-param=rs6000-min-insns-constant-in-pool= +Target Undocumented Joined UInteger Var(rs6000_min_insns_constant_in_pool) Init(2) IntegerRange(2, 5) Param +The minimum instruction number of building a constant to force loading it from +the constant pool. \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c index 542e2674b12..682e773d506 100644 --- a/gcc/testsuite/gcc.target/powerpc/const_anchors.c +++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c @@ -1,5 +1,5 @@ /* { dg-do compile { target has_arch_ppc64 } } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -fdump-rtl-final" } */ #define C1 0x2351847027482577ULL #define C2 0x2351847027482578ULL @@ -17,4 +17,5 @@ void __attribute__ ((noinline)) foo1 (long long *a, long long b) *a++ = C2; } -/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */ +/* { dg-final { scan-rtl-dump-times {\madddi3\M} 2 "final" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c index e3a9a7264cf..e39479bbf86 100644 --- a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O2 -mno-prefixed -save-temps" } */ +/* { dg-options "-O2 -mno-prefixed --param=rs6000-min-insns-constant-in-pool=5 -save-temps" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* { dg-final { scan-assembler-times {\mlis\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550.c b/gcc/testsuite/gcc.target/powerpc/pr106550.c index 92b76ac8811..2b12a7445b3 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106550.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106550.c @@ -1,5 +1,5 @@ /* PR target/106550 */ -/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 --param=rs6000-min-insns-constant-in-pool=3" } */ /* { dg-require-effective-target has_arch_ppc64 } */ void diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550_1.c b/gcc/testsuite/gcc.target/powerpc/pr106550_1.c index 5ab40d71a56..9da644578a5 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106550_1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106550_1.c @@ -1,7 +1,7 @@ /* PR target/106550 */ /* { dg-require-effective-target power10_ok } */ /* { dg-require-effective-target has_arch_ppc64 } */ -/* { dg-options "-O2 -mdejagnu-cpu=power10 -fdisable-rtl-split1" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -fdisable-rtl-split1 --param=rs6000-min-insns-constant-in-pool=5" } */ /* force the constant splitter run after RA: -fdisable-rtl-split1. */ void diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c new file mode 100644 index 00000000000..9763a7181fc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -0,0 +1,11 @@ +/* Check loading constant from memory pool. */ +/* { dg-options "-O2 -mpowerpc64" } */ + +void +foo (unsigned long long *a) +{ + *a++ = 0x2351847027482577ULL; +} + +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/pr87870.c b/gcc/testsuite/gcc.target/powerpc/pr87870.c index d2108ac3386..09b2e8de901 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr87870.c +++ b/gcc/testsuite/gcc.target/powerpc/pr87870.c @@ -25,4 +25,7 @@ test3 (void) return ((__int128)0xdeadbeefcafebabe << 64) | 0xfacefeedbaaaaaad; } -/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* test3 is using "ld" to load the value to r3 and r4. So there are 2 'ld's + test0, test1 and test2 are using "li", then check 6 'li's. */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mli\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr93012.c b/gcc/testsuite/gcc.target/powerpc/pr93012.c index 4f764d0576f..a89a24aee36 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr93012.c +++ b/gcc/testsuite/gcc.target/powerpc/pr93012.c @@ -1,6 +1,6 @@ /* PR target/93012 */ /* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -std=c99" } */ +/* { dg-options "-O2 -std=c99 --param=rs6000-min-insns-constant-in-pool=5" } */ unsigned long long msk66() { return 0x6666666666666666ULL; } unsigned long long mskih() { return 0xabcd1234abcd1234ULL; } From patchwork Mon Jul 29 05:07:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiufu Guo X-Patchwork-Id: 1965827 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Mon, 29 Jul 2024 05:08:00 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8A39D20040; Mon, 29 Jul 2024 05:07:59 +0000 (GMT) Received: from genoa.aus.stglabs.ibm.com (unknown [9.40.192.157]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 29 Jul 2024 05:07:59 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V7 2/3] split complicate 64bit constant to memory for -m32 -mpowerpc64 Date: Mon, 29 Jul 2024 13:07:56 +0800 Message-Id: <20240729050757.2500551-2-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729050757.2500551-1-guojiufu@linux.ibm.com> References: <20240729050757.2500551-1-guojiufu@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: IUH9oguDZsQynGuEATrwLF0s3CcNl1OW X-Proofpoint-GUID: Wf7bpjHbnKc5xoCfnIeuu7JTZYKkVanV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_03,2024-07-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxscore=0 adultscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407290032 X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, For "-m32 -mpowerpc64", it is also ok to use fewer instruciton (p?ld) to loading 64bit constant from memory. So, splitting the complicate 64bit constant to constant pool should also work for this case. Bootstrap and regtest pass on ppc64{,le}. Also no regression for "-m32 -mpowerpc64" variation on ppc64. Is this ok for trunk? BR, Jeff(Jiufu) Guo gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Split constant to pool for "-m32 -mpowerpc64". gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr63281.c: Allow checking -m32. --- gcc/config/rs6000/rs6000.cc | 21 +++++++++++++++++++-- gcc/testsuite/gcc.target/powerpc/pr63281.c | 2 +- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index ec384e87868..c785fb20b1b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10245,8 +10245,7 @@ rs6000_emit_set_const (rtx dest, rtx source) after RA when reusing the DEST register to build the value. */ else if ((can_create_pseudo_p () || base_reg_operand (dest, mode)) && num_insns_constant (source, mode) - > rs6000_min_insns_constant_in_pool - && TARGET_64BIT) + > rs6000_min_insns_constant_in_pool) { rtx sym = force_const_mem (mode, source); if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) @@ -10256,6 +10255,24 @@ rs6000_emit_set_const (rtx dest, rtx source) sym = gen_const_mem (mode, toc); set_mem_alias_set (sym, get_TOC_alias_set ()); } + else if (TARGET_32BIT) + { + /* After RA, reuse 'DEST' reg. */ + rtx addr = can_create_pseudo_p () + ? gen_reg_rtx (Pmode) + : gen_rtx_REG (Pmode, REGNO (dest)); + rtx sym_ref = XEXP (sym, 0); + if (flag_pic) + emit_move_insn (addr, sym_ref); + else + { + emit_move_insn (addr, gen_rtx_HIGH (Pmode, sym_ref)); + emit_move_insn (addr, gen_rtx_LO_SUM (Pmode, addr, sym_ref)); + } + rtx mem = gen_rtx_MEM (mode, addr); + MEM_COPY_ATTRIBUTES (mem, sym); + sym = mem; + } emit_move_insn (dest, sym); } diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c index 9763a7181fc..16a93b78606 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63281.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -7,5 +7,5 @@ foo (unsigned long long *a) *a++ = 0x2351847027482577ULL; } -/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { has_arch_ppc64 } } } } */ From patchwork Mon Jul 29 05:07:57 2024 Content-Type: text/plain; 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Mon, 29 Jul 2024 05:08:03 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C12982005A; Mon, 29 Jul 2024 05:08:01 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C382120040; Mon, 29 Jul 2024 05:08:00 +0000 (GMT) Received: from genoa.aus.stglabs.ibm.com (unknown [9.40.192.157]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 29 Jul 2024 05:08:00 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, dje.gcc@gmail.com, linkw@gcc.gnu.org, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V7 3/3] slight tune heuristic min_insns_constant_in_pool Date: Mon, 29 Jul 2024 13:07:57 +0800 Message-Id: <20240729050757.2500551-3-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240729050757.2500551-1-guojiufu@linux.ibm.com> References: <20240729050757.2500551-1-guojiufu@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Kw2xpgJPnY3TAOfRZX8y_FRcufdFBBAs X-Proofpoint-GUID: rZYA8rqlUfssDEKKo4LzEiV2Q18LbROS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_03,2024-07-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407290032 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, The default rs6000_min_insns_constant_in_pool is 2, which would suitable for a few cases. While for different targets, we can tune this threshold slightly. For example, 'pld' could load a constant value from memory as faster as building a constant by one instruction, and faster than build a constant through two instructions. This patch tune the parameter rs6000_min_insns_constant_in_pool for TARGET_PREFIXED and TARGET_32BIT. Bootstrap and regtest pass on ppc64 and ppc64le. Is this patch ok for trunk? BR, Jeff(Jiufu) Guo gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_option_override_internal): Tune rs6000_min_insns_constant_in_pool. gcc/testsuite/ChangeLog: * gcc.target/powerpc/const-build-1.c: Keep original test point by using rs6000_min_insns_constant_in_pool. * gcc.target/powerpc/const-build.c: Likewise. --- gcc/config/rs6000/rs6000.cc | 15 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/const-build-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/const-build.c | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index c785fb20b1b..632760dc814 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4847,6 +4847,21 @@ rs6000_option_override_internal (bool global_init_p) warning (0, "%qs is deprecated and not recommended in any circumstances", "-mno-speculate-indirect-jumps"); + /* Set the threshold for how complicated constant should be put + into constant pool. */ + if (!OPTION_SET_P (rs6000_min_insns_constant_in_pool)) + { + /* one insn could load for the constant: pld 3, .LC1@pcrel + ld 0,.LC1@toc(2). */ + if (TARGET_PREFIXED || (TARGET_64BIT && TARGET_CMODEL == CMODEL_SMALL)) + rs6000_min_insns_constant_in_pool = 1; + + /* Consider address addjust, slight increase the threshold: + add 30,0,30; lwz 9,.LC1-.LCTOC1(30); ld 9,0(9); or + lis 9,.LC0@ha; la 9,.LC0@l(9); ld 9,0(9)*/ + else if (TARGET_32BIT && flag_pic != 1) + rs6000_min_insns_constant_in_pool = 3; + } return ret; } diff --git a/gcc/testsuite/gcc.target/powerpc/const-build-1.c b/gcc/testsuite/gcc.target/powerpc/const-build-1.c index 7e35f8c507f..e7061709fea 100644 --- a/gcc/testsuite/gcc.target/powerpc/const-build-1.c +++ b/gcc/testsuite/gcc.target/powerpc/const-build-1.c @@ -1,5 +1,5 @@ /* { dg-do compile { target lp64 } } */ -/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 --param=rs6000-min-insns-constant-in-pool=2" } */ /* { dg-require-effective-target power10_ok } */ unsigned long long msk66() { return 0x6666666666666666ULL; } diff --git a/gcc/testsuite/gcc.target/powerpc/const-build.c b/gcc/testsuite/gcc.target/powerpc/const-build.c index 52941ca4c2f..31e1a611243 100644 --- a/gcc/testsuite/gcc.target/powerpc/const-build.c +++ b/gcc/testsuite/gcc.target/powerpc/const-build.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O2 -save-temps" } */ +/* { dg-options "-O2 -save-temps --param=rs6000-min-insns-constant-in-pool=2" } */ /* { dg-require-effective-target has_arch_ppc64 } */ /* Verify that two instructions are successfully used to build constants.