From patchwork Mon Jul 29 03:24:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 1965817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WXNzV4N0Wz1ybY for ; Mon, 29 Jul 2024 13:25:38 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 279BE385842A for ; Mon, 29 Jul 2024 03:25:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTPS id 415F63858D28 for ; Mon, 29 Jul 2024 03:25:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 415F63858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 415F63858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.84 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722223517; cv=none; b=obgn8jizTkezHBIa9Bm8lTHsUwpkA7BLj8cSwVSSHsHUY/to6hJgcO8TGfyj2ruJoBtwphi0+3fSkaq06WjJQ6+tImp8VmG2ILunumN26gDm+WY9chLZC3YBVv6ZmUMQw2iyKIFzV8gwiBLzEWRtN2SEZNjvFP2tDRhKw6Lyw9w= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722223517; c=relaxed/simple; bh=vwFXn2PC16WHPApI16JeUri5Ge5ft3VuhvII+2vj0Ik=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=dIiWLWKffjXUjg0Z0YoRuJBxKjLSyPgQqtJg/2J4H/k3Z+ngwIY8QcqECv+JHdxZ31+A+q8taQpMRjoqPMtGnaXeqYg9bBGkgNpXLDXMem2nHBx6v2JYNzE9d5Nnn5NMSGyM2s2nzM4n48cJgchKKEujQdX5a42XrxTXC8qgLns= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [112.74.111.65]) by APP-05 (Coremail) with SMTP id zQCowACnEUGOC6dmWVS3AQ--.37284S2; Mon, 29 Jul 2024 11:25:04 +0800 (CST) From: Jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, jlaw@ventanamicro.com, christoph.muellner@vrull.eu, palmer@rivosinc.com, jeff@riscv.org, Jiawei Subject: [RFC] RISC-V: Add support for Profiles RVA/B23. Date: Mon, 29 Jul 2024 11:24:44 +0800 Message-Id: <20240729032444.1429277-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowACnEUGOC6dmWVS3AQ--.37284S2 X-Coremail-Antispam: 1UD129KBjvJXoWxJF48Kr4rZw4rGF47ZFWfuFg_yoWrZFy8pa 18Gwn8KryrZF9Fgws3Gr98Z3W5Aws5urWru3s7Kr17CrWUtrWayF1qkr1Syr48JFsrArn8 uw4Y9w4Y934jqrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr 1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY1x0262kKe7AK xVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F4 0E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1l IxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxV AFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j 6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbSfO7 UUUUU== X-Originating-IP: [112.74.111.65] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCRANAGam72xZAAAAsO X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This patch adds support for RISC-V RVA23 and RVB23 Profiles[1], which depend on the base RISC-V Profiles support[2]. [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-v0.4-rvb23-v0.1-internal-review [2] https://gcc.gnu.org/pipermail/gcc-patches/2024-July/658082.html gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New Profiles. gcc/testsuite/ChangeLog: * gcc.target/riscv/attribute-22.c: New test. * gcc.target/riscv/attribute-23.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 20 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/attribute-22.c | 11 ++++++++++ gcc/testsuite/gcc.target/riscv/attribute-23.c | 10 ++++++++++ 3 files changed, 41 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-23.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 23ae07fe2f3..e6e8adf5e1b 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -323,6 +323,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zicclsm", ISA_SPEC_CLASS_NONE, 1, 0}, {"ziccrse", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zimop", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zcmop", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicntr", ISA_SPEC_CLASS_NONE, 2, 0}, {"zihpm", ISA_SPEC_CLASS_NONE, 2, 0}, @@ -467,6 +470,23 @@ static const riscv_profiles riscv_profiles_table[] = "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" "_zicboz_zfhmin_zkt"}, + /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension + 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"RVA23U64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + + + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"RVB23U64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + /* Currently we do not define S/M mode Profiles in gcc part. */ /* Terminate the list. */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-22.c b/gcc/testsuite/gcc.target/riscv/attribute-22.c new file mode 100644 index 00000000000..0bbb3242ddd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-22.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVA23U64 -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-23.c b/gcc/testsuite/gcc.target/riscv/attribute-23.c new file mode 100644 index 00000000000..459b5641ca3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-23.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=RVB23U64 -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0" +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0" +"_zbb1p0_zbs1p0_zkt1p0\"" } } */