From patchwork Sat Jul 27 08:54:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 1965628 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WWJNn1F5Vz1yYc for ; Sat, 27 Jul 2024 18:55:21 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6573A3858C39 for ; Sat, 27 Jul 2024 08:55:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id ED7763858429 for ; Sat, 27 Jul 2024 08:54:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ED7763858429 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org ED7763858429 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722070491; cv=none; b=oOrBZ0ESKVtYi+Lyd21CVjOIDpCUHx1wfWoqoJyrVrifdK32DVKcFQsbXQiMdMMjp5U6rpQOAe1wxwqw9dvO33XmkLRKy0cNddffgwQZ0yekngjmh/u1JH+gDSwHHWxouZZKyfKTF/U+jYuENJ7HSK3RNZdmZSpdsvrAZSWD9OM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1722070491; c=relaxed/simple; bh=D9swWK/szyAD91LASEEDELX3k2cBKp0cTHdhxZnVS4U=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=PIpuKD/hExeOYcxXtI1UriEX0pq8Ih15yB0NpDtS5TIqx9vTnow+k48DJjwSD9Xn4f4vEovrgwBDaClu4KlG6TBISljEg+h59yLjbRgvB6qAzMlvNSjWD2nhNi2tVqjmCTMpCvppCzrtEVf+VCc5C3fsiA0CtbcUGoQfOPaiQ9M= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8Dxi+rWtaRmmXMCAA--.9239S3; Sat, 27 Jul 2024 16:54:46 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by front1 (Coremail) with SMTP id qMiowMAxX8fStaRmlnIBAA--.7361S2; Sat, 27 Jul 2024 16:54:43 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH] LoongArch: Use iorn and andn standard pattern names. Date: Sat, 27 Jul 2024 16:54:38 +0800 Message-Id: <20240727085438.28284-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: qMiowMAxX8fStaRmlnIBAA--.7361S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoWxuF17Ar4UZF47Jr1DAFy7Arc_yoW7JFW7pr ZrCas2yrW8JFsFg3WkAay5Xw15tr9rGw47Zay3Zr9Fka1jqw1UZFy0kF9IqF17Xw4rur1I gayFg3WjqFW7C3gCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUvYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I 8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv67AK xVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64 vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1l4IxYO2xFxVAFwI0_Jw0_GFylx2IqxVAqx4xG 67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMI IYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E 14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJV W8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07jY38nU UUUU= X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/lasx.md (xvandn3): Rename to ... (andn3): This. (xvorn3): Rename to ... (iorn3): This. * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v): Defined as the modified name. (CODE_FOR_lsx_vorn_v): Likewise. (CODE_FOR_lasx_xvandn_v): Likewise. (CODE_FOR_lasx_xvorn_v): Likewise. * config/loongarch/loongarch.md (n): Rename to ... (n3): This. * config/loongarch/lsx.md (vandn3): Rename to ... (andn3): This. (vorn3): Rename to ... (iorn3): This. --- gcc/config/loongarch/lasx.md | 4 ++-- gcc/config/loongarch/loongarch-builtins.cc | 8 ++++---- gcc/config/loongarch/loongarch.md | 2 +- gcc/config/loongarch/lsx.md | 4 ++-- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md index 7bd61f8ed5b..c5fe04de86c 100644 --- a/gcc/config/loongarch/lasx.md +++ b/gcc/config/loongarch/lasx.md @@ -2716,7 +2716,7 @@ (define_insn "lasx_vext2xv_d_b" (set_attr "mode" "V4DI")]) ;; Extend loongson-sx to loongson-asx. -(define_insn "xvandn3" +(define_insn "andn3" [(set (match_operand:LASX 0 "register_operand" "=f") (and:LASX (not:LASX (match_operand:LASX 1 "register_operand" "f")) (match_operand:LASX 2 "register_operand" "f")))] @@ -4637,7 +4637,7 @@ (define_insn "lasx_xvssrlrn__" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) -(define_insn "xvorn3" +(define_insn "iorn3" [(set (match_operand:ILASX 0 "register_operand" "=f") (ior:ILASX (not:ILASX (match_operand:ILASX 2 "register_operand" "f")) (match_operand:ILASX 1 "register_operand" "f")))] diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc index fbe46833c9b..f0de80d767b 100644 --- a/gcc/config/loongarch/loongarch-builtins.cc +++ b/gcc/config/loongarch/loongarch-builtins.cc @@ -458,8 +458,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) #define CODE_FOR_lsx_vabsd_du CODE_FOR_lsx_vabsd_u_du #define CODE_FOR_lsx_vftint_wu_s CODE_FOR_lsx_vftint_u_wu_s #define CODE_FOR_lsx_vftint_lu_d CODE_FOR_lsx_vftint_u_lu_d -#define CODE_FOR_lsx_vandn_v CODE_FOR_vandnv16qi3 -#define CODE_FOR_lsx_vorn_v CODE_FOR_vornv16qi3 +#define CODE_FOR_lsx_vandn_v CODE_FOR_andnv16qi3 +#define CODE_FOR_lsx_vorn_v CODE_FOR_iornv16qi3 #define CODE_FOR_lsx_vneg_b CODE_FOR_vnegv16qi2 #define CODE_FOR_lsx_vneg_h CODE_FOR_vnegv8hi2 #define CODE_FOR_lsx_vneg_w CODE_FOR_vnegv4si2 @@ -692,8 +692,8 @@ AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE) #define CODE_FOR_lasx_xvrepli_w CODE_FOR_lasx_xvrepliv8si #define CODE_FOR_lasx_xvrepli_d CODE_FOR_lasx_xvrepliv4di -#define CODE_FOR_lasx_xvandn_v CODE_FOR_xvandnv32qi3 -#define CODE_FOR_lasx_xvorn_v CODE_FOR_xvornv32qi3 +#define CODE_FOR_lasx_xvandn_v CODE_FOR_andnv32qi3 +#define CODE_FOR_lasx_xvorn_v CODE_FOR_iornv32qi3 #define CODE_FOR_lasx_xvneg_b CODE_FOR_negv32qi2 #define CODE_FOR_lasx_xvneg_h CODE_FOR_negv16hi2 #define CODE_FOR_lasx_xvneg_w CODE_FOR_negv8si2 diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 459ad30b9bb..4e4ddd515c9 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1668,7 +1668,7 @@ (define_insn "*norsi3_internal" [(set_attr "type" "logical") (set_attr "mode" "SI")]) -(define_insn "n" +(define_insn "n3" [(set (match_operand:X 0 "register_operand" "=r") (neg_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md index 454cda47876..dcb667a6ce5 100644 --- a/gcc/config/loongarch/lsx.md +++ b/gcc/config/loongarch/lsx.md @@ -2344,7 +2344,7 @@ (define_insn_and_split "vec_concatv4sf" } [(set_attr "mode" "V4SF")]) -(define_insn "vandn3" +(define_insn "andn3" [(set (match_operand:LSX 0 "register_operand" "=f") (and:LSX (not:LSX (match_operand:LSX 1 "register_operand" "f")) (match_operand:LSX 2 "register_operand" "f")))] @@ -3028,7 +3028,7 @@ (define_insn "lsx_vssrlrn__" [(set_attr "type" "simd_int_arith") (set_attr "mode" "")]) -(define_insn "vorn3" +(define_insn "iorn3" [(set (match_operand:ILSX 0 "register_operand" "=f") (ior:ILSX (not:ILSX (match_operand:ILSX 2 "register_operand" "f")) (match_operand:ILSX 1 "register_operand" "f")))]