From patchwork Fri Jul 26 11:03:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 1965268 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org; envelope-from=devicetree+bounces-88299-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org [IPv6:2604:1380:45d1:ec00::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WVlPz2cmWz1yY5 for ; Fri, 26 Jul 2024 21:09:27 +1000 (AEST) Received: from smtp.subspace.kernel.org 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Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 26 Jul 2024 19:03:59 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 26 Jul 2024 19:03:59 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 01/10] dt-binding: mfd: aspeed,ast2x00-scu: Add binding for ASPEED AST2700 SCU Date: Fri, 26 Jul 2024 19:03:46 +0800 Message-ID: <20240726110355.2181563-2-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> References: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Kevin Chen --- Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 86ee69c0f45b..3fc991e4514d 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -13,6 +13,7 @@ description: maintainers: - Joel Stanley - Andrew Jeffery + - Kevin Chen properties: compatible: @@ -21,6 +22,7 @@ properties: - aspeed,ast2400-scu - aspeed,ast2500-scu - aspeed,ast2600-scu + - aspeed,ast2700-scu - const: syscon - const: simple-mfd @@ -76,6 +78,7 @@ patternProperties: - aspeed,ast2400-silicon-id - aspeed,ast2500-silicon-id - aspeed,ast2600-silicon-id + - aspeed,ast2700-silicon-id - const: aspeed,silicon-id reg: From patchwork Fri Jul 26 11:03:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 1965269 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=147.75.80.249; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-88300-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org [147.75.80.249]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WVlQD5n5rz1yY5 for ; Fri, 26 Jul 2024 21:09:40 +1000 (AEST) Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by 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+0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 26 Jul 2024 19:03:59 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 02/10] dt-binding: clk: ast2700: Add binding for Aspeed AST27xx Clock Date: Fri, 26 Jul 2024 19:03:47 +0800 Message-ID: <20240726110355.2181563-3-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> References: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Signed-off-by: Kevin Chen --- .../dt-bindings/clock/aspeed,ast2700-clk.h | 180 ++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 include/dt-bindings/clock/aspeed,ast2700-clk.h diff --git a/include/dt-bindings/clock/aspeed,ast2700-clk.h b/include/dt-bindings/clock/aspeed,ast2700-clk.h new file mode 100644 index 000000000000..5ca85503736d --- /dev/null +++ b/include/dt-bindings/clock/aspeed,ast2700-clk.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Device Tree binding constants for AST2700 clock controller. + * + * Copyright (c) 2023 Aspeed Technology Inc. + */ + +#ifndef __DT_BINDINGS_CLOCK_AST2700_H +#define __DT_BINDINGS_CLOCK_AST2700_H + +/* SOC0 clk-gate */ +#define SCU0_CLK_GATE_MCLK (0) +#define SCU0_CLK_GATE_ECLK (1) +#define SCU0_CLK_GATE_GCLK (2) +#define SCU0_CLK_GATE_VCLK (3) +#define SCU0_CLK_GATE_BCLK (4) +#define SCU0_CLK_GATE_D1CLK (5) +#define SCU0_CLK_GATE_REFCLK (6) +#define SCU0_CLK_GATE_USB0CLK (7) +#define SCU0_CLK_GATE_RSV8 (8) +#define SCU0_CLK_GATE_USB1CLK (9) +#define SCU0_CLK_GATE_D2CLK (10) +#define SCU0_CLK_GATE_RSV11 (11) +#define SCU0_CLK_GATE_RSV12 (12) +#define SCU0_CLK_GATE_YCLK (13) +#define SCU0_CLK_GATE_USB2CLK (14) +#define SCU0_CLK_GATE_UART4CLK (15) +#define SCU0_CLK_GATE_SLICLK (16) +#define SCU0_CLK_GATE_DACCLK (17) +#define SCU0_CLK_GATE_DP (18) +#define SCU0_CLK_GATE_RSV19 (19) +#define SCU0_CLK_GATE_CRT1CLK (20) +#define SCU0_CLK_GATE_CRT2CLK (21) +#define SCU0_CLK_GATE_VLCLK (22) +#define SCU0_CLK_GATE_ECCCLK (23) +#define SCU0_CLK_GATE_RSACLK (24) +#define SCU0_CLK_GATE_RVAS0CLK (25) +#define SCU0_CLK_GATE_UFSCLK (26) +#define SCU0_CLK_GATE_EMMCCLK (27) +#define SCU0_CLK_GATE_RVAS1CLK (28) +/* reserved 29 ~ 31*/ +#define SOC0_CLK_GATE_NUM (SCU0_CLK_GATE_RVAS1CLK + 1) + +/* SOC0 clk */ +#define SCU0_CLKIN (SOC0_CLK_GATE_NUM + 0) +#define SCU0_CLK_24M (SOC0_CLK_GATE_NUM + 1) +#define SCU0_CLK_192M (SOC0_CLK_GATE_NUM + 2) +#define SCU0_CLK_UART (SOC0_CLK_GATE_NUM + 3) +#define SCU0_CLK_PSP (SOC0_CLK_GATE_NUM + 4) +#define SCU0_CLK_HPLL (SOC0_CLK_GATE_NUM + 5) +#define SCU0_CLK_HPLL_DIV2 (SOC0_CLK_GATE_NUM + 6) +#define SCU0_CLK_HPLL_DIV4 (SOC0_CLK_GATE_NUM + 7) +#define SCU0_CLK_DPLL (SOC0_CLK_GATE_NUM + 8) +#define SCU0_CLK_MPLL (SOC0_CLK_GATE_NUM + 9) +#define SCU0_CLK_MPLL_DIV2 (SOC0_CLK_GATE_NUM + 10) +#define SCU0_CLK_MPLL_DIV4 (SOC0_CLK_GATE_NUM + 11) +#define SCU0_CLK_MPLL_DIV8 (SOC0_CLK_GATE_NUM + 12) +#define SCU0_CLK_D1CLK (SOC0_CLK_GATE_NUM + 13) +#define SCU0_CLK_D2CLK (SOC0_CLK_GATE_NUM + 14) +#define SCU0_CLK_CRT1 (SOC0_CLK_GATE_NUM + 15) +#define SCU0_CLK_CRT2 (SOC0_CLK_GATE_NUM + 16) +#define SCU0_CLK_MPHY (SOC0_CLK_GATE_NUM + 17) +#define SCU0_CLK_AXI (SOC0_CLK_GATE_NUM + 18) +#define SCU0_CLK_AXI1 (SOC0_CLK_GATE_NUM + 19) +#define SCU0_CLK_AHB (SOC0_CLK_GATE_NUM + 20) +#define SCU0_CLK_APB (SOC0_CLK_GATE_NUM + 21) +#define SCU0_CLK_MCLK (SOC0_CLK_GATE_NUM + 22) +#define SCU0_CLK_ECLK (SOC0_CLK_GATE_NUM + 23) +#define SCU0_CLK_GCLK (SOC0_CLK_GATE_NUM + 24) +#define SCU0_CLK_VCLK (SOC0_CLK_GATE_NUM + 25) +#define SCU0_CLK_BCLK (SOC0_CLK_GATE_NUM + 26) +#define SCU0_CLK_REF (SOC0_CLK_GATE_NUM + 27) +#define SCU0_CLK_USB0CLK (SOC0_CLK_GATE_NUM + 28) +#define SCU0_CLK_USB1CLK (SOC0_CLK_GATE_NUM + 29) +#define SCU0_CLK_USB2CLK (SOC0_CLK_GATE_NUM + 30) +#define SCU0_CLK_YCLK (SOC0_CLK_GATE_NUM + 31) +#define SCU0_CLK_UART4 (SOC0_CLK_GATE_NUM + 32) +#define SCU0_CLK_SLI (SOC0_CLK_GATE_NUM + 33) +#define SCU0_CLK_ECC (SOC0_CLK_GATE_NUM + 34) +#define SCU0_CLK_RSA (SOC0_CLK_GATE_NUM + 35) +#define SCU0_CLK_RVAS0 (SOC0_CLK_GATE_NUM + 36) +#define SCU0_CLK_UFS (SOC0_CLK_GATE_NUM + 37) +#define SCU0_CLK_RVAS1 (SOC0_CLK_GATE_NUM + 38) +#define SCU0_CLK_EMMCMUX (SOC0_CLK_GATE_NUM + 39) +#define SCU0_CLK_EMMC (SOC0_CLK_GATE_NUM + 40) +#define SCU0_CLK_U2PHY_CLK12M (SOC0_CLK_GATE_NUM + 41) +#define SCU0_CLK_U2PHY_REFCLK (SOC0_CLK_GATE_NUM + 42) + +#define SOC0_NUM_CLKS (SCU0_CLK_U2PHY_REFCLK + 1) + +/* SOC1 clk gate */ +#define SCU1_CLK_GATE_LCLK0 (0) +#define SCU1_CLK_GATE_LCLK1 (1) +#define SCU1_CLK_GATE_ESPI0CLK (2) +#define SCU1_CLK_GATE_ESPI1CLK (3) +#define SCU1_CLK_GATE_SDCLK (4) +#define SCU1_CLK_GATE_REFCLK (5) +#define SCU1_CLK_GATE_RSV5CLK (6) +#define SCU1_CLK_GATE_LPCHCLK (7) +#define SCU1_CLK_GATE_MAC0CLK (8) +#define SCU1_CLK_GATE_MAC1CLK (9) +#define SCU1_CLK_GATE_MAC2CLK (10) +#define SCU1_CLK_GATE_UART0CLK (11) +#define SCU1_CLK_GATE_UART1CLK (12) +#define SCU1_CLK_GATE_UART2CLK (13) +#define SCU1_CLK_GATE_UART3CLK (14) +/* reserved bit 15*/ +#define SCU1_CLK_GATE_I3C0CLK (16) +#define SCU1_CLK_GATE_I3C1CLK (17) +#define SCU1_CLK_GATE_I3C2CLK (18) +#define SCU1_CLK_GATE_I3C3CLK (19) +#define SCU1_CLK_GATE_I3C4CLK (20) +#define SCU1_CLK_GATE_I3C5CLK (21) +#define SCU1_CLK_GATE_I3C6CLK (22) +#define SCU1_CLK_GATE_I3C7CLK (23) +#define SCU1_CLK_GATE_I3C8CLK (24) +#define SCU1_CLK_GATE_I3C9CLK (25) +#define SCU1_CLK_GATE_I3C10CLK (26) +#define SCU1_CLK_GATE_I3C11CLK (27) +#define SCU1_CLK_GATE_I3C12CLK (28) +#define SCU1_CLK_GATE_I3C13CLK (29) +#define SCU1_CLK_GATE_I3C14CLK (30) +#define SCU1_CLK_GATE_I3C15CLK (31) + +#define SCU1_CLK_GATE_UART5CLK (32 + 0) +#define SCU1_CLK_GATE_UART6CLK (32 + 1) +#define SCU1_CLK_GATE_UART7CLK (32 + 2) +#define SCU1_CLK_GATE_UART8CLK (32 + 3) +#define SCU1_CLK_GATE_UART9CLK (32 + 4) +#define SCU1_CLK_GATE_UART10CLK (32 + 5) +#define SCU1_CLK_GATE_UART11CLK (32 + 6) +#define SCU1_CLK_GATE_UART12CLK (32 + 7) +#define SCU1_CLK_GATE_FSICLK (32 + 8) +#define SCU1_CLK_GATE_LTPIPHYCLK (32 + 9) +#define SCU1_CLK_GATE_LTPICLK (32 + 10) +#define SCU1_CLK_GATE_VGALCLK (32 + 11) +#define SCU1_CLK_GATE_USBUARTCLK (32 + 12) +#define SCU1_CLK_GATE_CANCLK (32 + 13) +#define SCU1_CLK_GATE_PCICLK (32 + 14) +#define SCU1_CLK_GATE_SLICLK (32 + 15) + +#define SOC1_CLK_GATE_NUM (SCU1_CLK_GATE_SLICLK + 1) + +/* SOC1 clk */ +#define SCU1_CLKIN (SOC1_CLK_GATE_NUM + 0) +#define SCU1_CLK_HPLL (SOC1_CLK_GATE_NUM + 1) +#define SCU1_CLK_APLL (SOC1_CLK_GATE_NUM + 2) +#define SCU1_CLK_APLL_DIV2 (SOC1_CLK_GATE_NUM + 3) +#define SCU1_CLK_APLL_DIV4 (SOC1_CLK_GATE_NUM + 4) +#define SCU1_CLK_DPLL (SOC1_CLK_GATE_NUM + 5) +#define SCU1_CLK_UXCLK (SOC1_CLK_GATE_NUM + 6) +#define SCU1_CLK_HUXCLK (SOC1_CLK_GATE_NUM + 7) +#define SCU1_CLK_UARTX (SOC1_CLK_GATE_NUM + 8) +#define SCU1_CLK_HUARTX (SOC1_CLK_GATE_NUM + 9) +#define SCU1_CLK_AHB (SOC1_CLK_GATE_NUM + 10) +#define SCU1_CLK_APB (SOC1_CLK_GATE_NUM + 11) +#define SCU1_CLK_UART0 (SOC1_CLK_GATE_NUM + 12) +#define SCU1_CLK_UART1 (SOC1_CLK_GATE_NUM + 13) +#define SCU1_CLK_UART2 (SOC1_CLK_GATE_NUM + 14) +#define SCU1_CLK_UART3 (SOC1_CLK_GATE_NUM + 15) +#define SCU1_CLK_UART5 (SOC1_CLK_GATE_NUM + 16) +#define SCU1_CLK_UART6 (SOC1_CLK_GATE_NUM + 17) +#define SCU1_CLK_UART7 (SOC1_CLK_GATE_NUM + 18) +#define SCU1_CLK_UART8 (SOC1_CLK_GATE_NUM + 19) +#define SCU1_CLK_UART9 (SOC1_CLK_GATE_NUM + 20) +#define SCU1_CLK_UART10 (SOC1_CLK_GATE_NUM + 21) +#define SCU1_CLK_UART11 (SOC1_CLK_GATE_NUM + 22) +#define SCU1_CLK_UART12 (SOC1_CLK_GATE_NUM + 23) +#define SCU1_CLK_APLL_DIVN (SOC1_CLK_GATE_NUM + 24) +#define SCU1_CLK_SDMUX (SOC1_CLK_GATE_NUM + 25) +#define SCU1_CLK_SDCLK (SOC1_CLK_GATE_NUM + 26) +#define SCU1_CLK_RMII (SOC1_CLK_GATE_NUM + 27) +#define SCU1_CLK_RGMII (SOC1_CLK_GATE_NUM + 28) +#define SCU1_CLK_MACHCLK (SOC1_CLK_GATE_NUM + 29) +#define SCU1_CLK_MAC0RCLK (SOC1_CLK_GATE_NUM + 30) +#define SCU1_CLK_MAC1RCLK (SOC1_CLK_GATE_NUM + 31) + +#define SOC1_NUM_CLKS (SCU1_CLK_MAC1RCLK + 1) + +#endif From patchwork Fri Jul 26 11:03:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 1965264 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org; envelope-from=devicetree+bounces-88290-incoming-dt=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org 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header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 26 Jul 2024 19:04:00 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 26 Jul 2024 19:04:00 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 04/10] dt-bindings: reset: ast2700: Add binding for ASPEED AST2700 Reset Date: Fri, 26 Jul 2024 19:03:49 +0800 Message-ID: <20240726110355.2181563-5-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> References: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 --- .../dt-bindings/reset/aspeed,ast2700-reset.h | 126 ++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 include/dt-bindings/reset/aspeed,ast2700-reset.h diff --git a/include/dt-bindings/reset/aspeed,ast2700-reset.h b/include/dt-bindings/reset/aspeed,ast2700-reset.h new file mode 100644 index 000000000000..704cdaac3fdc --- /dev/null +++ b/include/dt-bindings/reset/aspeed,ast2700-reset.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Device Tree binding constants for AST2700 reset controller. + * + * Copyright (c) 2023 Aspeed Technology Inc. + */ + +#ifndef _MACH_ASPEED_AST2700_RESET_H_ +#define _MACH_ASPEED_AST2700_RESET_H_ + +/* SOC0 */ +#define SCU0_RESET_SDRAM (0) +#define SCU0_RESET_DDRPHY (1) +#define SCU0_RESET_RSA (2) +#define SCU0_RESET_SHA3 (3) +#define SCU0_RESET_HACE (4) +#define SCU0_RESET_SOC (5) +#define SCU0_RESET_VIDEO (6) +#define SCU0_RESET_2D (7) +#define SCU0_RESET_PCIS (8) +#define SCU0_RESET_RVAS0 (9) +#define SCU0_RESET_RVAS1 (10) +#define SCU0_RESET_SM3 (11) +#define SCU0_RESET_SM4 (12) +#define SCU0_RESET_CRT0 (13) +#define SCU0_RESET_ECC (14) +#define SCU0_RESET_DP_PCI (15) +#define SCU0_RESET_UFS (16) +#define SCU0_RESET_EMMC (17) +#define SCU0_RESET_PCIE1RST (18) +#define SCU0_RESET_PCIE1RSTOE (19) +#define SCU0_RESET_PCIE0RST (20) +#define SCU0_RESET_PCIE0RSTOE (21) +#define SCU0_RESET_JTAG0 (22) +#define SCU0_RESET_MCTP0 (23) +#define SCU0_RESET_MCTP1 (24) +#define SCU0_RESET_XDMA0 (25) +#define SCU0_RESET_XDMA1 (26) +#define SCU0_RESET_H2X1 (27) +#define SCU0_RESET_DP (28) +#define SCU0_RESET_DP_MCU (29) +#define SCU0_RESET_GP_MCU (30) +#define SCU0_RESET_H2X0 (31) +#define SCU0_RESET_P0_VHUB2 (32) +#define SCU0_RESET_P0_PHY3 (33) +#define SCU0_RESET_P0_XHCI (34) +#define SCU0_RESET_P1_VHUB2 (35) +#define SCU0_RESET_P1_PHY3 (36) +#define SCU0_RESET_P1_XHCI (37) +#define SCU0_RESET_P0_USB2 (38) +#define SCU0_RESET_P1_USB2 (39) +#define SCU0_RESET_USB11 (40) +#define SCU0_RESET_RESERVED (41) +#define SCU0_RESET_E2M0 (42) +#define SCU0_RESET_E2M1 (43) + +#define SOC0_RESET_NUMS (SCU0_RESET_E2M1 + 1) + +/* SOC1 */ +#define SCU1_RESET_LPC0 (0) +#define SCU1_RESET_LPC1 (1) +#define SCU1_RESET_MII (2) +#define SCU1_RESET_PECI (3) +#define SCU1_RESET_PWM (4) +#define SCU1_RESET_MAC0 (5) +#define SCU1_RESET_MAC1 (6) +#define SCU1_RESET_MAC2 (7) +#define SCU1_RESET_ADC (8) +#define SCU1_RESET_SD (9) +#define SCU1_RESET_ESPI0 (10) +#define SCU1_RESET_ESPI1 (11) +#define SCU1_RESET_JTAG1 (12) +#define SCU1_RESET_SPI0 (13) +#define SCU1_RESET_SPI1 (14) +#define SCU1_RESET_SPI2 (15) +#define SCU1_RESET_I3C0 (16) +#define SCU1_RESET_I3C1 (17) +#define SCU1_RESET_I3C2 (18) +#define SCU1_RESET_I3C3 (19) +#define SCU1_RESET_I3C4 (20) +#define SCU1_RESET_I3C5 (21) +#define SCU1_RESET_I3C6 (22) +#define SCU1_RESET_I3C7 (23) +#define SCU1_RESET_I3C8 (24) +#define SCU1_RESET_I3C9 (25) +#define SCU1_RESET_I3C10 (26) +#define SCU1_RESET_I3C11 (27) +#define SCU1_RESET_I3C12 (28) +#define SCU1_RESET_I3C13 (29) +#define SCU1_RESET_I3C14 (30) +#define SCU1_RESET_I3C15 (31) +/* reserved 32 */ +#define SCU1_RESET_IOMCU (33) +#define SCU1_RESET_H2A_SPI1 (34) +#define SCU1_RESET_H2A_SPI2 (35) +#define SCU1_RESET_UART0 (36) +#define SCU1_RESET_UART1 (37) +#define SCU1_RESET_UART2 (38) +#define SCU1_RESET_UART3 (39) +#define SCU1_RESET_I2C_FILTER (40) +#define SCU1_RESET_CALIPTRA (41) +/* reserved 42:43 */ +#define SCU1_RESET_FSI (44) +#define SCU1_RESET_CAN (45) +#define SCU1_RESET_MCTP (46) +#define SCU1_RESET_I2C (47) +#define SCU1_RESET_UART6 (48) +#define SCU1_RESET_UART7 (49) +#define SCU1_RESET_UART8 (50) +#define SCU1_RESET_UART9 (51) +#define SCU1_RESET_LTPI (52) +#define SCU1_RESET_VGAL (53) +#define SCU1_RESET_LTPI1 (54) +#define SCU1_RESET_ACE (55) +#define SCU1_RESET_E2M2 (56) +#define SCU1_RESET_UHCI (57) +#define SCU1_RESET_PORTC_USB2H (58) +#define SCU1_RESET_PORTC_USB2V (59) +#define SCU1_RESET_PORTD_USB2H (60) +#define SCU1_RESET_PORTD_USB2V (61) +#define SCU1_RESET_H2X2 (62) +#define SCU1_RESET_I3CDMA (63) + +#define SOC1_RESET_NUMS (SCU1_RESET_I3CDMA + 1) + +#endif /* _MACH_ASPEED_AST2700_RESET_H_ */ From patchwork Fri Jul 26 11:03:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Chen X-Patchwork-Id: 1965265 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org; 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Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 05/10] dt-bindings: arm: aspeed: Add maintainer Date: Fri, 26 Jul 2024 19:03:50 +0800 Message-ID: <20240726110355.2181563-6-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> References: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 95113df178cc..71c31c08a8ad 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -8,6 +8,7 @@ title: Aspeed SoC based boards maintainers: - Joel Stanley + - Kevin Chen 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Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 26 Jul 2024 19:04:00 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 26 Jul 2024 19:04:00 +0800 From: Kevin Chen To: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 06/10] dt-bindings: arm: aspeed: Add aspeed,ast2700-evb compatible string Date: Fri, 26 Jul 2024 19:03:51 +0800 Message-ID: <20240726110355.2181563-7-kevin_chen@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> References: <20240726110355.2181563-1-kevin_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 71c31c08a8ad..b21551817f44 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -99,4 +99,9 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + additionalProperties: true