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Thu, 25 Jul 2024 02:15:06 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46P2F6TV014557 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:06 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:05 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 1/5] aarch64: Rename bic/orn patterns to iorn/andn for vector modes Date: Wed, 24 Jul 2024 19:14:45 -0700 Message-ID: <20240725021449.3650437-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Xcuh41yrljBdCr2PywMwrXB5jWPU04YE X-Proofpoint-GUID: Xcuh41yrljBdCr2PywMwrXB5jWPU04YE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This renames the patterns orn3 to iorn3 so it matches the new optab that was added with r15-1890-gf379596e0ba99d. Likewise for bic3 to andn3. Note the operand 1 and operand 2 are swapped from the original patterns to match the optab now. Built and tested for aarch64-linux-gnu with no regression. gcc/ChangeLog: * config/aarch64/aarch64-simd.md (bic3): Rename to ... (andn3): This. Also swap operands. (orn3): Rename to ... (iorn3): This. Also swap operands. (vec_cmp): Update orn call to iorn and swap the last two arguments. gcc/testsuite/ChangeLog: * g++.target/aarch64/vect_cmp-1.C: New test. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64-simd.md | 20 +++++----- gcc/testsuite/g++.target/aarch64/vect_cmp-1.C | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/g++.target/aarch64/vect_cmp-1.C diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bbeee221f37..459e11b09a1 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -322,21 +322,21 @@ (define_insn "aarch64_simd_mov_from_high" [(set_attr "length" "4")] ) -(define_insn "orn3" +(define_insn "iorn3" [(set (match_operand:VDQ_I 0 "register_operand" "=w") - (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) - (match_operand:VDQ_I 2 "register_operand" "w")))] + (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 2 "register_operand" "w")) + (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" - "orn\t%0., %2., %1." + "orn\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) -(define_insn "bic3" +(define_insn "andn3" [(set (match_operand:VDQ_I 0 "register_operand" "=w") - (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")) - (match_operand:VDQ_I 2 "register_operand" "w")))] + (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 2 "register_operand" "w")) + (match_operand:VDQ_I 1 "register_operand" "w")))] "TARGET_SIMD" - "bic\t%0., %2., %1." + "bic\t%0., %1., %2." [(set_attr "type" "neon_logic")] ) @@ -4064,7 +4064,7 @@ (define_expand "vec_cmp" tmp0, mode), lowpart_subreg (mode, tmp1, mode))); - emit_insn (gen_orn3 (operands[0], tmp2, operands[0])); + emit_insn (gen_iorn3 (operands[0], operands[0], tmp2)); } break; @@ -4111,7 +4111,7 @@ (define_expand "vec_cmp" else if (code == UNEQ) { emit_insn (gen_aarch64_cmeq (tmp, operands[2], operands[3])); - emit_insn (gen_orn3 (operands[0], operands[0], tmp)); + emit_insn (gen_iorn3 (operands[0], tmp, operands[0])); } break; diff --git a/gcc/testsuite/g++.target/aarch64/vect_cmp-1.C b/gcc/testsuite/g++.target/aarch64/vect_cmp-1.C new file mode 100644 index 00000000000..b82d87827d3 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/vect_cmp-1.C @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +#pragma GCC target "+nosve" + +#define vect8 __attribute__((vector_size(8) )) + +/** +**bar1: +** fcmgt v([0-9]+).2s, v[0-9]+.2s, v[0-9]+.2s +** bic v0.8b, v2.8b, v\1.8b +** ret +*/ +extern "C" +vect8 int bar1(vect8 float a, vect8 float b, vect8 int c) +{ + return (a > b) ? 0 : c; +} + +/** +**bar2: +** fcmgt v([0-9]+).2s, v[0-9]+.2s, v[0-9]+.2s +** orn v0.8b, v2.8b, v\1.8b +** ret +*/ +extern "C" +vect8 int bar2(vect8 float a, vect8 float b, vect8 int c) +{ + return (a > b) ? c : -1; +} + +// We should produce a BIT_ANDC and BIT_IORC here. + +// { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } +// { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } + From patchwork Thu Jul 25 02:14:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 1964582 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=ROIoWnRB; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; 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Thu, 25 Jul 2024 02:15:06 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:06 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 2/5] aarch64: sve: Rename aarch64_bic to standard pattern, andn Date: Wed, 24 Jul 2024 19:14:46 -0700 Message-ID: <20240725021449.3650437-2-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725021449.3650437-1-quic_apinski@quicinc.com> References: <20240725021449.3650437-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 6vqVoyM5jn3YBCviAzAIgm_DhilYS58f X-Proofpoint-GUID: 6vqVoyM5jn3YBCviAzAIgm_DhilYS58f X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 mlxlogscore=846 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Now there is an optab for bic, andn since r15-1890-gf379596e0ba99d. This moves aarch64_bic for sve over to use it instead. Note unlike the simd bic patterns, the operands were already in the order that was expected for the optab so no swapping was needed. Built and tested on aarch64-linux-gnu with no regressions. gcc/ChangeLog: * config/aarch64/aarch64-sve-builtins-base.cc (svbic_impl::expand): Update to use andn optab instead of using code_for_aarch64_bic. * config/aarch64/aarch64-sve.md (@aarch64_bic): Rename to ... (andn3): This. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64-sve-builtins-base.cc | 2 +- gcc/config/aarch64/aarch64-sve.md | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index aa26370d397..a2268353ae3 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -271,7 +271,7 @@ public: } if (e.pred == PRED_x) - return e.use_unpred_insn (code_for_aarch64_bic (e.vector_mode (0))); + return e.use_unpred_insn (e.direct_optab_handler (andn_optab)); return e.use_cond_insn (code_for_cond_bic (e.vector_mode (0))); } diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 5331e7121d5..c3ed5075c4e 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -4641,8 +4641,8 @@ (define_insn "3" ;; - BIC ;; ------------------------------------------------------------------------- -;; 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Thu, 25 Jul 2024 02:15:07 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46P2F6Dm008893 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:06 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:06 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 3/5] aarch64: Use iorn and andn standard pattern names for scalar modes Date: Wed, 24 Jul 2024 19:14:47 -0700 Message-ID: <20240725021449.3650437-3-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725021449.3650437-1-quic_apinski@quicinc.com> References: <20240725021449.3650437-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HgOZupjFE43pvPkuSz3T0O41161gxtmy X-Proofpoint-ORIG-GUID: HgOZupjFE43pvPkuSz3T0O41161gxtmy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 mlxlogscore=905 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Since r15-1890-gf379596e0ba99d, these are the new optabs. So let's use these names for them. These will be used to generate during expand from gimple in the next few patches. Built and tested for aarch64-linux-gnu with no regressions. gcc/ChangeLog: * config/aarch64/aarch64.md (*_one_cmpl3): Rename to ... (n3): This. (*_one_cmplsidi3_ze): Rename to ... (*nsidi3_ze): this. Signed-off-by: Andrew Pinski --- gcc/config/aarch64/aarch64.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 94ff0eefa77..ed29127dafb 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5069,18 +5069,18 @@ (define_insn "*one_cmpl_2" ;; Binary logical operators negating one operand, i.e. (a & !b), (a | !b). -(define_insn "*_one_cmpl3" +(define_insn "n3" [(set (match_operand:GPI 0 "register_operand") - (NLOGICAL:GPI (not:GPI (match_operand:GPI 1 "register_operand")) - (match_operand:GPI 2 "register_operand")))] + (NLOGICAL:GPI (not:GPI (match_operand:GPI 2 "register_operand")) + (match_operand:GPI 1 "register_operand")))] "" {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ] - [ r , r , r ; logic_reg , * ] \t%0, %2, %1 - [ w , w , w ; neon_logic , simd ] \t%0., %2., %1. + [ r , r , r ; logic_reg , * ] \t%0, %1, %2 + [ w , w , w ; neon_logic , simd ] \t%0., %1., %2. } ) -(define_insn "*_one_cmplsidi3_ze" +(define_insn "*nsidi3_ze" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (NLOGICAL:SI (not:SI (match_operand:SI 1 "register_operand" "r")) From patchwork Thu Jul 25 02:14:48 2024 Content-Type: text/plain; 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Thu, 25 Jul 2024 02:15:07 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46P2F7uv031817 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:07 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:06 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 4/5] MATCH: Create BIT_ANDN and BIT_IORN from matching Date: Wed, 24 Jul 2024 19:14:48 -0700 Message-ID: <20240725021449.3650437-4-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725021449.3650437-1-quic_apinski@quicinc.com> References: <20240725021449.3650437-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: fdy7Q_q4hPpW08eWzgkeCOy5caEvyrKh X-Proofpoint-GUID: fdy7Q_q4hPpW08eWzgkeCOy5caEvyrKh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 mlxscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 adultscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org To better create rtl directly from gimple, we can use these already internal functions from the gimple. That is simplify `a & ~b` into BIT_ANDN. Likewise `a | ~b` into BIT_IORN. We only want to do this late after vectorization as some targets (e.g. aarch64 SVE) has BIT_IORN on scalars but not on some vector modes; even though the vectorizer could expand it back. Note a few testcases need to be changed to not look into optimized dump and catch them earlier. The modified testcases could catch BIT_ANDN and BIT_IORN so move the testing to forwprop2 before simplification happens. Built and tested on aarch64-linux-gnu with no regressions. PR target/115086 gcc/ChangeLog: * match.pd (`a & ~b`, `a | ~b`): New pattern. (BIT_ANDN/BIT_IORN with CST): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/bic-cst-1.c: New test. * gcc.target/aarch64/bic_simd-1.c: New test. * gcc.dg/tree-ssa/bitops-1.c: Move testing from optimized to forwprop2. * gcc.dg/tree-ssa/bitops-6.c: Likewise. * gcc.dg/tree-ssa/cmpbit-4.c: Likewise. * gcc.dg/tree-ssa/pr110637-2.c: Likewise. * gcc.dg/tree-ssa/pr94880.c: Likewise. * gcc.dg/tree-ssa/pr96671-1.c: Likewise. Signed-off-by: Andrew Pinski --- gcc/match.pd | 17 ++++++++++ gcc/testsuite/gcc.dg/tree-ssa/bitops-1.c | 10 +++--- gcc/testsuite/gcc.dg/tree-ssa/bitops-6.c | 12 +++---- gcc/testsuite/gcc.dg/tree-ssa/bitops-8.c | 8 ++--- gcc/testsuite/gcc.dg/tree-ssa/cmpbit-4.c | 12 +++---- gcc/testsuite/gcc.dg/tree-ssa/pr110637-2.c | 8 ++--- gcc/testsuite/gcc.dg/tree-ssa/pr94880.c | 6 ++-- gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 8 ++--- gcc/testsuite/gcc.target/aarch64/bic-cst-1.c | 31 ++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/bic_simd-1.c | 32 +++++++++++++++++++ 10 files changed, 112 insertions(+), 32 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/bic-cst-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/bic_simd-1.c diff --git a/gcc/match.pd b/gcc/match.pd index cf359b0ec0f..56f631dfeec 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -9979,6 +9979,23 @@ and, (cond_op:s @1 @2 @3 @4 @5) @5) (cond_op (bit_and @1 @0) @2 @3 @4 @5))) +#if GIMPLE +/* Create bit_andc and bit_iorc internal functions. */ +(for bitop (bit_and bit_ior) + bitopc (IFN_BIT_ANDN IFN_BIT_IORN) + (simplify + (bitop:c (bit_not:s @0) @1) + (if (canonicalize_math_after_vectorization_p () + && direct_internal_fn_supported_p (as_internal_fn (bitopc), + type, OPTIMIZE_FOR_BOTH)) + (bitopc @1 @0))) + /* If the second operand is a constant, then reduce it to a & ~cst if + the not simplifies. */ + (simplify + (bitopc @0 CONSTANT_CLASS_P@1) + (bitop (bit_not! @1) @0))) +#endif + /* For pointers @0 and @2 and nonnegative constant offset @1, look for expressions like: diff --git a/gcc/testsuite/gcc.dg/tree-ssa/bitops-1.c b/gcc/testsuite/gcc.dg/tree-ssa/bitops-1.c index cf2823deb62..3a394b1f188 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/bitops-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/bitops-1.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-options "-O -fdump-tree-optimized-raw" } */ +/* { dg-options "-O -fdump-tree-forwprop2-raw" } */ #define DECLS(n,VOL) \ __attribute__((noinline,noclone)) \ @@ -66,7 +66,7 @@ int main(){ } } -/* { dg-final { scan-tree-dump-times "bit_not_expr" 12 "optimized"} } */ -/* { dg-final { scan-tree-dump-times "bit_and_expr" 9 "optimized"} } */ -/* { dg-final { scan-tree-dump-times "bit_ior_expr" 10 "optimized"} } */ -/* { dg-final { scan-tree-dump-times "bit_xor_expr" 9 "optimized"} } */ +/* { dg-final { scan-tree-dump-times "bit_not_expr, " 12 "forwprop2"} } */ +/* { dg-final { scan-tree-dump-times "bit_and_expr, " 9 "forwprop2"} } */ +/* { dg-final { scan-tree-dump-times "bit_ior_expr, " 10 "forwprop2"} } */ +/* { dg-final { scan-tree-dump-times "bit_xor_expr, " 9 "forwprop2"} } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/bitops-6.c b/gcc/testsuite/gcc.dg/tree-ssa/bitops-6.c index e6ab2fd6c71..e08132e2ab5 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/bitops-6.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/bitops-6.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized-raw" } */ +/* { dg-options "-O2 -fdump-tree-forwprop2-raw" } */ /* PR tree-optimization/111282 */ @@ -25,9 +25,9 @@ int fcmp(int x, int y) return a & (b ^ !a); // (x == 2) & (y == 1) } -/* { dg-final { scan-tree-dump-not "bit_xor_expr, " "optimized" } } */ -/* { dg-final { scan-tree-dump-times "bit_and_expr, " 4 "optimized" } } */ -/* { dg-final { scan-tree-dump-times "bit_not_expr, " 1 "optimized" } } */ -/* { dg-final { scan-tree-dump-not "ne_expr, " "optimized" } } */ -/* { dg-final { scan-tree-dump-times "eq_expr, " 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-not "bit_xor_expr, " "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "bit_and_expr, " 4 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "bit_not_expr, " 1 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-not "ne_expr, " "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "eq_expr, " 2 "forwprop2" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/bitops-8.c b/gcc/testsuite/gcc.dg/tree-ssa/bitops-8.c index 40f756e4455..52c2f394222 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/bitops-8.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/bitops-8.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized-raw" } */ +/* { dg-options "-O2 -fdump-tree-forwprop2-raw" } */ /* PR tree-optimization/115224 */ int f1(int a, int b) @@ -9,7 +9,7 @@ int f1(int a, int b) return c | (a ^ b); // ~((a ^ 1) & b) or (a ^ -2) | ~b } -/* { dg-final { scan-tree-dump-times "bit_xor_expr, " 1 "optimized" } } */ -/* { dg-final { scan-tree-dump-times "bit_ior_expr, " 1 "optimized" } } */ -/* { dg-final { scan-tree-dump-times "bit_not_expr, " 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "bit_xor_expr, " 1 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "bit_ior_expr, " 1 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "bit_not_expr, " 1 "forwprop2" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-4.c b/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-4.c index cdba5d623af..627dcc57cc7 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/cmpbit-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized-raw" } */ +/* { dg-options "-O2 -fdump-tree-forwprop2-raw" } */ int g(int x, int y) { @@ -40,8 +40,8 @@ _Bool gbi0(int a, int b) } /* All of these should be optimized to `x & y` or `~x & y` */ -/* { dg-final { scan-tree-dump-times "le_expr, " 3 "optimized" } } */ -/* { dg-final { scan-tree-dump-times "gt_expr, " 1 "optimized" } } */ -/* { dg-final { scan-tree-dump-not "bit_xor_expr, " "optimized" } } */ -/* { dg-final { scan-tree-dump-times "bit_and_expr, " 6 "optimized" } } */ -/* { dg-final { scan-tree-dump-times "bit_not_expr, " 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "le_expr, " 3 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "gt_expr, " 1 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-not "bit_xor_expr, " "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "bit_and_expr, " 6 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times "bit_not_expr, " 2 "forwprop2" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr110637-2.c b/gcc/testsuite/gcc.dg/tree-ssa/pr110637-2.c index f1c5b90353a..81d6a092508 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr110637-2.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr110637-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -fdump-tree-optimized" } */ +/* { dg-options "-O1 -fdump-tree-forwprop2" } */ int f(int a) { int b = a & 1; @@ -8,6 +8,6 @@ int f(int a) } /* This should be optimized to just return `(a&1) ^ 1` or `(~a) & 1`. */ -/* { dg-final { scan-tree-dump-not " == " "optimized"} } */ -/* { dg-final { scan-tree-dump-times "~a" 1 "optimized"} } */ -/* { dg-final { scan-tree-dump-times " & 1" 1 "optimized"} } */ +/* { dg-final { scan-tree-dump-not " == " "forwprop2"} } */ +/* { dg-final { scan-tree-dump-times "~a" 1 "forwprop2"} } */ +/* { dg-final { scan-tree-dump-times " & 1" 1 "forwprop2"} } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr94880.c b/gcc/testsuite/gcc.dg/tree-ssa/pr94880.c index f7216618147..72a14b915a5 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr94880.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr94880.c @@ -1,8 +1,8 @@ /* PR tree-optimization/94786 */ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ -/* { dg-final { scan-tree-dump-times "= ~\[xy\]_" 4 "optimized" } } */ -/* { dg-final { scan-tree-dump-times " & \[xy\]_" 4 "optimized" } } */ +/* { dg-options "-O2 -fdump-tree-forwprop2" } */ +/* { dg-final { scan-tree-dump-times "= ~\[xy\]_" 4 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times " & \[xy\]_" 4 "forwprop2" } } */ unsigned foo_u(unsigned x, unsigned y) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c index 42c5b27b53f..cf977b55cc2 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c @@ -1,9 +1,9 @@ /* PR tree-optimization/96671 */ /* { dg-do compile } */ -/* { dg-options "-O2 -fdump-tree-optimized" } */ -/* { dg-final { scan-tree-dump-times " \\^ " 6 "optimized" } } */ -/* { dg-final { scan-tree-dump-times " ~" 6 "optimized" } } */ -/* { dg-final { scan-tree-dump-times " & " 6 "optimized" } } */ +/* { dg-options "-O2 -fdump-tree-forwprop2" } */ +/* { dg-final { scan-tree-dump-times " \\^ " 6 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times " ~" 6 "forwprop2" } } */ +/* { dg-final { scan-tree-dump-times " & " 6 "forwprop2" } } */ int foo (int a, int b, int c) diff --git a/gcc/testsuite/gcc.target/aarch64/bic-cst-1.c b/gcc/testsuite/gcc.target/aarch64/bic-cst-1.c new file mode 100644 index 00000000000..1c25de3ba84 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic-cst-1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +/** +**bar1: +** mov w([0-9]+), 4 +** bic w0, w\1, w1 +** ret +*/ +int bar1(int a, int c) +{ + int b = 4 & ~c; + return b; +} + +/** +**foo1: +** mov w([0-9]+), 4 +** orn w0, w\1, w1 +** ret +*/ +int foo1(int a, int c) +{ + int b = 4 | ~c; + return b; +} + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/bic_simd-1.c b/gcc/testsuite/gcc.target/aarch64/bic_simd-1.c new file mode 100644 index 00000000000..e2a69272456 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic_simd-1.c @@ -0,0 +1,32 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +/** +**bar1: +** movi v([0-9]+).2s, 0x4 +** bic v0.8b, v\1.8b, v1.8b +** ret +*/ +#define vect8 __attribute__((vector_size(8))) +vect8 int bar1(vect8 int a, vect8 int c) +{ + vect8 int b = 4 & ~c; + return b; +} + +/** +**foo1: +** movi v([0-9]+).2s, 0x4 +** orn v0.8b, v\1.8b, v1.8b +** ret +*/ +vect8 int foo1(vect8 int a, vect8 int c) +{ + vect8 int b = 4 | ~c; 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Thu, 25 Jul 2024 02:15:08 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46P2F7hD025184 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 25 Jul 2024 02:15:07 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 24 Jul 2024 19:15:06 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH 5/5] MATCH: Add an alt pattern for ANDN and IORN with constants Date: Wed, 24 Jul 2024 19:14:49 -0700 Message-ID: <20240725021449.3650437-5-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725021449.3650437-1-quic_apinski@quicinc.com> References: <20240725021449.3650437-1-quic_apinski@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01c.na.qualcomm.com (10.47.97.35) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k6c89yPHIBqaDv0WLelv68p6sieNanq0 X-Proofpoint-ORIG-GUID: k6c89yPHIBqaDv0WLelv68p6sieNanq0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-25_02,2024-07-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407250012 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org With constants we can match `~(a | CST)` into `CST & ~a`. Likewise `~(a & CST)` into `CST | ~a`. Built and tested for aarch64-linux-gnu with no regressions. PR target/116013 PR target/115086 gcc/ChangeLog: * match.pd (`~(a & CST)`, `~(a | CST)`): New pattern. gcc/testsuite/ChangeLog: * gcc.target/aarch64/bic-cst-2.c: New test. * gcc.target/aarch64/bic_simd-2.c: New test. Signed-off-by: Andrew Pinski --- gcc/match.pd | 10 ++++++ gcc/testsuite/gcc.target/aarch64/bic-cst-2.c | 31 +++++++++++++++++ gcc/testsuite/gcc.target/aarch64/bic_simd-2.c | 33 +++++++++++++++++++ 3 files changed, 74 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/bic-cst-2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/bic_simd-2.c diff --git a/gcc/match.pd b/gcc/match.pd index 56f631dfeec..680dfea523f 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -9994,6 +9994,16 @@ and, (simplify (bitopc @0 CONSTANT_CLASS_P@1) (bitop (bit_not! @1) @0))) + +/* Create bit_andc and bit_iorc internal functions. */ +(for rbitop (bit_ior bit_and) + bitopc (IFN_BIT_ANDN IFN_BIT_IORN) + (simplify + (bit_not (rbitop:s @0 CONSTANT_CLASS_P@1)) + (if (canonicalize_math_after_vectorization_p () + && direct_internal_fn_supported_p (as_internal_fn (bitopc), + type, OPTIMIZE_FOR_BOTH)) + (bitopc (bit_not! @1) @0)))) #endif /* For pointers @0 and @2 and nonnegative constant offset @1, look for diff --git a/gcc/testsuite/gcc.target/aarch64/bic-cst-2.c b/gcc/testsuite/gcc.target/aarch64/bic-cst-2.c new file mode 100644 index 00000000000..b89ac72dae1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic-cst-2.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +/** +**bar1: +** mov w([0-9]+), 4 +** bic w0, w\1, w1 +** ret +*/ +int bar1(int a, int c) +{ + int b = ~((~4) | c); + return b; +} + +/** +**foo1: +** mov w([0-9]+), 4 +** orn w0, w\1, w1 +** ret +*/ +int foo1(int a, int c) +{ + int b = ~((~4) & c); + return b; +} + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/bic_simd-2.c b/gcc/testsuite/gcc.target/aarch64/bic_simd-2.c new file mode 100644 index 00000000000..8543ce61400 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bic_simd-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { check-function-bodies "**" "" "" { target { le } } } } */ + +/** +**bar1: +** movi v([0-9]+).2s, 0x4 +** bic v0.8b, v\1.8b, v1.8b +** ret +*/ +#define vect8 __attribute__((vector_size(8))) +vect8 int bar1(vect8 int a, vect8 int c) +{ + vect8 int b = ~((~4) | c); + return b; +} + +/** +**foo1: +** movi v([0-9]+).2s, 0x4 +** orn v0.8b, v\1.8b, v1.8b +** ret +*/ +#define vect8 __attribute__((vector_size(8))) +vect8 int foo1(vect8 int a, vect8 int c) +{ + vect8 int b = ~((~4) & c); + return b; +} + +/* { dg-final { scan-tree-dump ".BIT_ANDN " "optimized" } } */ +/* { dg-final { scan-tree-dump ".BIT_IORN " "optimized" } } */ +