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Mon, 22 Jul 2024 01:26:24 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , , , "Thippeswamy Havalige" Subject: [PATCH v2 1/2] dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx QDMA PCIe Root Port Bridge Date: Mon, 22 Jul 2024 11:55:57 +0530 Message-ID: <20240722062558.1578744-2-thippesw@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240722062558.1578744-1-thippesw@amd.com> References: <20240722062558.1578744-1-thippesw@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: thippesw@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|MN2PR12MB4405:EE_ X-MS-Office365-Filtering-Correlation-Id: 53bac269-f03e-4a0c-c8e7-08dcaa173850 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|376014|1800799024|36860700013; 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Signed-off-by: Thippeswamy Havalige --- .../bindings/pci/xlnx,xdma-host.yaml | 41 ++++++++++++++++++- 1 file changed, 39 insertions(+), 2 deletions(-) --- changes in v2 - update dt node label with pcie. --- diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml index 2f59b3a73dd2..28d9350a7fb4 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -14,10 +14,21 @@ allOf: properties: compatible: - const: xlnx,xdma-host-3.00 + enum: + - xlnx,xdma-host-3.00 + - xlnx,qdma-host-3.00 reg: - maxItems: 1 + items: + - description: configuration region and XDMA bridge register. + - description: QDMA bridge register. + minItems: 1 + + reg-names: + items: + - const: cfg + - const: breg + minItems: 1 ranges: maxItems: 2 @@ -111,4 +122,30 @@ examples: interrupt-controller; }; }; + + pcie@80000000 { + compatible = "xlnx,qdma-host-3.00"; + reg = <0x0 0x80000000 0x0 0x10000000>, <0x0 0x90000000 0x0 0x10000000>; + reg-names = "cfg", "breg"; + ranges = <0x2000000 0x0 0xa8000000 0x0 0xa8000000 0x0 0x8000000>, + <0x43000000 0x4 0x80000000 0x4 0x80000000 0x0 0x40000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = , , + ; + interrupt-names = "misc", "msi0", "msi1"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + pcie_intc_1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; };