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Wed, 17 Jul 2024 10:55:10 +0000 From: "demin.han" To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, pan2.li@intel.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com Subject: [PATCH] RISC-V: More support of vx and vf for autovec comparison Date: Wed, 17 Jul 2024 18:55:19 +0800 Message-ID: <20240717105519.1981872-1-demin.han@starfivetech.com> X-Mailer: git-send-email 2.45.2 X-ClientProxiedBy: NT0PR01CA0035.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::12) To ZQ0PR01MB1063.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:d::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ0PR01MB1063:EE_|ZQ0PR01MB1013:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a7137cc-db64-4b8d-4ca7-08dca64eed6f X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; ARA:13230040|52116014|41320700013|1800799024|366016|38350700014; X-Microsoft-Antispam-Message-Info: zFHWI8n71I00/7lNy3n136pkCJ7B67nJPRUXUHPIPLp4mXenGgpE0XFfrodt3SrYnrnF55AcEfNr1EJqeMuZk69ujGScI7okxNzp7gqiQXaPp9ubtt1lpeI0Zz7xF2WAO7AAoHRwHsfAQZkaG9YJ4yTPiecLLKMBMobn96Bq80YJlSt61vMopME3gV5UPsAI3X036qMzL3zR356dWrofahvfEeeNM3hsBBYOvR6VCn3TRA7X1M6ukHqhle5wKP5w9bveO3c8H/Tih6jSuJ4AtkSIKWFt9gSLH3zc7VQv2nerzPji+EvNhfDqkWKZxCvKbGvbYKk+pzT3ihZUXQKaxZpxEi+kgYIQ4LyfQIaBJ4aYHxZaHvTiYW7dnbaiU3AUsr8J84RaYl+wKcZqHIq3EsmNCr/r05A26B2KWPAAAoogYXZJw0UHTF2Ey2H7Ptw6MFftSIfBhEnDPmnjKoqAxLEcY0ZJKf7eSTSdF7Oava8nvHe7Dt67i8FXp6NI8f4L5fVovsEGUt0fSdmvrBIWQQhhl/mBzSUhdlSee82fN4njg4llOoK1dC0w//OetaiizZOm66njeHyeOVN8GSqbBI18/P3JceHv7AW8gKWvvKyG2XYsB/MsoinucNK2ALb9 X-Forefront-Antispam-Report: CIP:255.255.255.255; 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DI or DF mode under RV32 This patch fix above mentioned issues. Tested on RV32 and RV64. gcc/ChangeLog: * config/riscv/autovec.md: register_operand to nonmemory_operand * config/riscv/riscv-v.cc (get_cmp_insn_code): Select code according * to scalar_p (expand_vec_cmp): Generate scalar_p and transform op1 * config/riscv/riscv.cc (riscv_const_insns): Add !FLOAT_MODE_P * constrain * config/riscv/vector.md: Add !FLOAT_MODE_P constrain gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Fix test * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto * gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Fix and add test * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Fix * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Fix test * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto Signed-off-by: demin.han Signed-off-by: demin.han --- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/riscv-v.cc | 72 ++++++++++++------- gcc/config/riscv/riscv.cc | 2 +- gcc/config/riscv/vector.md | 3 +- .../rvv/autovec/binop/vadd-rv32gcv-nofm.c | 4 +- .../rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 4 +- .../rvv/autovec/binop/vmul-rv32gcv-nofm.c | 4 +- .../rvv/autovec/binop/vsub-rv32gcv-nofm.c | 4 +- .../riscv/rvv/autovec/cmp/vcond-1.c | 48 ++++++++++++- .../rvv/autovec/cond/cond_copysign-rv32gcv.c | 8 +-- .../riscv/rvv/autovec/cond/cond_fadd-1.c | 4 +- .../riscv/rvv/autovec/cond/cond_fadd-2.c | 4 +- .../riscv/rvv/autovec/cond/cond_fadd-3.c | 4 +- .../riscv/rvv/autovec/cond/cond_fadd-4.c | 4 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 4 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 4 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 4 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 4 +- .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmax-1.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmax-2.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmax-3.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmax-4.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmin-1.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmin-2.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmin-3.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmin-4.c | 4 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 4 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 4 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c | 4 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c | 4 +- .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmul-1.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmul-2.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmul-3.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmul-4.c | 4 +- .../riscv/rvv/autovec/cond/cond_fmul-5.c | 4 +- 37 files changed, 162 insertions(+), 97 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index d5793acc999..a7111172153 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -690,7 +690,7 @@ (define_expand "vec_cmp" [(set (match_operand: 0 "register_operand") (match_operator: 1 "comparison_operator" [(match_operand:V_VLSF 2 "register_operand") - (match_operand:V_VLSF 3 "register_operand")]))] + (match_operand:V_VLSF 3 "nonmemory_operand")]))] "TARGET_VECTOR" { riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]), diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index e290675bbf0..e676cb4cd17 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -155,6 +155,11 @@ public: create_output_operand (&m_ops[m_opno++], x, mode); gcc_assert (m_opno <= MAX_OPERANDS); } + void add_integer_operand (rtx x) + { + create_integer_operand (&m_ops[m_opno++], INTVAL (x)); + gcc_assert (m_opno <= MAX_OPERANDS); + } void add_input_operand (rtx x, machine_mode mode) { create_input_operand (&m_ops[m_opno++], x, mode); @@ -284,12 +289,13 @@ public: for (; num_ops; num_ops--, opno++) { any_mem_p |= MEM_P (ops[opno]); - machine_mode mode = insn_data[(int) icode].operand[m_opno].mode; + machine_mode orig_mode = insn_data[(int) icode].operand[m_opno].mode; + machine_mode mode = orig_mode; /* 'create_input_operand doesn't allow VOIDmode. According to vector.md, we may have some patterns that do not have explicit machine mode specifying the operand. Such operands are always Pmode. */ - if (mode == VOIDmode) + if (orig_mode == VOIDmode) mode = Pmode; /* Early assertion ensures same mode since maybe_legitimize_operand @@ -303,7 +309,10 @@ public: insn_data[(int) icode].name, GET_MODE_NAME (required_mode)); - add_input_operand (ops[opno], mode); + if (CONST_INT_P (ops[opno]) && orig_mode != E_VOIDmode) + add_integer_operand (ops[opno]); + else + add_input_operand (ops[opno], mode); } /* Add vl operand. */ @@ -2624,32 +2633,27 @@ expand_vec_init (rtx target, rtx vals) /* Get insn code for corresponding comparison. */ static insn_code -get_cmp_insn_code (rtx_code code, machine_mode mode) +get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p) { insn_code icode; - switch (code) + if (FLOAT_MODE_P (mode)) { - case EQ: - case NE: - case LE: - case LEU: - case GT: - case GTU: - case LTGT: - icode = code_for_pred_cmp (mode); - break; - case LT: - case LTU: - case GE: - case GEU: - if (FLOAT_MODE_P (mode)) - icode = code_for_pred_cmp (mode); + icode = !scalar_p ? code_for_pred_cmp (mode) + : code_for_pred_cmp_scalar (mode); + return icode; + } + if (scalar_p) + { + if (code == GE || code == GEU) + icode = code_for_pred_ge_scalar (mode); else - icode = code_for_pred_ltge (mode); - break; - default: - gcc_unreachable (); + icode = code_for_pred_cmp_scalar (mode); + return icode; } + if (code == LT || code == LTU || code == GE || code == GEU) + icode = code_for_pred_ltge (mode); + else + icode = code_for_pred_cmp (mode); return icode; } @@ -2771,7 +2775,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, { machine_mode mask_mode = GET_MODE (target); machine_mode data_mode = GET_MODE (op0); - insn_code icode = get_cmp_insn_code (code, data_mode); if (code == LTGT) { @@ -2779,12 +2782,29 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask, rtx gt = gen_reg_rtx (mask_mode); expand_vec_cmp (lt, LT, op0, op1, mask, maskoff); expand_vec_cmp (gt, GT, op0, op1, mask, maskoff); - icode = code_for_pred (IOR, mask_mode); + insn_code icode = code_for_pred (IOR, mask_mode); rtx ops[] = {target, lt, gt}; emit_vlmax_insn (icode, BINARY_MASK_OP, ops); return; } + rtx elt; + bool scalar_p = false; + if (const_vec_duplicate_p (op1, &elt)) + { + if (FLOAT_MODE_P (data_mode)) + { + scalar_p = true; + op1 = force_reg (GET_MODE_INNER (GET_MODE (op1)), elt); + } + else if (!has_vi_variant_p (code, elt)) + { + scalar_p = true; + op1 = elt; + } + } + insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p); + rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1); if (!mask && !maskoff) { diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 19b9b2daa95..ad5668b2c5a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2140,7 +2140,7 @@ riscv_const_insns (rtx x) register vec_duplicate into vmv.v.x. */ scalar_mode smode = GET_MODE_INNER (GET_MODE (x)); if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD) - && !immediate_operand (elt, Pmode)) + && !FLOAT_MODE_P (smode) && !immediate_operand (elt, Pmode)) return 0; /* Constants from -16 to 15 can be loaded with vmv.v.i. The Wc0, Wc1 constraints are already covered by the diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index bcedf3d79e2..d1518f3e623 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1486,7 +1486,8 @@ (define_expand "vec_duplicate" { /* Early expand DImode broadcast in RV32 system to avoid RA reload generate (set (reg) (vec_duplicate:DI)). */ - if (maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (Pmode))) + bool gt_p = maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (Pmode)); + if (!FLOAT_MODE_P (mode) && gt_p) { riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (mode), riscv_vector::UNARY_OP, operands); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c index db8c653b179..b9a040f2f78 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c @@ -5,7 +5,7 @@ /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvfadd\.vf} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvfadd\.vf} 5 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index d7a2d259495..0750d8efc3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -8,8 +8,8 @@ /* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ /* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c index 58310135ea6..7197bf2a385 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c @@ -4,6 +4,6 @@ #include "vmul-template.h" /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvfmul\.vf} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c index aa20a90583f..c2afbde8368 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c @@ -6,8 +6,8 @@ /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */ /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {\tvfsub\.vf} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfsub\.vv} 7 } } */ +/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */ /* { dg-final { scan-assembler-times {\tvfrsub\.vf} 4 } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c index 0faedacb2c7..6a072aab281 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c @@ -141,6 +141,34 @@ TEST_VAR_ALL (DEF_VCOND_VAR) TEST_IMM_ALL (DEF_VCOND_IMM) +#define TEST_COND_IMM_FLOAT(T, COND, IMM, SUFFIX) \ + T (float, float, COND, IMM, SUFFIX##_float_float) \ + T (double, double, COND, IMM, SUFFIX##_double_double) + +#define TEST_IMM_FLOAT_ALL(T) \ + TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) \ + TEST_COND_IMM_FLOAT (T, <, 0.0, _lt) \ + TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge) \ + TEST_COND_IMM_FLOAT (T, <=, 0.0, _le) \ + TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq) \ + TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne) \ + \ + TEST_COND_IMM_FLOAT (T, >, 1.0, _gt1) \ + TEST_COND_IMM_FLOAT (T, <, 1.0, _lt1) \ + TEST_COND_IMM_FLOAT (T, >=, 1.0, _ge1) \ + TEST_COND_IMM_FLOAT (T, <=, 1.0, _le1) \ + TEST_COND_IMM_FLOAT (T, ==, 1.0, _eq1) \ + TEST_COND_IMM_FLOAT (T, !=, 1.0, _ne1) \ + \ + TEST_COND_IMM_FLOAT (T, >, -1.0, _gt2) \ + TEST_COND_IMM_FLOAT (T, <, -1.0, _lt2) \ + TEST_COND_IMM_FLOAT (T, >=, -1.0, _ge2) \ + TEST_COND_IMM_FLOAT (T, <=, -1.0, _le2) \ + TEST_COND_IMM_FLOAT (T, ==, -1.0, _eq2) \ + TEST_COND_IMM_FLOAT (T, !=, -1.0, _ne2) + +TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM) + /* { dg-final { scan-assembler-times {\tvmseq\.vi} 42 } } */ /* { dg-final { scan-assembler-times {\tvmsne\.vi} 42 } } */ /* { dg-final { scan-assembler-times {\tvmsgt\.vi} 30 } } */ @@ -152,6 +180,22 @@ TEST_IMM_ALL (DEF_VCOND_IMM) /* { dg-final { scan-assembler-times {\tvmseq} 78 } } */ /* { dg-final { scan-assembler-times {\tvmsne} 78 } } */ /* { dg-final { scan-assembler-times {\tvmsgt} 82 } } */ -/* { dg-final { scan-assembler-times {\tvmslt} 38 } } */ -/* { dg-final { scan-assembler-times {\tvmsge} 38 } } */ +/* { dg-final { scan-assembler-times {\tvmslt} 56 } } */ +/* { dg-final { scan-assembler-times {\tvmsge} 20 } } */ /* { dg-final { scan-assembler-times {\tvmsle} 82 } } */ +/* { dg-final { scan-assembler-times {\tvmseq\.vx} 24 } } */ +/* { dg-final { scan-assembler-times {\tvmsne\.vx} 24 } } */ +/* { dg-final { scan-assembler-times {\tvmsgt\.vx} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmsgtu\.vx} 22 } } */ +/* { dg-final { scan-assembler-times {\tvmslt\.vx} 36 } } */ +/* { dg-final { scan-assembler-times {\tvmsltu\.vx} 0 } } */ +/* { dg-final { scan-assembler-times {\tvmsge\.vx} 0 } } */ +/* { dg-final { scan-assembler-times {\tvmsgeu\.vx} 0 } } */ +/* { dg-final { scan-assembler-times {\tvmsle\.vx} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmsleu\.vx} 22 } } */ +/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfle.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfeq.vf} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmfne.vf} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c index f633d40df10..b9cfc238c73 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c @@ -3,13 +3,13 @@ #include "cond_copysign-template.h" -/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */ /* 1. The vectorizer wraps scalar variants of copysign into vector constants which expand cannot handle currently. 2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently. */ /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */ /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c index 1cdcbf2c36d..1aac30659f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c index 87ba39164a2..947e43ccde2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c @@ -28,6 +28,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c index 728e4470216..8a8d7d03a42 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c index 7f6cb24a3a8..e282d2c2edc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */ -/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c index 4a8523d13da..ef8631dd2ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c @@ -33,7 +33,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c index d49cdbe5715..e3aaba2c921 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c @@ -33,7 +33,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c index 6f37968a222..f91bec12eac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c @@ -33,7 +33,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c index 3a3841ff7ca..381d40532e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c @@ -32,8 +32,8 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* NOTE: 14 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c index 9d084ff0e24..cb878167619 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c @@ -33,8 +33,8 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ /* { dg-final { scan-assembler-times {vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-times {vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ /* NOTE: 14 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c index 1ec67c37f20..95368ad38d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c index d59f7db2406..c07b331d169 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c index 6d8b93db4fc..a01ba8db5b2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c index eb567af346f..9aabfb51d72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c @@ -29,6 +29,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c index d53ffcacb9e..116131b009e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-1.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c index 2cb90512983..6ac47cb0ab9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-2.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c index 44e9be24afe..2d445a9224d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-3.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c index 7ce291d6a40..ae642061c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c @@ -6,6 +6,6 @@ #define FN(X) __builtin_fmin##X #include "cond_fmax-4.c" -/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */ -/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c index 187641f4eaf..1e367b324da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c index e99545e5dfb..3af559dd7ef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c index 456f67db38d..e777c8c4755 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c index 456f67db38d..e777c8c4755 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c index ed9897f86bb..46f2b5ff264 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c @@ -26,7 +26,7 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */ /* NOTE: 3 vmerge is need for other purpose. */ /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c index 97b0c37dab8..0f85dfc4fdc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c index 9ffe3ea6733..6cdb2c40d85 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c @@ -25,6 +25,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c index a1dd46295e9..5a921cb614a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c index 2f59e98f062..939e6bd8f7f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c @@ -26,6 +26,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c index 20d230898e5..608fbef7ba9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c @@ -25,6 +25,6 @@ TEST_ALL (DEF_LOOP) -/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */ +/* { dg-final { scan-assembler-times {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */ /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */