From patchwork Mon Jul 15 02:14:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: HAO CHEN GUI X-Patchwork-Id: 1960387 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=K79u/hce; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WMm470qcpz1xr4 for ; Mon, 15 Jul 2024 12:14:47 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B89BA3864824 for ; Mon, 15 Jul 2024 02:14:44 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id ABC023858289 for ; Mon, 15 Jul 2024 02:14:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ABC023858289 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org ABC023858289 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721009663; cv=none; b=hfwUN6exlxBN9jbDCWYWRDnCK5Z003H6vswjLHn9SibVsdwjCZfIguqDhui/H+THtdRjza6cXRiyor9IpUcxq4buZZ10onQaS0Y4ogAuBdRHZRKwgQgCF8GWwG56PpDqAneHMNU77jU67E9g4bnYZV/VW2o/cIvQf+pj5PA4ieg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1721009663; c=relaxed/simple; bh=QZXzrKEWlgll2P2KA9newsULYOh1dqgwQ9QNvvvcSqQ=; h=DKIM-Signature:Message-ID:Date:MIME-Version:To:From:Subject; b=xC5/TuGzdRU0NKExsHarw+UNEl8YljLQJmjiCbjTGMSNdH/fPV+j7TquZ9ZlfodCwMTSyfcaNMgdun5lvSWLbEnnBrLTf4upYQr431Xmty8vw5r40vLpDkXW2dslvdpx9AfQ7gTh1uzRm1Y0rDAYycnAAUIASgRv+BB3fH9vfHw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0353729.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46F1tN2M006331; Mon, 15 Jul 2024 02:14:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h= message-id:date:mime-version:to:cc:from:subject:content-type :content-transfer-encoding; s=pp1; bh=bOluWaM6T5lAbb7FSf80dhrsR8 oGNG1FvGwKgtog0v0=; b=K79u/hceSMYreGuf7hb8JRIvNksp696w3GCJ28WkHF XkhoJZbdiTD26vkC3QKbA9GLmIlqAyoWB9xKC6l+i5SIChFT11GzZa9AiHuTpGCs OdYTMSTVUCkULCAMaHwcu1e8CS5ERA9R4pjOC5uopoL0Ov3xwoxs/q/oXBS1kCv/ /YfQT8eJboEIZr5s2yzlD2tnuHIvRAmqxCAkxEoVjcsVndevSOfO84YW2xl8vUh/ JNQF9Qsytl3lOL+0eydnp7VXV9OlTeAPemgJ21nhQZ/n8GjdmbjJB9TxdZpOf7hs n8qhNsEdqUEjFDDrXW+quh/nSwjpc0loEhkSB2/9lf1g== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 40cfk7s7u8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jul 2024 02:14:17 +0000 (GMT) Received: from m0353729.ppops.net (m0353729.ppops.net [127.0.0.1]) by pps.reinject (8.18.0.8/8.18.0.8) with ESMTP id 46F2EHZV000584; Mon, 15 Jul 2024 02:14:17 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 40cfk7s7u6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jul 2024 02:14:17 +0000 (GMT) Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 46F0oOr5022007; Mon, 15 Jul 2024 02:14:15 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 40c5dnmksa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jul 2024 02:14:15 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 46F2E9Cl53346656 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 15 Jul 2024 02:14:11 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A6A712004B; Mon, 15 Jul 2024 02:14:09 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 504F520043; Mon, 15 Jul 2024 02:14:07 +0000 (GMT) Received: from [9.197.237.195] (unknown [9.197.237.195]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 15 Jul 2024 02:14:07 +0000 (GMT) Message-ID: <5998649a-afec-4b1b-b638-18c14cf63c13@linux.ibm.com> Date: Mon, 15 Jul 2024 10:14:05 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner From: HAO CHEN GUI Subject: [PATCH, rs6000] Remove redundant guard for float128 mode patterns X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ORKZ9e02gcvmxC27zSy_MIIcyV40EXb6 X-Proofpoint-GUID: bxUaeCNh8-QFLAjLilEXNqvbfmcZpimi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-14_19,2024-07-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 mlxscore=0 suspectscore=0 adultscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407150013 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, This patch removes FLOAT128_IEEE_P guard when the mode of pattern is IEEE128 and FLOAT128_IBM_P when the mode of pattern is IBM128. The mode iterators already do the checking. So they're redundant. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is it OK for trunk? Thanks Gui Haochen ChangeLog rs6000: Remove redundant guard for float128 mode patterns gcc/ * config/rs6000/rs6000.md (movcc, *movcc_p10, *movcc_invert_p10, *fpmask, *xxsel, @ieee_128bit_vsx_abs2, *ieee_128bit_vsx_nabs2, add3, sub3, mul3, div3, sqrt2, copysign3, copysign3_hard, copysign3_soft, @neg2_hw, @abs2_hw, *nabs2_hw, fma4_hw, *fms4_hw, *nfma4_hw, *nfms4_hw, extend2_hw, truncdf2_hw, truncsf2_hw, fix_2_hw, fix_trunc2, *fix_trunc2_mem, float_di2_hw, float_si2_hw, float2, floatuns_di2_hw, floatuns_si2_hw, floatuns2, floor2, ceil2, btrunc2, round2, add3_odd, sub3_odd, mul3_odd, div3_odd, sqrt2_odd, fma4_odd, *fms4_odd, *nfma4_odd, *nfms4_odd, truncdf2_odd, *cmp_hw for IEEE128): Remove guard FLOAT128_IEEE_P. (@extenddf2_fprs, @extenddf2_vsx, truncdf2_internal1, truncdf2_internal2, fix_trunc_helper, neg2, *cmp_internal1, *cmp_internal2 for IBM128): Remove guard FLOAT128_IBM_P. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c0f6599c08b..f22b7ed6256 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5736,7 +5736,7 @@ (define_expand "movcc" (if_then_else:IEEE128 (match_operand 1 "comparison_operator") (match_operand:IEEE128 2 "gpc_reg_operand") (match_operand:IEEE128 3 "gpc_reg_operand")))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) DONE; @@ -5753,7 +5753,7 @@ (define_insn_and_split "*movcc_p10" (match_operand:IEEE128 4 "altivec_register_operand" "v,v") (match_operand:IEEE128 5 "altivec_register_operand" "v,v"))) (clobber (match_scratch:V2DI 6 "=0,&v"))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 6) @@ -5785,7 +5785,7 @@ (define_insn_and_split "*movcc_invert_p10" (match_operand:IEEE128 4 "altivec_register_operand" "v,v") (match_operand:IEEE128 5 "altivec_register_operand" "v,v"))) (clobber (match_scratch:V2DI 6 "=0,&v"))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 6) @@ -5820,7 +5820,7 @@ (define_insn "*fpmask" (match_operand:IEEE128 3 "altivec_register_operand" "v")]) (match_operand:V2DI 4 "all_ones_constant" "") (match_operand:V2DI 5 "zero_constant" "")))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "xscmp%V1qp %0,%2,%3" [(set_attr "type" "fpcompare")]) @@ -5831,7 +5831,7 @@ (define_insn "*xxsel" (match_operand:V2DI 2 "zero_constant" "")) (match_operand:IEEE128 3 "altivec_register_operand" "v") (match_operand:IEEE128 4 "altivec_register_operand" "v")))] - "TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_POWER10 && TARGET_FLOAT128_HW" "xxsel %x0,%x4,%x3,%x1" [(set_attr "type" "vecmove")]) @@ -8904,7 +8904,7 @@ (define_insn_and_split "@extenddf2_fprs" (match_operand:DF 1 "nonimmediate_operand" "d,m,d"))) (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))] "!TARGET_VSX && TARGET_HARD_FLOAT - && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (mode)" + && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 1)) @@ -8921,7 +8921,7 @@ (define_insn_and_split "@extenddf2_vsx" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d") (float_extend:IBM128 (match_operand:DF 1 "nonimmediate_operand" "wa,m")))] - "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (mode)" + "TARGET_LONG_DOUBLE_128 && TARGET_VSX" "#" "&& reload_completed" [(set (match_dup 2) (match_dup 1)) @@ -8967,7 +8967,7 @@ (define_insn_and_split "truncdf2_internal1" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d") (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "0,d")))] - "FLOAT128_IBM_P (mode) && !TARGET_XL_COMPAT + "!TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "@ # @@ -8983,7 +8983,7 @@ (define_insn_and_split "truncdf2_internal1" (define_insn "truncdf2_internal2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") (float_truncate:DF (match_operand:IBM128 1 "gpc_reg_operand" "d")))] - "FLOAT128_IBM_P (mode) && TARGET_XL_COMPAT && TARGET_HARD_FLOAT + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "fadd %0,%1,%L1" [(set_attr "type" "fp")]) @@ -9036,7 +9036,7 @@ (define_insn "fix_trunc_helper" (unspec:DF [(match_operand:IBM128 1 "gpc_reg_operand" "d")] UNSPEC_FIX_TRUNC_TF)) (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))] - "TARGET_HARD_FLOAT && FLOAT128_IBM_P (mode)" + "TARGET_HARD_FLOAT" "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" [(set_attr "type" "fp") (set_attr "length" "20")]) @@ -9191,7 +9191,7 @@ (define_expand "neg2" (define_insn "neg2_internal" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d") (neg:IBM128 (match_operand:IBM128 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && FLOAT128_IBM_P (mode)" + "TARGET_HARD_FLOAT" { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) return "fneg %L0,%L1\;fneg %0,%1"; @@ -9313,7 +9313,7 @@ (define_insn_and_split "@ieee_128bit_vsx_abs2" [(set (match_operand:IEEE128 0 "register_operand" "=wa") (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa"))) (clobber (match_scratch:V16QI 2 "=v"))] - "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW" "#" "&& 1" [(parallel [(set (match_dup 0) @@ -9343,8 +9343,7 @@ (define_insn_and_split "*ieee_128bit_vsx_nabs2" (abs:IEEE128 (match_operand:IEEE128 1 "register_operand" "wa")))) (clobber (match_scratch:V16QI 2 "=v"))] - "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW - && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW" "#" "&& 1" [(parallel [(set (match_dup 0) @@ -12704,7 +12703,7 @@ (define_insn "*cmp_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:IBM128 1 "gpc_reg_operand" "d") (match_operand:IBM128 2 "gpc_reg_operand" "d")))] - "!TARGET_XL_COMPAT && FLOAT128_IBM_P (mode) + "!TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" [(set_attr "type" "fpcompare") @@ -12723,7 +12722,7 @@ (define_insn_and_split "*cmp_internal2" (clobber (match_scratch:DF 9 "=d")) (clobber (match_scratch:DF 10 "=d")) (clobber (match_scratch:GPR 11 "=b"))] - "TARGET_XL_COMPAT && FLOAT128_IBM_P (mode) + "TARGET_XL_COMPAT && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" "#" "&& reload_completed" @@ -15020,7 +15019,7 @@ (define_insn "add3" (plus:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsaddqp %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15030,7 +15029,7 @@ (define_insn "sub3" (minus:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xssubqp %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15040,7 +15039,7 @@ (define_insn "mul3" (mult:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsmulqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15050,7 +15049,7 @@ (define_insn "div3" (div:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsdivqp %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15059,7 +15058,7 @@ (define_insn "sqrt2" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (sqrt:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xssqrtqp %0,%1" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15068,7 +15067,7 @@ (define_expand "copysign3" [(use (match_operand:IEEE128 0 "altivec_register_operand")) (use (match_operand:IEEE128 1 "altivec_register_operand")) (use (match_operand:IEEE128 2 "any_operand"))] - "FLOAT128_IEEE_P (mode)" + "" { /* Middle-end canonicalizes -fabs (x) to copysign (x, -1), but PowerPC prefers -fabs (x). */ @@ -15102,7 +15101,7 @@ (define_insn "copysign3_hard" (copysign:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscpsgnqp %0,%2,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15113,7 +15112,7 @@ (define_insn "copysign3_soft" (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v"))) (clobber (match_scratch:IEEE128 3 "=&v"))] - "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "!TARGET_FLOAT128_HW" "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1" [(set_attr "type" "veccomplex") (set_attr "length" "8")]) @@ -15122,7 +15121,7 @@ (define_insn "@neg2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (neg:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsnegqp %0,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15132,7 +15131,7 @@ (define_insn "@abs2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (abs:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsabsqp %0,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15143,7 +15142,7 @@ (define_insn "*nabs2_hw" (neg:IEEE128 (abs:IEEE128 (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsnabsqp %0,%1" [(set_attr "type" "vecmove") (set_attr "size" "128")]) @@ -15155,7 +15154,7 @@ (define_insn "fma4_hw" (match_operand:IEEE128 1 "altivec_register_operand" "%v") (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsmaddqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15167,7 +15166,7 @@ (define_insn "*fms4_hw" (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsmsubqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15179,7 +15178,7 @@ (define_insn "*nfma4_hw" (match_operand:IEEE128 1 "altivec_register_operand" "%v") (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0"))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsnmaddqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15192,7 +15191,7 @@ (define_insn "*nfms4_hw" (match_operand:IEEE128 2 "altivec_register_operand" "v") (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0")))))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsnmsubqp %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15201,7 +15200,7 @@ (define_insn "extend2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (float_extend:IEEE128 (match_operand:SFDF 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvdpqp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15244,7 +15243,7 @@ (define_insn "truncdf2_hw" [(set (match_operand:DF 0 "altivec_register_operand" "=v") (float_truncate:DF (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvqpdp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15257,7 +15256,7 @@ (define_insn_and_split "truncsf2_hw" (float_truncate:SF (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:DF 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 2) @@ -15287,7 +15286,7 @@ (define_insn_and_split "truncsf2_hw" (define_insn "fix_2_hw" [(set (match_operand:SDI 0 "altivec_register_operand" "=v") (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvqpz %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15296,7 +15295,7 @@ (define_insn "fix_trunc2" [(set (match_operand:QHI 0 "altivec_register_operand" "=v") (any_fix:QHI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvqpwz %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15308,7 +15307,7 @@ (define_insn_and_split "*fix_trunc2_mem" (any_fix:QHSI (match_operand:IEEE128 1 "altivec_register_operand" "v"))) (clobber (match_scratch:QHSI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "#" "&& reload_completed" [(set (match_dup 2) @@ -15319,7 +15318,7 @@ (define_insn_and_split "*fix_trunc2_mem" (define_insn "float_di2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvsdqp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15328,7 +15327,7 @@ (define_insn_and_split "float_si2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ"))) (clobber (match_scratch:DI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 2) @@ -15347,7 +15346,7 @@ (define_insn_and_split "float2" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v,v,v") (float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) (clobber (match_scratch:DI 2 "=X,r,X"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "#" "&& reload_completed" [(const_int 0)] @@ -15384,7 +15383,7 @@ (define_insn "floatuns_di2_hw" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") (unsigned_float:IEEE128 (match_operand:DI 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvudqp %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15394,7 +15393,7 @@ (define_insn_and_split "floatuns_si2_hw" (unsigned_float:IEEE128 (match_operand:SI 1 "nonimmediate_operand" "vrZ"))) (clobber (match_scratch:DI 2 "=v"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "#" "&& 1" [(set (match_dup 2) @@ -15414,7 +15413,7 @@ (define_insn_and_split "floatuns2" (unsigned_float:IEEE128 (match_operand:QHI 1 "nonimmediate_operand" "v,r,Z"))) (clobber (match_scratch:DI 2 "=X,r,X"))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "#" "&& reload_completed" [(const_int 0)] @@ -15447,7 +15446,7 @@ (define_insn "floor2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIM))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsrqpi 1,%0,%1,3" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15457,7 +15456,7 @@ (define_insn "ceil2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIP))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsrqpi 1,%0,%1,2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15467,7 +15466,7 @@ (define_insn "btrunc2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIZ))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsrqpi 1,%0,%1,1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15477,7 +15476,7 @@ (define_insn "round2" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_FRIN))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsrqpi 0,%0,%1,0" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15489,7 +15488,7 @@ (define_insn "add3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_ADD_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsaddqpo %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15500,7 +15499,7 @@ (define_insn "sub3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_SUB_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xssubqpo %0,%1,%2" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15511,7 +15510,7 @@ (define_insn "mul3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_MUL_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsmulqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15522,7 +15521,7 @@ (define_insn "div3_odd" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_DIV_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsdivqpo %0,%1,%2" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15532,7 +15531,7 @@ (define_insn "sqrt2_odd" (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_SQRT_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xssqrtqpo %0,%1" [(set_attr "type" "vecdiv") (set_attr "size" "128")]) @@ -15544,7 +15543,7 @@ (define_insn "fma4_odd" (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsmaddqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15557,7 +15556,7 @@ (define_insn "*fms4_odd" (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsmsubqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15570,7 +15569,7 @@ (define_insn "*nfma4_odd" (match_operand:IEEE128 2 "altivec_register_operand" "v") (match_operand:IEEE128 3 "altivec_register_operand" "0")] UNSPEC_FMA_ROUND_TO_ODD)))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsnmaddqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15584,7 +15583,7 @@ (define_insn "*nfms4_odd" (neg:IEEE128 (match_operand:IEEE128 3 "altivec_register_operand" "0"))] UNSPEC_FMA_ROUND_TO_ODD)))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xsnmsubqpo %0,%1,%2" [(set_attr "type" "qmul") (set_attr "size" "128")]) @@ -15593,7 +15592,7 @@ (define_insn "truncdf2_odd" [(set (match_operand:DF 0 "vsx_register_operand" "=v") (unspec:DF [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_TRUNC_ROUND_TO_ODD))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscvqpdpo %0,%1" [(set_attr "type" "vecfloat") (set_attr "size" "128")]) @@ -15603,7 +15602,7 @@ (define_insn "*cmp_hw" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:IEEE128 2 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" + "TARGET_FLOAT128_HW" "xscmpuqp %0,%1,%2" [(set_attr "type" "veccmp") (set_attr "size" "128")])