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Mon, 15 Jul 2024 02:10:13 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BB60C2004B; Mon, 15 Jul 2024 02:10:11 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E850720040; Mon, 15 Jul 2024 02:10:09 +0000 (GMT) Received: from [9.197.237.195] (unknown [9.197.237.195]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 15 Jul 2024 02:10:09 +0000 (GMT) Message-ID: <23187440-ee81-4816-b3be-2682e64912ed@linux.ibm.com> Date: Mon, 15 Jul 2024 10:10:07 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner From: HAO CHEN GUI Subject: [PATCHv2, rs6000] Add TARGET_FLOAT128_HW guard for quad-precision insns X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 0ryeWR-bLK1haxy5q0tWQcOO3Tm9jXKn X-Proofpoint-ORIG-GUID: eQkwoLD0C-VHIaXWpq5oqJCIbMxST6ym X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-14_19,2024-07-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 bulkscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407150013 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, This patch adds TARGET_FLOAT128_HW into pattern conditions for quad- precision insns. Some qp patterns are guarded by TARGET_P9_VECTOR originally, so replace it with "TARGET_FLOAT128_HW". For test case float128-cmp2-runnable.c, it should be guarded with ppc_float128_hw as it calls qp insns. The p9vector_hw is covered with ppc_float128_hw, so it's removed. Compared to previous version, the main change it to split redundant FLOAT128_IEEE_P removal to another patch. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is it OK for trunk? Thanks Gui Haochen ChangeLog rs6000: Add TARGET_FLOAT128_HW guard for quad-precision insns gcc/ * config/rs6000/rs6000.md (floatti2, floatunsti2, fix_truncti2): Add guard TARGET_FLOAT128_HW. * config/rs6000/vsx.md (xsxexpqp__, xsxsigqp__, xsiexpqpf_, xsiexpqp__, xscmpexpqp__, *xscmpexpqp, xststdcnegqp_): Replace guard TARGET_P9_VECTOR with TARGET_FLOAT128_HW. (xststdc_, *xststdc_, isinf2): Add guard TARGET_FLOAT128_HW for the IEEE128 modes. gcc/testsuite/ * testsuite/gcc.target/powerpc/float128-cmp2-runnable.c: Replace ppc_float128_sw with ppc_float128_hw and remove p9vector_hw. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index deffc4b601c..c0f6599c08b 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -6928,7 +6928,7 @@ (define_insn "floatdidf2" (define_insn "floatti2" [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") (float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvsqqp %0,%1"; } @@ -6937,7 +6937,7 @@ (define_insn "floatti2" (define_insn "floatunsti2" [(set (match_operand:IEEE128 0 "vsx_register_operand" "=v") (unsigned_float:IEEE128 (match_operand:TI 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvuqqp %0,%1"; } @@ -6946,7 +6946,7 @@ (define_insn "floatunsti2" (define_insn "fix_truncti2" [(set (match_operand:TI 0 "vsx_register_operand" "=v") (fix:TI (match_operand:IEEE128 1 "vsx_register_operand" "v")))] - "TARGET_POWER10" + "TARGET_POWER10 && TARGET_FLOAT128_HW" { return "xscvqpsqz %0,%1"; } diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 1272f8b2080..7dd08895bec 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5157,7 +5157,7 @@ (define_insn "xsxexpqp__" (unspec:V2DI_DI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXEXPDP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsxexpqp %0,%1" [(set_attr "type" "vecmove")]) @@ -5176,7 +5176,7 @@ (define_insn "xsxsigqp__" (unspec:VEC_TI [(match_operand:IEEE128 1 "altivec_register_operand" "v")] UNSPEC_VSX_SXSIG))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsxsigqp %0,%1" [(set_attr "type" "vecmove")]) @@ -5196,7 +5196,7 @@ (define_insn "xsiexpqpf_" [(match_operand:IEEE128 1 "altivec_register_operand" "v") (match_operand:DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsiexpqp %0,%1,%2" [(set_attr "type" "vecmove")]) @@ -5208,7 +5208,7 @@ (define_insn "xsiexpqp__" (match_operand:V2DI_DI 2 "altivec_register_operand" "v")] UNSPEC_VSX_SIEXPQP))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xsiexpqp %0,%1,%2" [(set_attr "type" "vecmove")]) @@ -5278,7 +5278,7 @@ (define_expand "xscmpexpqp__" (set (match_operand:SI 0 "register_operand" "=r") (CMP_TEST:SI (match_dup 3) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" { if ( == UNORDERED && !HONOR_NANS (mode)) { @@ -5296,7 +5296,7 @@ (define_insn "*xscmpexpqp" (match_operand:IEEE128 2 "altivec_register_operand" "v")] UNSPEC_VSX_SCMPEXPQP) (match_operand:SI 3 "zero_constant" "j")))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" "xscmpexpqp %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -5315,7 +5315,8 @@ (define_expand "xststdc_" (set (match_operand:SI 0 "register_operand" "=r") (eq:SI (match_dup 3) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)" { operands[3] = gen_reg_rtx (CCFPmode); operands[4] = CONST0_RTX (SImode); @@ -5324,7 +5325,8 @@ (define_expand "xststdc_" (define_expand "isinf2" [(use (match_operand:SI 0 "gpc_reg_operand")) (use (match_operand:IEEE_FP 1 ""))] - "TARGET_HARD_FLOAT && TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)" { int mask = VSX_TEST_DATA_CLASS_POS_INF | VSX_TEST_DATA_CLASS_NEG_INF; emit_insn (gen_xststdc_ (operands[0], operands[1], GEN_INT (mask))); @@ -5343,7 +5345,7 @@ (define_expand "xststdcnegqp_" (set (match_operand:SI 0 "register_operand" "=r") (lt:SI (match_dup 2) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_FLOAT128_HW" { operands[2] = gen_reg_rtx (CCFPmode); }) @@ -5374,7 +5376,8 @@ (define_insn "*xststdc_" (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_STSTDC) (const_int 0)))] - "TARGET_P9_VECTOR" + "TARGET_P9_VECTOR + && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)" "xststdcp %0,%1,%2" [(set_attr "type" "fpcompare")]) diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c index d376a3ca68e..f48aa089b05 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c @@ -1,6 +1,5 @@ /* { dg-do run } */ -/* { dg-require-effective-target ppc_float128_sw } */ -/* { dg-require-effective-target p9vector_hw } */ +/* { dg-require-effective-target ppc_float128_hw } */ /* { dg-options "-O2 -mdejagnu-cpu=power9 " } */ #define NAN_Q __builtin_nanq ("")