From patchwork Sat Jul 13 15:15:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1960180 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WLsVR697Rz1xr4 for ; Sun, 14 Jul 2024 01:15:59 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 169163861025 for ; Sat, 13 Jul 2024 15:15:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 6EBF2385DDCC for ; Sat, 13 Jul 2024 15:15:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6EBF2385DDCC Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 6EBF2385DDCC Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720883737; cv=none; b=HCJY/iOOgymn+Kc3gApEb0PnZP+duebEt67AwFOQxrSqsiaPYnDQLFTffFQGo/WxBBGG090H22f6J7tBvwJOOJgxO4Dcmn2GAtu5Juzq7q23dZsU5oZ8V9BsURXn1ZPcwlYp/K0D43XRR8cqStb1kKEJdCSGOmb1M0HVEfFNrXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720883737; c=relaxed/simple; bh=SWILdUT4K9SYhPiPv9sDABDVWbAjboxSaaYN1R2Gp0Q=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=xknuLDC5BIjrATt/PJwNv8JOpFaXonYZ04vIfTv2oiIsQcN7/xwuq3k+Z+Tank0m/n06wTm80bkwPjdRisXpw4gVDQsiKWw1eU4cHFrHOILdgI4TagAfkxNe7HO5YlUc3tarJFHkiM8FuCQESwoXtVbdlbX1fq49wzkmtOBOkzE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 632831007 for ; Sat, 13 Jul 2024 08:15:59 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BDDAA3F762 for ; Sat, 13 Jul 2024 08:15:33 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [PATCH] recog: restrict paradoxical mode punning in insn_propagation [PR115901] Date: Sat, 13 Jul 2024 16:15:32 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) MIME-Version: 1.0 X-Spam-Status: No, score=-19.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org In g:44fc801e97a8dc626a4806ff4124439003420b20 I'd extended insn_propagation to handle simple cases of hard-reg mode punning. One of the checks was that the new use mode occupied the same number of registers as the original definition mode. However, as PR115901 shows, we need to avoid increasing the size of any registers in the punned "to" expression as well. Specifically, the test includes a DImode move from GPR x0 to a vector register, followed by a V2DI use of the vector register. The simplification would then create a V2DI spanning x0 and x1, manufacturing a new, unwanted use of x1. Checking for that kind of thing directly seems too cumbersome, and is not related to the original motivation (which was to improve handling of shared vector zeros on aarch64). This patch therefore restricts the paradoxical case to constants. Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install? Richard gcc/ PR rtl-optimization/115901 * recog.cc (insn_propagation::apply_to_rvalue_1): Restrict paradoxical mode punning to cases where "to" is constant. gcc/testsuite/ PR rtl-optimization/115901 * gcc.dg/torture/pr115901.c: New test. --- gcc/recog.cc | 8 ++++++++ gcc/testsuite/gcc.dg/torture/pr115901.c | 14 ++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/torture/pr115901.c diff --git a/gcc/recog.cc b/gcc/recog.cc index 7710c55b745..54b317126c2 100644 --- a/gcc/recog.cc +++ b/gcc/recog.cc @@ -1082,6 +1082,14 @@ insn_propagation::apply_to_rvalue_1 (rtx *loc) || !REG_CAN_CHANGE_MODE_P (REGNO (x), GET_MODE (from), GET_MODE (x))) return false; + /* If the reference is paradoxical and the replacement + value contains registers, we would need to check that the + simplification below does not increase REG_NREGS for those + registers either. It seems simpler to punt on nonconstant + values instead. */ + if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (from)) + && !CONSTANT_P (to)) + return false; newval = simplify_subreg (GET_MODE (x), to, GET_MODE (from), subreg_lowpart_offset (GET_MODE (x), GET_MODE (from))); diff --git a/gcc/testsuite/gcc.dg/torture/pr115901.c b/gcc/testsuite/gcc.dg/torture/pr115901.c new file mode 100644 index 00000000000..244af857d88 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr115901.c @@ -0,0 +1,14 @@ +/* { dg-additional-options "-ftrivial-auto-var-init=zero" } */ + +int p; +void g(long); +#define vec16 __attribute__((vector_size(16))) + +void l(vec16 long *); +void h() +{ + long inv1; + vec16 long inv = {p, inv1}; + g (p); + l(&inv); +}