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Thu, 11 Jul 2024 10:48:06 -0700 From: Liming Sun To: Subject: [PATCH v1 1/1] UBUNTU: SAUCE: [SRU][J:linux-bluefield] mmc:sdhci-of-dwcmshc: Add hw_reset() support for BlueField-3 SoC Date: Thu, 11 Jul 2024 13:48:05 -0400 Message-ID: <8b17c2f11409a4c53b604a01528bec3686952196.1720719340.git.limings@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|SJ0PR12MB6903:EE_ X-MS-Office365-Filtering-Correlation-Id: 043fd2e5-27ff-456d-a076-08dca1d1a89e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: bNkkKCpiftIHSQIS+ETu7XuoJAGv8RM5s9/axU29ZyrxzYhoyWQDPYzc6z/gdOdk1ibU9rl3M7r3HWidnawWOh/3SiEHkSasZv+NVhCjZo+r9OBpgdJ8nh3vPxFMprF9fYnsFha1Mnji57wcsRLFEBsWdzaN+tNFOwhQwse2JdDLEhf8KS0iNXEnGpfS6HCjZl8aXFa4yk3EhcaITJEq/WibcLEaFMfUEqHslMlMv3EMT83L740n8yEHPt7NLxFYyP820tNXEk+UqJULobH5Osc9PvZH0gSFmXki99APRRbbHlxcBkDgb2/iW5S0rIHBKmoshuqcCC4UppjCZHFn48Ul/Up+NHjkR4aUJeUtzYngfx3jms/oexNjJXCFl/elUczbsG3HkpB07JBd9LrSil3pvz4Cm0NyPpYu4WwTJEafPbXjLFAmQT4Dt5fsw2uvqwJ3ExbRc/c/aXOFZRar8Btd0Aibd746FtoQdqN536cSRpeH63YS7Z99uwFzh9sgjJJKdr+hQaCmgl7EhEY/5lDuXRxl7QdKKHwVKBqOfWRsDhcM8YUGgrzqyaVzL8fy6veh+zlxAU9qVirHJgwsKdEIJQe2HccCwdKnZNUiKVHIhT2qk8TryKv8xnGGZBTj9N8YZX1C1Xpx2PFvcpARgvpmnUOAFpNcJL9U3cIKx7S+Tdc4w5zJV5AvVuE9rEVjXywsequQmvyMBBItJwQs7/aGQ7HHyzN78X6EnK0W1G78H6JmSTwDmvKso8ybFfXWma3jwkkBFgFFKySHDG2b4tm2eFc8gKbYGdssoeuKYhXQD4diIvuVP/zGzUAJ7AI0yyuiw3Tflue+fnmuJAtFos+CprJ4K2TFQn9nfg45DTBlx/tV0MxrA3K/RWyLrGMFm+eUKNzXtSsQSZYYC67eHaQbdTLXdrwHkWWPNBtW05lri/Xenvos/IdEkLMRDhDyfkhuup5DCc+YMMFfoHjlB0C9l+iEF6NSExV9AU9dKIWONITbYa/8NFddURbQVpbongqfzu+0OHtGimphbI8WMSDlX6bKj6Vq7biET9vvuI9Ha/ndxGi+2h67hO+T/h90OgNf7xKHuolMdN5VlBXmLrEhDrxCRCwzJGBDjx8o5mWbdTZz6f/jAX3DKI6cHhzo/rZUfDBJ6n7UomMKesqb7z78uOr000PQbBtH2HspMYrFRdxCT9T4uh+4CpdemoRrxLJoYkAuau5X30isYNgg6cqI6wbndSBCXonoOe9uN/Rgkuo+jb1EESUGOaz/4SwnNDBKUL/RwDokjplDM02B7cwH9+zmTvJRyFz7+qF0hjjoL6Vtj9JUxR/Ni1S/kWHJ5OhPGIfTVSmDvrpnLo+Ay4xwt+U7YabTWno0hCgivHvO2XGsH9szOyROkWvcniJkKsqK2Sncy2EjeD0VZSmFjl0KWWtJvGg2guGXFaBGD4ldtdRo8cD6m6rqqSzyp5pH X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2024 17:48:22.7253 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 043fd2e5-27ff-456d-a076-08dca1d1a89e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003448.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6903 Received-SPF: softfail client-ip=40.107.236.77; envelope-from=limings@nvidia.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.20 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: "kernel-team" BugLink: https://bugs.launchpad.net/bugs/2072786 The eMMC RST_N register is implemented as secure register on the BlueField-3 SoC and controlled by TF-A. This commit adds the hw_reset() support which sends an SMC call to TF-A for the eMMC HW reset. Reviewed-by: David Thompson Signed-off-by: Liming Sun --- drivers/mmc/host/sdhci-of-dwcmshc.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 4d19d4ec01f8..23c7f5d28837 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -22,6 +23,9 @@ #include "sdhci-pltfm.h" +/* SMC call for RST_N */ +#define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 + #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) /* DWCMSHC specific Mode Select value */ @@ -274,6 +278,18 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +#ifdef CONFIG_ACPI +static void dwcmshc_bf3_hw_reset(struct sdhci_host *host) +{ + struct arm_smccc_res res = { 0 }; + + arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res); + + if (res.a0) + pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); +} +#endif + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -299,8 +315,18 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { }; #ifdef CONFIG_ACPI +static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, + .get_max_clock = dwcmshc_get_max_clock, + .reset = sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + .hw_reset = dwcmshc_bf3_hw_reset, +}; + static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { - .ops = &sdhci_dwcmshc_ops, + .ops = &sdhci_dwcmshc_bf3_ops, .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |