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(aarch64_override_options_internal): Remove dead assignment. diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 7f0cc47d0f071de9297068baa85c6d5fc4d7fa5b..2a67383bf9d21631664aba82e753120a0173efcf 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -349,9 +349,6 @@ static bool aarch64_print_address_internal (FILE*, machine_mode, rtx, /* The processor for which instructions should be scheduled. */ enum aarch64_processor aarch64_tune = cortexa53; -/* Mask to specify which instruction scheduling options should be used. */ -uint64_t aarch64_tune_flags = 0; - /* Global flag for PC relative loads. */ bool aarch64_pcrelative_literal_loads; @@ -18273,7 +18270,6 @@ void aarch64_override_options_internal (struct gcc_options *opts) { const struct processor *tune = aarch64_get_tune_cpu (opts->x_selected_tune); - aarch64_tune_flags = tune->flags; aarch64_tune = tune->sched_core; /* Make a copy of the tuning parameters attached to the core, which we may later overwrite. */ From patchwork Thu Jul 11 12:12:11 2024 Content-Type: text/plain; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(35042699022)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2024 12:12:24.3906 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e3db815-c09d-4926-2977-08dca1a2b940 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000198.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS1PR08MB7562 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org AARCH64_NUM_ISA_MODES will be used within aarch64-opts.h in a later commit. gcc/ChangeLog: * config/aarch64/aarch64.h (DEF_AARCH64_ISA_MODE): Move to... * config/aarch64/aarch64-opts.h (DEF_AARCH64_ISA_MODE): ...here. diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index a05c0d3ded1c69802f15eebb8c150c7dcc62b4ef..06a4fed3833482543891b4f7c778933f7cebd631 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -24,6 +24,11 @@ #ifndef USED_FOR_TARGET typedef uint64_t aarch64_feature_flags; + +constexpr unsigned int AARCH64_NUM_ISA_MODES = (0 +#define DEF_AARCH64_ISA_MODE(IDENT) + 1 +#include "aarch64-isa-modes.def" +); #endif /* The various cores that implement AArch64. */ diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index fac1882bcb38eae3690c2dc366ebc6c3f64ee940..2be6dc4089b81d2a4e1ba6861b25094774198406 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -183,11 +183,6 @@ enum class aarch64_feature : unsigned char { constexpr auto AARCH64_FL_SM_STATE = AARCH64_FL_SM_ON | AARCH64_FL_SM_OFF; -constexpr unsigned int AARCH64_NUM_ISA_MODES = (0 -#define DEF_AARCH64_ISA_MODE(IDENT) + 1 -#include "aarch64-isa-modes.def" -); - /* The mask of all ISA modes. */ constexpr auto AARCH64_FL_ISA_MODES = (aarch64_feature_flags (1) << AARCH64_NUM_ISA_MODES) - 1; From patchwork Thu Jul 11 12:12:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 1959298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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#endif - auto isa_mode = AARCH64_FL_DEFAULT_ISA_MODE; if (cpu && arch) { /* If both -mcpu and -march are specified, warn if they are not @@ -18879,25 +18878,25 @@ aarch64_override_options (void) } selected_arch = arch->arch; - aarch64_set_asm_isa_flags (arch_isa | isa_mode); + aarch64_set_asm_isa_flags (arch_isa | AARCH64_FL_DEFAULT_ISA_MODE); } else if (cpu) { selected_arch = cpu->arch; - aarch64_set_asm_isa_flags (cpu_isa | isa_mode); + aarch64_set_asm_isa_flags (cpu_isa | AARCH64_FL_DEFAULT_ISA_MODE); } else if (arch) { cpu = &all_cores[arch->ident]; selected_arch = arch->arch; - aarch64_set_asm_isa_flags (arch_isa | isa_mode); + aarch64_set_asm_isa_flags (arch_isa | AARCH64_FL_DEFAULT_ISA_MODE); } else { /* No -mcpu or -march specified, so use the default CPU. */ cpu = &all_cores[TARGET_CPU_DEFAULT]; selected_arch = cpu->arch; - aarch64_set_asm_isa_flags (cpu->flags | isa_mode); + aarch64_set_asm_isa_flags (cpu->flags | AARCH64_FL_DEFAULT_ISA_MODE); } selected_tune = tune ? tune->ident : cpu->ident; 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Using a separate data type for these value makes it more clear that they're not expected or required to have any of their upper feature bits set. It will also make things simpler and more efficient when we extend aarch64_feature_flags to 128 bits. This patch uses explicit casts whenever converting from an aarch64_feature_flags value to an aarch64_isa_mode value. This isn't strictly necessary, but serves to highlight the locations where an explicit conversion will become necessary later. gcc/ChangeLog: * config/aarch64/aarch64-opts.h: Add aarch64_isa_mode typedef. * config/aarch64/aarch64-protos.h (aarch64_gen_callee_cookie): Use aarch64_isa_mode parameter. (aarch64_sme_vq_immediate): Ditto. * config/aarch64/aarch64.cc (aarch64_fntype_pstate_sm): Use aarch64_isa_mode values. (aarch64_fntype_pstate_za): Ditto. (aarch64_fndecl_pstate_sm): Ditto. (aarch64_fndecl_pstate_za): Ditto. (aarch64_fndecl_isa_mode): Ditto. (aarch64_cfun_incoming_pstate_sm): Ditto. (aarch64_cfun_enables_pstate_sm): Ditto. (aarch64_call_switches_pstate_sm): Ditto. (aarch64_gen_callee_cookie): Ditto. (aarch64_callee_isa_mode): Ditto. (aarch64_insn_callee_abi): Ditto. (aarch64_sme_vq_immediate): Ditto. (aarch64_add_offset_temporaries): Ditto. (aarch64_add_offset): Ditto. (aarch64_add_sp): Ditto. (aarch64_sub_sp): Ditto. (aarch64_guard_switch_pstate_sm): Ditto. (aarch64_switch_pstate_sm): Ditto. (aarch64_init_cumulative_args): Ditto. (aarch64_allocate_and_probe_stack_space): Ditto. (aarch64_expand_prologue): Ditto. (aarch64_expand_epilogue): Ditto. (aarch64_start_call_args): Ditto. (aarch64_expand_call): Ditto. (aarch64_end_call_args): Ditto. (aarch64_set_current_function): Ditto, with added conversions. (aarch64_handle_attr_arch): Avoid macro with changed type. (aarch64_handle_attr_cpu): Ditto. (aarch64_handle_attr_isa_flags): Ditto. (aarch64_switch_pstate_sm_for_landing_pad): Use arch64_isa_mode values. (aarch64_switch_pstate_sm_for_jump): Ditto. (pass_switch_pstate_sm::gate): Ditto. * config/aarch64/aarch64.h (AARCH64_ISA_MODE_{SM_ON|SM_OFF|ZA_ON}): New macros. (AARCH64_FL_SM_STATE): Mark as possibly unused. (AARCH64_ISA_MODE_SM_STATE): New aarch64_isa_mode mask. (AARCH64_DEFAULT_ISA_MODE): New aarch64_isa_mode value. (AARCH64_FL_DEFAULT_ISA_MODE): Define using above value. (AARCH64_ISA_MODE): Change type to aarch64_isa_mode. (arm_pcs): Use aarch64_isa_mode value. diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index 06a4fed3833482543891b4f7c778933f7cebd631..2c36bfaad19b999238601d44709c280ef987046b 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -23,6 +23,8 @@ #define GCC_AARCH64_OPTS_H #ifndef USED_FOR_TARGET +typedef uint64_t aarch64_isa_mode; + typedef uint64_t aarch64_feature_flags; constexpr unsigned int AARCH64_NUM_ISA_MODES = (0 diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 42639e9efcf1e0f9362f759ae63a31b8eeb0d581..f64afe2889018e1c4735a1677e6bf5febc4a7665 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -767,7 +767,7 @@ bool aarch64_constant_address_p (rtx); bool aarch64_emit_approx_div (rtx, rtx, rtx); bool aarch64_emit_approx_sqrt (rtx, rtx, bool); tree aarch64_vector_load_decl (tree); -rtx aarch64_gen_callee_cookie (aarch64_feature_flags, arm_pcs); +rtx aarch64_gen_callee_cookie (aarch64_isa_mode, arm_pcs); void aarch64_expand_call (rtx, rtx, rtx, bool); bool aarch64_expand_cpymem_mops (rtx *, bool); bool aarch64_expand_cpymem (rtx *, bool); @@ -808,7 +808,7 @@ int aarch64_add_offset_temporaries (rtx); void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx); bool aarch64_rdsvl_immediate_p (const_rtx); rtx aarch64_sme_vq_immediate (machine_mode mode, HOST_WIDE_INT, - aarch64_feature_flags); + aarch64_isa_mode); char *aarch64_output_rdsvl (const_rtx); bool aarch64_addsvl_addspl_immediate_p (const_rtx); char *aarch64_output_addsvl_addspl (rtx); diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 2be6dc4089b81d2a4e1ba6861b25094774198406..dfb244307635a7aa1c552acd55a635cd0bdeeb39 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -181,7 +181,17 @@ enum class aarch64_feature : unsigned char { #include "aarch64-arches.def" #undef HANDLE -constexpr auto AARCH64_FL_SM_STATE = AARCH64_FL_SM_ON | AARCH64_FL_SM_OFF; +/* Define aarch64_isa_mode masks. */ +#define DEF_AARCH64_ISA_MODE(IDENT) \ + constexpr auto AARCH64_ISA_MODE_##IDENT ATTRIBUTE_UNUSED \ + = aarch64_isa_mode (1) << int (aarch64_feature::IDENT); +#include "aarch64-isa-modes.def" +#undef HANDLE + +constexpr auto AARCH64_FL_SM_STATE ATTRIBUTE_UNUSED + = AARCH64_FL_SM_ON | AARCH64_FL_SM_OFF; +constexpr auto AARCH64_ISA_MODE_SM_STATE ATTRIBUTE_UNUSED + = AARCH64_ISA_MODE_SM_ON | AARCH64_ISA_MODE_SM_OFF; /* The mask of all ISA modes. */ constexpr auto AARCH64_FL_ISA_MODES @@ -189,7 +199,10 @@ constexpr auto AARCH64_FL_ISA_MODES /* The default ISA mode, for functions with no attributes that specify something to the contrary. */ -constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; +constexpr auto AARCH64_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED + = AARCH64_ISA_MODE_SM_OFF; +constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED + = aarch64_feature_flags (AARCH64_DEFAULT_ISA_MODE); #endif @@ -202,7 +215,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE = AARCH64_FL_SM_OFF; #define AARCH64_ISA_SM_OFF (aarch64_isa_flags & AARCH64_FL_SM_OFF) #define AARCH64_ISA_SM_ON (aarch64_isa_flags & AARCH64_FL_SM_ON) #define AARCH64_ISA_ZA_ON (aarch64_isa_flags & AARCH64_FL_ZA_ON) -#define AARCH64_ISA_MODE (aarch64_isa_flags & AARCH64_FL_ISA_MODES) +#define AARCH64_ISA_MODE (aarch64_isa_mode) (aarch64_isa_flags & AARCH64_FL_ISA_MODES) #define AARCH64_ISA_V8A (aarch64_isa_flags & AARCH64_FL_V8A) #define AARCH64_ISA_V8_1A (aarch64_isa_flags & AARCH64_FL_V8_1A) #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) @@ -1131,7 +1144,7 @@ enum arm_pcs typedef struct { enum arm_pcs pcs_variant; - aarch64_feature_flags isa_mode; + aarch64_isa_mode isa_mode; int aapcs_arg_processed; /* No need to lay out this argument again. */ int aapcs_ncrn; /* Next Core register number. */ int aapcs_nextncrn; /* Next next core register number. */ diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 67c97569b7d4b5502e8dfc111eced65d2aee5cb2..726f769e708d09285a291472bda4babcc3241d00 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -2166,17 +2166,17 @@ aarch64_fntype_abi (const_tree fntype) /* Return the state of PSTATE.SM on entry to functions of type FNTYPE. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_fntype_pstate_sm (const_tree fntype) { if (lookup_attribute ("arm", "streaming", TYPE_ATTRIBUTES (fntype))) - return AARCH64_FL_SM_ON; + return AARCH64_ISA_MODE_SM_ON; if (lookup_attribute ("arm", "streaming_compatible", TYPE_ATTRIBUTES (fntype))) return 0; - return AARCH64_FL_SM_OFF; + return AARCH64_ISA_MODE_SM_OFF; } /* Return state flags that describe whether and how functions of type @@ -2191,19 +2191,19 @@ aarch64_fntype_shared_flags (const_tree fntype, const char *state_name) /* Return the state of PSTATE.ZA on entry to functions of type FNTYPE. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_fntype_pstate_za (const_tree fntype) { if (aarch64_fntype_shared_flags (fntype, "za") || aarch64_fntype_shared_flags (fntype, "zt0")) - return AARCH64_FL_ZA_ON; + return AARCH64_ISA_MODE_ZA_ON; return 0; } /* Return the ISA mode on entry to functions of type FNTYPE. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_fntype_isa_mode (const_tree fntype) { return (aarch64_fntype_pstate_sm (fntype) @@ -2224,11 +2224,11 @@ aarch64_fndecl_is_locally_streaming (const_tree fndecl) function FNDECL. This might be different from the state of PSTATE.SM on entry. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_fndecl_pstate_sm (const_tree fndecl) { if (aarch64_fndecl_is_locally_streaming (fndecl)) - return AARCH64_FL_SM_ON; + return AARCH64_ISA_MODE_SM_ON; return aarch64_fntype_pstate_sm (TREE_TYPE (fndecl)); } @@ -2247,12 +2247,12 @@ aarch64_fndecl_has_state (tree fndecl, const char *state_name) /* Return the state of PSTATE.ZA when compiling the body of function FNDECL. This might be different from the state of PSTATE.ZA on entry. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_fndecl_pstate_za (const_tree fndecl) { if (aarch64_fndecl_has_new_state (fndecl, "za") || aarch64_fndecl_has_new_state (fndecl, "zt0")) - return AARCH64_FL_ZA_ON; + return AARCH64_ISA_MODE_ZA_ON; return aarch64_fntype_pstate_za (TREE_TYPE (fndecl)); } @@ -2260,7 +2260,7 @@ aarch64_fndecl_pstate_za (const_tree fndecl) /* Return the ISA mode that should be used to compile the body of function FNDECL. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_fndecl_isa_mode (const_tree fndecl) { return (aarch64_fndecl_pstate_sm (fndecl) @@ -2271,7 +2271,7 @@ aarch64_fndecl_isa_mode (const_tree fndecl) This might be different from the state of PSTATE.SM in the function body. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_cfun_incoming_pstate_sm () { return aarch64_fntype_pstate_sm (TREE_TYPE (cfun->decl)); @@ -2281,7 +2281,7 @@ aarch64_cfun_incoming_pstate_sm () This might be different from the state of PSTATE.ZA in the function body. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_cfun_incoming_pstate_za () { return aarch64_fntype_pstate_za (TREE_TYPE (cfun->decl)); @@ -2313,7 +2313,7 @@ static bool aarch64_cfun_enables_pstate_sm () { return (aarch64_fndecl_is_locally_streaming (cfun->decl) - && aarch64_cfun_incoming_pstate_sm () != AARCH64_FL_SM_ON); + && aarch64_cfun_incoming_pstate_sm () != AARCH64_ISA_MODE_SM_ON); } /* Return true if the current function has state STATE_NAME, either by @@ -2330,9 +2330,9 @@ aarch64_cfun_has_state (const char *state_name) the BL instruction. */ static bool -aarch64_call_switches_pstate_sm (aarch64_feature_flags callee_mode) +aarch64_call_switches_pstate_sm (aarch64_isa_mode callee_mode) { - return (callee_mode & ~AARCH64_ISA_MODE & AARCH64_FL_SM_STATE) != 0; + return (bool) (callee_mode & ~AARCH64_ISA_MODE & AARCH64_ISA_MODE_SM_STATE); } /* Implement TARGET_COMPATIBLE_VECTOR_TYPES_P. */ @@ -2401,7 +2401,7 @@ aarch64_reg_save_mode (unsigned int regno) return the CONST_INT that should be placed in an UNSPEC_CALLEE_ABI rtx. */ rtx -aarch64_gen_callee_cookie (aarch64_feature_flags isa_mode, arm_pcs pcs_variant) +aarch64_gen_callee_cookie (aarch64_isa_mode isa_mode, arm_pcs pcs_variant) { return gen_int_mode ((unsigned int) isa_mode | (unsigned int) pcs_variant << AARCH64_NUM_ISA_MODES, @@ -2421,10 +2421,10 @@ aarch64_callee_abi (rtx cookie) required ISA mode on entry to the callee, which is also the ISA mode on return from the callee. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_callee_isa_mode (rtx cookie) { - return UINTVAL (cookie) & AARCH64_FL_ISA_MODES; + return UINTVAL (cookie) & ((1 << AARCH64_NUM_ISA_MODES) - 1); } /* INSN is a call instruction. Return the CONST_INT stored in its @@ -2452,7 +2452,7 @@ aarch64_insn_callee_abi (const rtx_insn *insn) /* INSN is a call instruction. Return the required ISA mode on entry to the callee, which is also the ISA mode on return from the callee. */ -static aarch64_feature_flags +static aarch64_isa_mode aarch64_insn_callee_isa_mode (const rtx_insn *insn) { return aarch64_callee_isa_mode (aarch64_insn_callee_cookie (insn)); @@ -3986,10 +3986,10 @@ aarch64_output_sve_vector_inc_dec (const char *operands, rtx x) rtx aarch64_sme_vq_immediate (machine_mode mode, HOST_WIDE_INT factor, - aarch64_feature_flags isa_mode) + aarch64_isa_mode isa_mode) { gcc_assert (aarch64_sve_rdvl_addvl_factor_p (factor)); - if (isa_mode & AARCH64_FL_SM_ON) + if (isa_mode & AARCH64_ISA_MODE_SM_ON) /* We're in streaming mode, so we can use normal poly-int values. */ return gen_int_mode ({ factor, factor }, mode); @@ -4640,7 +4640,7 @@ aarch64_add_offset_temporaries (rtx x) TEMP2, if nonnull, is a second temporary register that doesn't overlap either DEST or REG. - FORCE_ISA_MODE is AARCH64_FL_SM_ON if any variable component of OFFSET + FORCE_ISA_MODE is AARCH64_ISA_MODE_SM_ON if any variable component of OFFSET is measured relative to the SME vector length instead of the current prevailing vector length. It is 0 otherwise. @@ -4652,7 +4652,7 @@ aarch64_add_offset_temporaries (rtx x) static void aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx src, poly_int64 offset, rtx temp1, rtx temp2, - aarch64_feature_flags force_isa_mode, + aarch64_isa_mode force_isa_mode, bool frame_related_p, bool emit_move_imm = true) { gcc_assert (emit_move_imm || temp1 != NULL_RTX); @@ -4673,7 +4673,7 @@ aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx src, offset_rtx = aarch64_sme_vq_immediate (mode, offset.coeffs[0], 0); rtx_insn *insn = emit_insn (gen_add3_insn (dest, src, offset_rtx)); RTX_FRAME_RELATED_P (insn) = frame_related_p; - if (frame_related_p && (force_isa_mode & AARCH64_FL_SM_ON)) + if (frame_related_p && (force_isa_mode & AARCH64_ISA_MODE_SM_ON)) add_reg_note (insn, REG_CFA_ADJUST_CFA, gen_rtx_SET (dest, plus_constant (Pmode, src, offset))); @@ -4701,7 +4701,7 @@ aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx src, { rtx_insn *insn = emit_insn (gen_add3_insn (dest, src, offset_rtx)); RTX_FRAME_RELATED_P (insn) = true; - if (force_isa_mode & AARCH64_FL_SM_ON) + if (force_isa_mode & AARCH64_ISA_MODE_SM_ON) add_reg_note (insn, REG_CFA_ADJUST_CFA, gen_rtx_SET (dest, plus_constant (Pmode, src, poly_offset))); @@ -4735,7 +4735,7 @@ aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx src, rtx val; if (IN_RANGE (rel_factor, -32, 31)) { - if (force_isa_mode & AARCH64_FL_SM_ON) + if (force_isa_mode & AARCH64_ISA_MODE_SM_ON) { /* Try to use an unshifted RDSVL, otherwise fall back on a shifted RDSVL #1. */ @@ -4783,7 +4783,7 @@ aarch64_add_offset (scalar_int_mode mode, rtx dest, rtx src, val = gen_int_mode (poly_int64 (low_bit, low_bit), mode); shift = 0; } - else if ((force_isa_mode & AARCH64_FL_SM_ON) + else if ((force_isa_mode & AARCH64_ISA_MODE_SM_ON) && aarch64_sve_rdvl_addvl_factor_p (low_bit)) { val = aarch64_sme_vq_immediate (mode, low_bit, 0); @@ -4886,7 +4886,7 @@ aarch64_split_add_offset (scalar_int_mode mode, rtx dest, rtx src, static inline void aarch64_add_sp (rtx temp1, rtx temp2, poly_int64 delta, - aarch64_feature_flags force_isa_mode, bool emit_move_imm) + aarch64_isa_mode force_isa_mode, bool emit_move_imm) { aarch64_add_offset (Pmode, stack_pointer_rtx, stack_pointer_rtx, delta, temp1, temp2, force_isa_mode, true, emit_move_imm); @@ -4898,7 +4898,7 @@ aarch64_add_sp (rtx temp1, rtx temp2, poly_int64 delta, static inline void aarch64_sub_sp (rtx temp1, rtx temp2, poly_int64 delta, - aarch64_feature_flags force_isa_mode, + aarch64_isa_mode force_isa_mode, bool frame_related_p, bool emit_move_imm = true) { aarch64_add_offset (Pmode, stack_pointer_rtx, stack_pointer_rtx, -delta, @@ -4915,11 +4915,11 @@ aarch64_sub_sp (rtx temp1, rtx temp2, poly_int64 delta, matches LOCAL_MODE. Return the label that the branch jumps to. */ static rtx_insn * -aarch64_guard_switch_pstate_sm (rtx old_svcr, aarch64_feature_flags local_mode) +aarch64_guard_switch_pstate_sm (rtx old_svcr, aarch64_isa_mode local_mode) { - local_mode &= AARCH64_FL_SM_STATE; + local_mode &= AARCH64_ISA_MODE_SM_STATE; gcc_assert (local_mode != 0); - auto already_ok_cond = (local_mode & AARCH64_FL_SM_ON ? NE : EQ); + auto already_ok_cond = (local_mode & AARCH64_ISA_MODE_SM_ON ? NE : EQ); auto *label = gen_label_rtx (); auto branch = aarch64_gen_test_and_branch (already_ok_cond, old_svcr, 0, label); @@ -4933,15 +4933,14 @@ aarch64_guard_switch_pstate_sm (rtx old_svcr, aarch64_feature_flags local_mode) an SMSTOP SM. */ static void -aarch64_switch_pstate_sm (aarch64_feature_flags old_mode, - aarch64_feature_flags new_mode) +aarch64_switch_pstate_sm (aarch64_isa_mode old_mode, aarch64_isa_mode new_mode) { - old_mode &= AARCH64_FL_SM_STATE; - new_mode &= AARCH64_FL_SM_STATE; + old_mode &= AARCH64_ISA_MODE_SM_STATE; + new_mode &= AARCH64_ISA_MODE_SM_STATE; gcc_assert (old_mode != new_mode); - if ((new_mode & AARCH64_FL_SM_ON) - || (new_mode == 0 && (old_mode & AARCH64_FL_SM_OFF))) + if ((new_mode & AARCH64_ISA_MODE_SM_ON) + || (!new_mode && (old_mode & AARCH64_ISA_MODE_SM_OFF))) emit_insn (gen_aarch64_smstart_sm ()); else emit_insn (gen_aarch64_smstop_sm ()); @@ -7222,7 +7221,7 @@ aarch64_init_cumulative_args (CUMULATIVE_ARGS *pcum, else { pcum->pcs_variant = ARM_PCS_AAPCS64; - pcum->isa_mode = AARCH64_FL_DEFAULT_ISA_MODE; + pcum->isa_mode = AARCH64_DEFAULT_ISA_MODE; } pcum->aapcs_reg = NULL_RTX; pcum->aapcs_arg_processed = false; @@ -9157,14 +9156,14 @@ aarch64_emit_stack_tie (rtx reg) then the signal handler doesn't know the state of the stack and can make no assumptions about which pages have been probed. - FORCE_ISA_MODE is AARCH64_FL_SM_ON if any variable component of POLY_SIZE + FORCE_ISA_MODE is AARCH64_ISA_MODE_SM_ON if any variable component of POLY_SIZE is measured relative to the SME vector length instead of the current prevailing vector length. It is 0 otherwise. */ static void aarch64_allocate_and_probe_stack_space (rtx temp1, rtx temp2, poly_int64 poly_size, - aarch64_feature_flags force_isa_mode, + aarch64_isa_mode force_isa_mode, bool frame_related_p, bool final_adjustment_p) { @@ -9477,7 +9476,7 @@ aarch64_read_old_svcr (unsigned int regno) static rtx_insn * aarch64_guard_switch_pstate_sm (unsigned int regno, - aarch64_feature_flags local_mode) + aarch64_isa_mode local_mode) { rtx old_svcr = aarch64_read_old_svcr (regno); return aarch64_guard_switch_pstate_sm (old_svcr, local_mode); @@ -9578,9 +9577,9 @@ aarch64_expand_prologue (void) unsigned reg2 = frame.wb_push_candidate2; bool emit_frame_chain = frame.emit_frame_chain; rtx_insn *insn; - aarch64_feature_flags force_isa_mode = 0; + aarch64_isa_mode force_isa_mode = 0; if (aarch64_cfun_enables_pstate_sm ()) - force_isa_mode = AARCH64_FL_SM_ON; + force_isa_mode = AARCH64_ISA_MODE_SM_ON; if (flag_stack_clash_protection && known_eq (callee_adjust, 0) @@ -9784,7 +9783,7 @@ aarch64_expand_prologue (void) emit_insn (gen_aarch64_read_svcr (svcr)); emit_move_insn (aarch64_old_svcr_mem (), svcr); guard_label = aarch64_guard_switch_pstate_sm (svcr, - aarch64_isa_flags); + AARCH64_ISA_MODE); } aarch64_sme_mode_switch_regs args_switch; auto &args = crtl->args.info; @@ -9845,9 +9844,9 @@ aarch64_expand_epilogue (rtx_call_insn *sibcall) HOST_WIDE_INT guard_size = 1 << param_stack_clash_protection_guard_size; HOST_WIDE_INT guard_used_by_caller = STACK_CLASH_CALLER_GUARD; - aarch64_feature_flags force_isa_mode = 0; + aarch64_isa_mode force_isa_mode = 0; if (aarch64_cfun_enables_pstate_sm ()) - force_isa_mode = AARCH64_FL_SM_ON; + force_isa_mode = AARCH64_ISA_MODE_SM_ON; /* We can re-use the registers when: @@ -9877,8 +9876,10 @@ aarch64_expand_epilogue (rtx_call_insn *sibcall) { rtx_insn *guard_label = nullptr; if (known_ge (cfun->machine->frame.old_svcr_offset, 0)) - guard_label = aarch64_guard_switch_pstate_sm (IP0_REGNUM, - aarch64_isa_flags); + { + guard_label = aarch64_guard_switch_pstate_sm (IP0_REGNUM, + AARCH64_ISA_MODE); + } aarch64_sme_mode_switch_regs return_switch; if (sibcall) return_switch.add_call_args (sibcall); @@ -11159,7 +11160,7 @@ aarch64_start_call_args (cumulative_args_t ca_v) { CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v); - if (!TARGET_SME && (ca->isa_mode & AARCH64_FL_SM_ON)) + if (!TARGET_SME && (ca->isa_mode & AARCH64_ISA_MODE_SM_ON)) { error ("calling a streaming function requires the ISA extension %qs", "sme"); @@ -11176,20 +11177,20 @@ aarch64_start_call_args (cumulative_args_t ca_v) && !aarch64_cfun_has_state ("zt0")) error ("call to a function that shares %qs state from a function" " that has no %qs state", "zt0", "zt0"); - else if (!TARGET_ZA && (ca->isa_mode & AARCH64_FL_ZA_ON)) + else if (!TARGET_ZA && (ca->isa_mode & AARCH64_ISA_MODE_ZA_ON)) error ("call to a function that shares SME state from a function" " that has no SME state"); /* If this is a call to a private ZA function, emit a marker to indicate where any necessary set-up code could be inserted. The code itself is inserted by the mode-switching pass. */ - if (TARGET_ZA && !(ca->isa_mode & AARCH64_FL_ZA_ON)) + if (TARGET_ZA && !(ca->isa_mode & AARCH64_ISA_MODE_ZA_ON)) emit_insn (gen_aarch64_start_private_za_call ()); /* If this is a call to a shared-ZA function that doesn't share ZT0, save and restore ZT0 around the call. */ if (aarch64_cfun_has_state ("zt0") - && (ca->isa_mode & AARCH64_FL_ZA_ON) + && (ca->isa_mode & AARCH64_ISA_MODE_ZA_ON) && ca->shared_zt0_flags == 0) aarch64_save_zt0 (); } @@ -11232,7 +11233,7 @@ aarch64_expand_call (rtx result, rtx mem, rtx cookie, bool sibcall) auto callee_isa_mode = aarch64_callee_isa_mode (callee_abi); if (aarch64_cfun_has_state ("za") - && (callee_isa_mode & AARCH64_FL_ZA_ON) + && (callee_isa_mode & AARCH64_ISA_MODE_ZA_ON) && !shared_za_flags) { sorry ("call to a function that shares state other than %qs" @@ -11387,7 +11388,7 @@ aarch64_expand_call (rtx result, rtx mem, rtx cookie, bool sibcall) gen_rtx_REG (VNx16BImode, ZA_SAVED_REGNUM)); /* Keep the aarch64_start/end_private_za_call markers live. */ - if (!(callee_isa_mode & AARCH64_FL_ZA_ON)) + if (!(callee_isa_mode & AARCH64_ISA_MODE_ZA_ON)) use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (VNx16BImode, LOWERING_REGNUM)); @@ -11413,13 +11414,13 @@ aarch64_end_call_args (cumulative_args_t ca_v) /* If this is a call to a private ZA function, emit a marker to indicate where any necessary restoration code could be inserted. The code itself is inserted by the mode-switching pass. */ - if (TARGET_ZA && !(ca->isa_mode & AARCH64_FL_ZA_ON)) + if (TARGET_ZA && !(ca->isa_mode & AARCH64_ISA_MODE_ZA_ON)) emit_insn (gen_aarch64_end_private_za_call ()); /* If this is a call to a shared-ZA function that doesn't share ZT0, save and restore ZT0 around the call. */ if (aarch64_cfun_has_state ("zt0") - && (ca->isa_mode & AARCH64_FL_ZA_ON) + && (ca->isa_mode & AARCH64_ISA_MODE_ZA_ON) && ca->shared_zt0_flags == 0) aarch64_restore_zt0 (false); } @@ -19098,7 +19099,7 @@ aarch64_set_current_function (tree fndecl) auto new_isa_mode = (fndecl ? aarch64_fndecl_isa_mode (fndecl) - : AARCH64_FL_DEFAULT_ISA_MODE); + : AARCH64_DEFAULT_ISA_MODE); auto isa_flags = TREE_TARGET_OPTION (new_tree)->x_aarch64_isa_flags; static bool reported_zt0_p; @@ -19120,7 +19121,7 @@ aarch64_set_current_function (tree fndecl) aarch64_pragma_target_parse. */ if (old_tree == new_tree && (!fndecl || aarch64_previous_fndecl) - && (isa_flags & AARCH64_FL_ISA_MODES) == new_isa_mode) + && (aarch64_isa_mode) (isa_flags & AARCH64_FL_ISA_MODES) == new_isa_mode) { gcc_assert (AARCH64_ISA_MODE == new_isa_mode); return; @@ -19135,10 +19136,11 @@ aarch64_set_current_function (tree fndecl) /* The ISA mode can vary based on function type attributes and function declaration attributes. Make sure that the target options correctly reflect these attributes. */ - if ((isa_flags & AARCH64_FL_ISA_MODES) != new_isa_mode) + if ((aarch64_isa_mode) (isa_flags & AARCH64_FL_ISA_MODES) != new_isa_mode) { auto base_flags = (aarch64_asm_isa_flags & ~AARCH64_FL_ISA_MODES); - aarch64_set_asm_isa_flags (base_flags | new_isa_mode); + aarch64_set_asm_isa_flags (base_flags + | (aarch64_feature_flags) new_isa_mode); aarch64_override_options_internal (&global_options); new_tree = build_target_option_node (&global_options, @@ -19203,7 +19205,8 @@ aarch64_handle_attr_arch (const char *str) { gcc_assert (tmp_arch); selected_arch = tmp_arch->arch; - aarch64_set_asm_isa_flags (tmp_flags | AARCH64_ISA_MODE); + aarch64_set_asm_isa_flags (tmp_flags | (aarch64_asm_isa_flags + & AARCH64_FL_ISA_MODES)); return true; } @@ -19244,7 +19247,8 @@ aarch64_handle_attr_cpu (const char *str) gcc_assert (tmp_cpu); selected_tune = tmp_cpu->ident; selected_arch = tmp_cpu->arch; - aarch64_set_asm_isa_flags (tmp_flags | AARCH64_ISA_MODE); + aarch64_set_asm_isa_flags (tmp_flags | (aarch64_asm_isa_flags + & AARCH64_FL_ISA_MODES)); return true; } @@ -19322,7 +19326,7 @@ aarch64_handle_attr_isa_flags (char *str) features if the user wants to handpick specific features. */ if (strncmp ("+nothing", str, 8) == 0) { - isa_flags = AARCH64_ISA_MODE; + isa_flags &= AARCH64_FL_ISA_MODES; str += 8; } @@ -30036,11 +30040,11 @@ aarch64_switch_pstate_sm_for_landing_pad (basic_block bb) rtx_insn *guard_label = nullptr; if (TARGET_STREAMING_COMPATIBLE) guard_label = aarch64_guard_switch_pstate_sm (IP0_REGNUM, - AARCH64_FL_SM_OFF); + AARCH64_ISA_MODE_SM_OFF); aarch64_sme_mode_switch_regs args_switch; args_switch.add_call_preserved_regs (df_get_live_in (bb)); args_switch.emit_prologue (); - aarch64_switch_pstate_sm (AARCH64_FL_SM_OFF, AARCH64_FL_SM_ON); + aarch64_switch_pstate_sm (AARCH64_ISA_MODE_SM_OFF, AARCH64_ISA_MODE_SM_ON); args_switch.emit_epilogue (); if (guard_label) emit_label (guard_label); @@ -30064,8 +30068,8 @@ aarch64_switch_pstate_sm_for_jump (rtx_insn *jump) rtx_insn *guard_label = nullptr; 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Use a macro to avoid doing this manually in more than one location. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_handle_option): Use new macro. * config/aarch64/aarch64.cc (aarch64_override_options_internal): Ditto. (aarch64_option_print): Ditto. (aarch64_set_current_function): Ditto. (aarch64_can_inline_p): Ditto. (aarch64_declare_function_name): Ditto. (aarch64_start_file): Ditto. * config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): New (aarch64_get_isa_flags): New. (aarch64_asm_isa_flags): Use new macro. (aarch64_isa_flags): Ditto. diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc index 951d041d3109b935e90a7cb5d714940414e81761..63c50189a09d5c7c713f57e23a8172f44bf6bec5 100644 --- a/gcc/common/config/aarch64/aarch64-common.cc +++ b/gcc/common/config/aarch64/aarch64-common.cc @@ -111,7 +111,7 @@ aarch64_handle_option (struct gcc_options *opts, case OPT_mgeneral_regs_only: opts->x_target_flags |= MASK_GENERAL_REGS_ONLY; - aarch64_set_asm_isa_flags (opts, opts->x_aarch64_asm_isa_flags); + aarch64_set_asm_isa_flags (opts, aarch64_get_asm_isa_flags (opts)); return true; case OPT_mfix_cortex_a53_835769: diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index dfb244307635a7aa1c552acd55a635cd0bdeeb39..193f2486176b6bac372a143e2f52041c5a28ebaf 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -22,15 +22,18 @@ #ifndef GCC_AARCH64_H #define GCC_AARCH64_H +#define aarch64_get_asm_isa_flags(opts) \ + (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags)) +#define aarch64_get_isa_flags(opts) \ + (aarch64_feature_flags ((opts)->x_aarch64_isa_flags)) + /* Make these flags read-only so that all uses go via aarch64_set_asm_isa_flags. */ #ifndef GENERATOR_FILE #undef aarch64_asm_isa_flags -#define aarch64_asm_isa_flags \ - ((aarch64_feature_flags) global_options.x_aarch64_asm_isa_flags) +#define aarch64_asm_isa_flags (aarch64_get_asm_isa_flags (&global_options)) #undef aarch64_isa_flags -#define aarch64_isa_flags \ - ((aarch64_feature_flags) global_options.x_aarch64_isa_flags) +#define aarch64_isa_flags (aarch64_get_isa_flags (&global_options)) #endif /* Target CPU builtins. */ diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 726f769e708d09285a291472bda4babcc3241d00..69f481ecfc848e6c5b61516c2f7b8bff5cd4f8b8 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -18331,10 +18331,11 @@ aarch64_override_options_internal (struct gcc_options *opts) && !fixed_regs[R18_REGNUM]) error ("%<-fsanitize=shadow-call-stack%> requires %<-ffixed-x18%>"); - if ((opts->x_aarch64_isa_flags & (AARCH64_FL_SM_ON | AARCH64_FL_ZA_ON)) - && !(opts->x_aarch64_isa_flags & AARCH64_FL_SME)) + aarch64_feature_flags isa_flags = aarch64_get_isa_flags (opts); + if ((isa_flags & (AARCH64_FL_SM_ON | AARCH64_FL_ZA_ON)) + && !(isa_flags & AARCH64_FL_SME)) { - if (opts->x_aarch64_isa_flags & AARCH64_FL_SM_ON) + if (isa_flags & AARCH64_FL_SM_ON) error ("streaming functions require the ISA extension %qs", "sme"); else error ("functions with SME state require the ISA extension %qs", @@ -18343,8 +18344,7 @@ aarch64_override_options_internal (struct gcc_options *opts) " option %<-march%>, or by using the %" " attribute or pragma", "sme"); opts->x_target_flags &= ~MASK_GENERAL_REGS_ONLY; - auto new_flags = (opts->x_aarch64_asm_isa_flags - | feature_deps::SME ().enable); + auto new_flags = isa_flags | feature_deps::SME ().enable; aarch64_set_asm_isa_flags (opts, new_flags); } @@ -19038,9 +19038,9 @@ aarch64_option_print (FILE *file, int indent, struct cl_target_option *ptr) const struct processor *cpu = aarch64_get_tune_cpu (ptr->x_selected_tune); const struct processor *arch = aarch64_get_arch (ptr->x_selected_arch); + aarch64_feature_flags isa_flags = aarch64_get_asm_isa_flags(ptr); std::string extension - = aarch64_get_extension_string_for_isa_flags (ptr->x_aarch64_asm_isa_flags, - arch->flags); + = aarch64_get_extension_string_for_isa_flags (isa_flags, arch->flags); fprintf (file, "%*sselected tune = %s\n", indent, "", cpu->name); fprintf (file, "%*sselected arch = %s%s\n", indent, "", @@ -19100,7 +19100,7 @@ aarch64_set_current_function (tree fndecl) auto new_isa_mode = (fndecl ? aarch64_fndecl_isa_mode (fndecl) : AARCH64_DEFAULT_ISA_MODE); - auto isa_flags = TREE_TARGET_OPTION (new_tree)->x_aarch64_isa_flags; + auto isa_flags = aarch64_get_isa_flags (TREE_TARGET_OPTION (new_tree)); static bool reported_zt0_p; if (!reported_zt0_p @@ -20701,16 +20701,16 @@ aarch64_can_inline_p (tree caller, tree callee) : target_option_default_node); /* Callee's ISA flags should be a subset of the caller's. */ - auto caller_asm_isa = (caller_opts->x_aarch64_asm_isa_flags + auto caller_asm_isa = (aarch64_get_asm_isa_flags (caller_opts) & ~AARCH64_FL_ISA_MODES); - auto callee_asm_isa = (callee_opts->x_aarch64_asm_isa_flags + auto callee_asm_isa = (aarch64_get_asm_isa_flags (callee_opts) & ~AARCH64_FL_ISA_MODES); if (callee_asm_isa & ~caller_asm_isa) return false; - auto caller_isa = (caller_opts->x_aarch64_isa_flags + auto caller_isa = (aarch64_get_isa_flags (caller_opts) & ~AARCH64_FL_ISA_MODES); - auto callee_isa = (callee_opts->x_aarch64_isa_flags + auto callee_isa = (aarch64_get_isa_flags (callee_opts) & ~AARCH64_FL_ISA_MODES); if (callee_isa & ~caller_isa) return false; @@ -20730,8 +20730,8 @@ aarch64_can_inline_p (tree caller, tree callee) PSTATE.SM mode. Otherwise the caller and callee must agree on PSTATE.SM mode, unless we can prove that the callee is naturally streaming-compatible. */ - auto caller_sm = (caller_opts->x_aarch64_isa_flags & AARCH64_FL_SM_STATE); - auto callee_sm = (callee_opts->x_aarch64_isa_flags & AARCH64_FL_SM_STATE); + auto caller_sm = (aarch64_get_isa_flags (caller_opts) & AARCH64_FL_SM_STATE); + auto callee_sm = (aarch64_get_isa_flags (callee_opts) & AARCH64_FL_SM_STATE); if (callee_sm && caller_sm != callee_sm && callee_has_property (AARCH64_IPA_SM_FIXED)) @@ -20744,8 +20744,8 @@ aarch64_can_inline_p (tree caller, tree callee) The only other problematic case for ZA is inlining a function that directly clobbers ZA or ZT0 into a function that has ZA or ZT0 state. */ - auto caller_za = (caller_opts->x_aarch64_isa_flags & AARCH64_FL_ZA_ON); - auto callee_za = (callee_opts->x_aarch64_isa_flags & AARCH64_FL_ZA_ON); + auto caller_za = (aarch64_get_isa_flags (caller_opts) & AARCH64_FL_ZA_ON); + auto callee_za = (aarch64_get_isa_flags (callee_opts) & AARCH64_FL_ZA_ON); if (!caller_za && callee_za) return false; if (!callee_za @@ -24480,7 +24480,7 @@ aarch64_declare_function_name (FILE *stream, const char* name, const struct processor *this_arch = aarch64_get_arch (targ_options->x_selected_arch); - auto isa_flags = targ_options->x_aarch64_asm_isa_flags; + auto isa_flags = aarch64_get_asm_isa_flags (targ_options); std::string extension = aarch64_get_extension_string_for_isa_flags (isa_flags, this_arch->flags); @@ -24610,7 +24610,7 @@ aarch64_start_file (void) const struct processor *default_arch = aarch64_get_arch (default_options->x_selected_arch); - auto default_isa_flags = default_options->x_aarch64_asm_isa_flags; + auto default_isa_flags = aarch64_get_asm_isa_flags (default_options); std::string extension = aarch64_get_extension_string_for_isa_flags (default_isa_flags, default_arch->flags); From patchwork Thu Jul 11 12:14:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 1959296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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The unrecognised aarch64_feature_flags type is handled as a uint64_t, which happens to be correct for now. However, that assumption will change when we extend the mask to 128 bits. This patch changes the option members to use uint64_t types, and adds a "_0" suffix to the names (both for future extensibility, and to allow the original name to be used for the full aarch64_feature_flags mask within generator files). gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_set_asm_isa_flags): Reorder, and add suffix to names. * config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): Add "_0" suffix. (aarch64_get_isa_flags): Ditto. (aarch64_asm_isa_flags): Redefine using renamed uint64_t value. (aarch64_isa_flags): Ditto. * config/aarch64/aarch64.opt: (aarch64_asm_isa_flags): Rename to... (aarch64_asm_isa_flags_0): ...this, and change to uint64_t. (aarch64_isa_flags): Rename to... (aarch64_isa_flags_0): ...this, and change to uint64_t. diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc index 63c50189a09d5c7c713f57e23a8172f44bf6bec5..bd0770dd0d84005701afed35d4af356380a405e9 100644 --- a/gcc/common/config/aarch64/aarch64-common.cc +++ b/gcc/common/config/aarch64/aarch64-common.cc @@ -66,15 +66,16 @@ static const struct default_options aarch_option_optimization_table[] = { OPT_LEVELS_NONE, 0, NULL, 0 } }; -/* Set OPTS->x_aarch64_asm_isa_flags to FLAGS and update - OPTS->x_aarch64_isa_flags accordingly. */ + +/* Set OPTS->x_aarch64_asm_isa_flags_0 to FLAGS and update + OPTS->x_aarch64_isa_flags_0 accordingly. */ void aarch64_set_asm_isa_flags (gcc_options *opts, aarch64_feature_flags flags) { - opts->x_aarch64_asm_isa_flags = flags; - opts->x_aarch64_isa_flags = flags; + opts->x_aarch64_asm_isa_flags_0 = flags; if (opts->x_target_flags & MASK_GENERAL_REGS_ONLY) - opts->x_aarch64_isa_flags &= ~feature_deps::get_flags_off (AARCH64_FL_FP); + flags &= ~feature_deps::get_flags_off (AARCH64_FL_FP); + opts->x_aarch64_isa_flags_0 = flags; } /* Implement TARGET_HANDLE_OPTION. diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 193f2486176b6bac372a143e2f52041c5a28ebaf..903e708565dc7830e9544813dd315f99d489cad2 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -23,13 +23,18 @@ #define GCC_AARCH64_H #define aarch64_get_asm_isa_flags(opts) \ - (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags)) + (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags_0)) #define aarch64_get_isa_flags(opts) \ - (aarch64_feature_flags ((opts)->x_aarch64_isa_flags)) + (aarch64_feature_flags ((opts)->x_aarch64_isa_flags_0)) /* Make these flags read-only so that all uses go via aarch64_set_asm_isa_flags. */ -#ifndef GENERATOR_FILE +#ifdef GENERATOR_FILE +#undef aarch64_asm_isa_flags +#define aarch64_asm_isa_flags (aarch64_feature_flags (aarch64_asm_isa_flags_0)) +#undef aarch64_isa_flags +#define aarch64_isa_flags (aarch64_feature_flags (aarch64_isa_flags_0)) +#else #undef aarch64_asm_isa_flags #define aarch64_asm_isa_flags (aarch64_get_asm_isa_flags (&global_options)) #undef aarch64_isa_flags diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 6356c419399bd324929cd599e5a4b926b0383469..45aab49de27bdfa0fb3f67ec06c7dcf0ac242fb3 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -31,10 +31,10 @@ TargetVariable enum aarch64_arch selected_arch = aarch64_no_arch TargetVariable -aarch64_feature_flags aarch64_asm_isa_flags = 0 +uint64_t aarch64_asm_isa_flags_0 = 0 TargetVariable -aarch64_feature_flags aarch64_isa_flags = 0 +uint64_t aarch64_isa_flags_0 = 0 TargetVariable unsigned aarch_enable_bti = 2 From patchwork Thu Jul 11 12:14:20 2024 Content-Type: text/plain; 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if (sysreg->arch_reqs) - return (aarch64_isa_flags & sysreg->arch_reqs); + return bool (aarch64_isa_flags & sysreg->arch_reqs); return true; } From patchwork Thu Jul 11 12:14:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 1959299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=cejedxGU; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=cejedxGU; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; 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(aarch64_update_cpp_builtins): Use TARGET_* macros. * config/aarch64/aarch64.h (AARCH64_HAVE_ISA): New macro. (AARCH64_ISA_SM_OFF, AARCH64_ISA_SM_ON, AARCH64_ISA_ZA_ON) (AARCH64_ISA_V8A, AARCH64_ISA_V8_1A, AARCH64_ISA_CRC) (AARCH64_ISA_FP, AARCH64_ISA_SIMD, AARCH64_ISA_LSE) (AARCH64_ISA_RDMA, AARCH64_ISA_V8_2A, AARCH64_ISA_F16) (AARCH64_ISA_SVE, AARCH64_ISA_SVE2, AARCH64_ISA_SVE2_AES) (AARCH64_ISA_SVE2_BITPERM, AARCH64_ISA_SVE2_SHA3) (AARCH64_ISA_SVE2_SM4, AARCH64_ISA_SME, AARCH64_ISA_SME_I16I64) (AARCH64_ISA_SME_F64F64, AARCH64_ISA_SME2, AARCH64_ISA_V8_3A) (AARCH64_ISA_DOTPROD, AARCH64_ISA_AES, AARCH64_ISA_SHA2) (AARCH64_ISA_V8_4A, AARCH64_ISA_SM4, AARCH64_ISA_SHA3) (AARCH64_ISA_F16FML, AARCH64_ISA_RCPC, AARCH64_ISA_RCPC8_4) (AARCH64_ISA_RNG, AARCH64_ISA_V8_5A, AARCH64_ISA_TME) (AARCH64_ISA_MEMTAG, AARCH64_ISA_V8_6A, AARCH64_ISA_I8MM) (AARCH64_ISA_F32MM, AARCH64_ISA_F64MM, AARCH64_ISA_BF16) (AARCH64_ISA_SB, AARCH64_ISA_RCPC3, AARCH64_ISA_V8R) (AARCH64_ISA_PAUTH, AARCH64_ISA_V8_7A, AARCH64_ISA_V8_8A) (AARCH64_ISA_V8_9A, AARCH64_ISA_V9A, AARCH64_ISA_V9_1A) (AARCH64_ISA_V9_2A, AARCH64_ISA_V9_3A, AARCH64_ISA_V9_4A) (AARCH64_ISA_MOPS, AARCH64_ISA_LS64, AARCH64_ISA_CSSC) (AARCH64_ISA_D128, AARCH64_ISA_THE, AARCH64_ISA_GCS): Remove. (TARGET_BASE_SIMD, TARGET_SIMD, TARGET_FLOAT) (TARGET_NON_STREAMING, TARGET_STREAMING, TARGET_ZA, TARGET_SHA2) (TARGET_SHA3, TARGET_AES, TARGET_SM4, TARGET_F16FML) (TARGET_CRC32, TARGET_LSE, TARGET_FP_F16INST) (TARGET_SIMD_F16INST, TARGET_DOTPROD, TARGET_SVE, TARGET_SVE2) (TARGET_SVE2_AES, TARGET_SVE2_BITPERM, TARGET_SVE2_SHA3) (TARGET_SVE2_SM4, TARGET_SME, TARGET_SME_I16I64) (TARGET_SME_F64F64, TARGET_SME2, TARGET_ARMV8_3, TARGET_JSCVT) (TARGET_FRINT, TARGET_TME, TARGET_RNG, TARGET_MEMTAG) (TARGET_I8MM, TARGET_SVE_I8MM, TARGET_SVE_F32MM) (TARGET_SVE_F64MM, TARGET_BF16_FP, TARGET_BF16_SIMD) (TARGET_SVE_BF16, TARGET_PAUTH, TARGET_BTI, TARGET_MOPS) (TARGET_LS64, TARGET_CSSC, TARGET_SB, TARGET_RCPC, TARGET_RCPC2) (TARGET_RCPC3, TARGET_SIMD_RDMA, TARGET_ARMV9_4, TARGET_D128) (TARGET_THE, TARGET_GCS): Redefine using AARCH64_HAVE_ISA. (TARGET_V8R, TARGET_V9A): New. * config/aarch64/aarch64.md (arch_enabled): Use TARGET_RCPC2. * config/aarch64/iterators.md (GPI_I16): Use TARGET_FP_F16INST. (GPF_F16): Ditto. * config/aarch64/predicates.md (aarch64_rcpc_memory_operand): Use TARGET_RCPC2. diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index 2aff097dd33c1892d255f7227c72dc90892bc78a..f9b9e379375507c5c49cac280f3a8c3e34c9aec9 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -64,7 +64,7 @@ aarch64_define_unconditional_macros (cpp_reader *pfile) builtin_define ("__ARM_ARCH_8A"); builtin_define_with_int_value ("__ARM_ARCH_PROFILE", - AARCH64_ISA_V8R ? 'R' : 'A'); + TARGET_V8R ? 'R' : 'A'); builtin_define ("__ARM_FEATURE_CLZ"); builtin_define ("__ARM_FEATURE_IDIV"); builtin_define ("__ARM_FEATURE_UNALIGNED"); @@ -132,7 +132,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (flag_unsafe_math_optimizations, "__ARM_FP_FAST", pfile); cpp_undef (pfile, "__ARM_ARCH"); - builtin_define_with_int_value ("__ARM_ARCH", AARCH64_ISA_V9A ? 9 : 8); + builtin_define_with_int_value ("__ARM_ARCH", TARGET_V9A ? 9 : 8); builtin_define_with_int_value ("__ARM_SIZEOF_MINIMAL_ENUM", flag_short_enums ? 1 : 4); @@ -259,7 +259,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_LS64, "__ARM_FEATURE_LS64", pfile); - aarch64_def_or_undef (AARCH64_ISA_RCPC, "__ARM_FEATURE_RCPC", pfile); + aarch64_def_or_undef (TARGET_RCPC, "__ARM_FEATURE_RCPC", pfile); aarch64_def_or_undef (TARGET_D128, "__ARM_FEATURE_SYSREG128", pfile); aarch64_def_or_undef (TARGET_SME, "__ARM_FEATURE_SME", pfile); diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 903e708565dc7830e9544813dd315f99d489cad2..902de6bd269d7111186d58248d1d2e1614217fa2 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -68,18 +68,6 @@ #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) -/* AdvSIMD is supported in the default configuration, unless disabled by - -mgeneral-regs-only or by the +nosimd extension. The set of available - instructions is then subdivided into: - - - the "base" set, available both in SME streaming mode and in - non-streaming mode - - - the full set, available only in non-streaming mode. */ -#define TARGET_BASE_SIMD (AARCH64_ISA_SIMD) -#define TARGET_SIMD (AARCH64_ISA_SIMD && AARCH64_ISA_SM_OFF) -#define TARGET_FLOAT (AARCH64_ISA_FP) - #define UNITS_PER_WORD 8 #define UNITS_PER_VREG 16 @@ -220,80 +208,35 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED is not always set when its constituent features are present. Check (TARGET_AES && TARGET_SHA2) instead. */ -#define AARCH64_ISA_SM_OFF (aarch64_isa_flags & AARCH64_FL_SM_OFF) -#define AARCH64_ISA_SM_ON (aarch64_isa_flags & AARCH64_FL_SM_ON) -#define AARCH64_ISA_ZA_ON (aarch64_isa_flags & AARCH64_FL_ZA_ON) +#define AARCH64_HAVE_ISA(X) (bool (aarch64_isa_flags & AARCH64_FL_##X)) + #define AARCH64_ISA_MODE (aarch64_isa_mode) (aarch64_isa_flags & AARCH64_FL_ISA_MODES) -#define AARCH64_ISA_V8A (aarch64_isa_flags & AARCH64_FL_V8A) -#define AARCH64_ISA_V8_1A (aarch64_isa_flags & AARCH64_FL_V8_1A) -#define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) -#define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) -#define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) -#define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) -#define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) -#define AARCH64_ISA_V8_2A (aarch64_isa_flags & AARCH64_FL_V8_2A) -#define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) -#define AARCH64_ISA_SVE (aarch64_isa_flags & AARCH64_FL_SVE) -#define AARCH64_ISA_SVE2 (aarch64_isa_flags & AARCH64_FL_SVE2) -#define AARCH64_ISA_SVE2_AES (aarch64_isa_flags & AARCH64_FL_SVE2_AES) -#define AARCH64_ISA_SVE2_BITPERM (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM) -#define AARCH64_ISA_SVE2_SHA3 (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3) -#define AARCH64_ISA_SVE2_SM4 (aarch64_isa_flags & AARCH64_FL_SVE2_SM4) -#define AARCH64_ISA_SME (aarch64_isa_flags & AARCH64_FL_SME) -#define AARCH64_ISA_SME_I16I64 (aarch64_isa_flags & AARCH64_FL_SME_I16I64) -#define AARCH64_ISA_SME_F64F64 (aarch64_isa_flags & AARCH64_FL_SME_F64F64) -#define AARCH64_ISA_SME2 (aarch64_isa_flags & AARCH64_FL_SME2) -#define AARCH64_ISA_V8_3A (aarch64_isa_flags & AARCH64_FL_V8_3A) -#define AARCH64_ISA_DOTPROD (aarch64_isa_flags & AARCH64_FL_DOTPROD) -#define AARCH64_ISA_AES (aarch64_isa_flags & AARCH64_FL_AES) -#define AARCH64_ISA_SHA2 (aarch64_isa_flags & AARCH64_FL_SHA2) -#define AARCH64_ISA_V8_4A (aarch64_isa_flags & AARCH64_FL_V8_4A) -#define AARCH64_ISA_SM4 (aarch64_isa_flags & AARCH64_FL_SM4) -#define AARCH64_ISA_SHA3 (aarch64_isa_flags & AARCH64_FL_SHA3) -#define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML) -#define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC) -#define AARCH64_ISA_RCPC8_4 ((AARCH64_ISA_RCPC && AARCH64_ISA_V8_4A) \ - || (aarch64_isa_flags & AARCH64_FL_RCPC3)) -#define AARCH64_ISA_RNG (aarch64_isa_flags & AARCH64_FL_RNG) -#define AARCH64_ISA_V8_5A (aarch64_isa_flags & AARCH64_FL_V8_5A) -#define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME) -#define AARCH64_ISA_MEMTAG (aarch64_isa_flags & AARCH64_FL_MEMTAG) -#define AARCH64_ISA_V8_6A (aarch64_isa_flags & AARCH64_FL_V8_6A) -#define AARCH64_ISA_I8MM (aarch64_isa_flags & AARCH64_FL_I8MM) -#define AARCH64_ISA_F32MM (aarch64_isa_flags & AARCH64_FL_F32MM) -#define AARCH64_ISA_F64MM (aarch64_isa_flags & AARCH64_FL_F64MM) -#define AARCH64_ISA_BF16 (aarch64_isa_flags & AARCH64_FL_BF16) -#define AARCH64_ISA_SB (aarch64_isa_flags & AARCH64_FL_SB) -#define AARCH64_ISA_RCPC3 (aarch64_isa_flags & AARCH64_FL_RCPC3) -#define AARCH64_ISA_V8R (aarch64_isa_flags & AARCH64_FL_V8R) -#define AARCH64_ISA_PAUTH (aarch64_isa_flags & AARCH64_FL_PAUTH) -#define AARCH64_ISA_V8_7A (aarch64_isa_flags & AARCH64_FL_V8_7A) -#define AARCH64_ISA_V8_8A (aarch64_isa_flags & AARCH64_FL_V8_8A) -#define AARCH64_ISA_V8_9A (aarch64_isa_flags & AARCH64_FL_V8_9A) -#define AARCH64_ISA_V9A (aarch64_isa_flags & AARCH64_FL_V9A) -#define AARCH64_ISA_V9_1A (aarch64_isa_flags & AARCH64_FL_V9_1A) -#define AARCH64_ISA_V9_2A (aarch64_isa_flags & AARCH64_FL_V9_2A) -#define AARCH64_ISA_V9_3A (aarch64_isa_flags & AARCH64_FL_V9_3A) -#define AARCH64_ISA_V9_4A (aarch64_isa_flags & AARCH64_FL_V9_4A) -#define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS) -#define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64) -#define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC) -#define AARCH64_ISA_D128 (aarch64_isa_flags & AARCH64_FL_D128) -#define AARCH64_ISA_THE (aarch64_isa_flags & AARCH64_FL_THE) -#define AARCH64_ISA_GCS (aarch64_isa_flags & AARCH64_FL_GCS) /* The current function is a normal non-streaming function. */ -#define TARGET_NON_STREAMING (AARCH64_ISA_SM_OFF) +#define TARGET_NON_STREAMING AARCH64_HAVE_ISA (SM_OFF) /* The current function has a streaming body. */ -#define TARGET_STREAMING (AARCH64_ISA_SM_ON) +#define TARGET_STREAMING AARCH64_HAVE_ISA (SM_ON) /* The current function has a streaming-compatible body. */ #define TARGET_STREAMING_COMPATIBLE \ ((aarch64_isa_flags & AARCH64_FL_SM_STATE) == 0) /* PSTATE.ZA is enabled in the current function body. */ -#define TARGET_ZA (AARCH64_ISA_ZA_ON) +#define TARGET_ZA AARCH64_HAVE_ISA (ZA_ON) + +/* AdvSIMD is supported in the default configuration, unless disabled by + -mgeneral-regs-only or by the +nosimd extension. The set of available + instructions is then subdivided into: + + - the "base" set, available both in SME streaming mode and in + non-streaming mode + + - the full set, available only in non-streaming mode. */ +#define TARGET_BASE_SIMD AARCH64_HAVE_ISA (SIMD) +#define TARGET_SIMD (TARGET_BASE_SIMD && TARGET_NON_STREAMING) +#define TARGET_FLOAT AARCH64_HAVE_ISA (FP) + /* AARCH64_FL options necessary for system register implementation. */ /* Define AARCH64_FL aliases for architectural features which are protected @@ -328,123 +271,127 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED #define AARCH64_FL_SPE_FDS AARCH64_FL_V8_9A #define AARCH64_FL_TCR2 AARCH64_FL_V8_9A +#define TARGET_V8R AARCH64_HAVE_ISA (V8R) +#define TARGET_V9A AARCH64_HAVE_ISA (V9A) + + /* SHA2 is an optional extension to AdvSIMD. */ -#define TARGET_SHA2 (AARCH64_ISA_SHA2) +#define TARGET_SHA2 AARCH64_HAVE_ISA (SHA2) /* SHA3 is an optional extension to AdvSIMD. */ -#define TARGET_SHA3 (AARCH64_ISA_SHA3) +#define TARGET_SHA3 AARCH64_HAVE_ISA (SHA3) /* AES is an optional extension to AdvSIMD. */ -#define TARGET_AES (AARCH64_ISA_AES) +#define TARGET_AES AARCH64_HAVE_ISA (AES) /* SM is an optional extension to AdvSIMD. */ -#define TARGET_SM4 (AARCH64_ISA_SM4) +#define TARGET_SM4 AARCH64_HAVE_ISA (SM4) /* FP16FML is an optional extension to AdvSIMD. */ -#define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST) +#define TARGET_F16FML (TARGET_SIMD && AARCH64_HAVE_ISA (F16FML) && TARGET_FP_F16INST) /* CRC instructions that can be enabled through +crc arch extension. */ -#define TARGET_CRC32 (AARCH64_ISA_CRC) +#define TARGET_CRC32 AARCH64_HAVE_ISA (CRC) /* Atomic instructions that can be enabled through the +lse extension. */ -#define TARGET_LSE (AARCH64_ISA_LSE) +#define TARGET_LSE AARCH64_HAVE_ISA (LSE) /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension. */ -#define TARGET_FP_F16INST (AARCH64_ISA_F16) -#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16) +#define TARGET_FP_F16INST AARCH64_HAVE_ISA (F16) +#define TARGET_SIMD_F16INST (TARGET_SIMD && TARGET_FP_F16INST) /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod. */ -#define TARGET_DOTPROD (AARCH64_ISA_DOTPROD) +#define TARGET_DOTPROD AARCH64_HAVE_ISA (DOTPROD) /* SVE instructions, enabled through +sve. */ -#define TARGET_SVE (AARCH64_ISA_SVE) +#define TARGET_SVE AARCH64_HAVE_ISA (SVE) /* SVE2 instructions, enabled through +sve2. */ -#define TARGET_SVE2 (AARCH64_ISA_SVE2) +#define TARGET_SVE2 AARCH64_HAVE_ISA (SVE2) /* SVE2 AES instructions, enabled through +sve2-aes. */ -#define TARGET_SVE2_AES (AARCH64_ISA_SVE2_AES && TARGET_NON_STREAMING) +#define TARGET_SVE2_AES (AARCH64_HAVE_ISA (SVE2_AES) && TARGET_NON_STREAMING) /* SVE2 BITPERM instructions, enabled through +sve2-bitperm. */ -#define TARGET_SVE2_BITPERM (AARCH64_ISA_SVE2_BITPERM && TARGET_NON_STREAMING) +#define TARGET_SVE2_BITPERM (AARCH64_HAVE_ISA (SVE2_BITPERM) && TARGET_NON_STREAMING) /* SVE2 SHA3 instructions, enabled through +sve2-sha3. */ -#define TARGET_SVE2_SHA3 (AARCH64_ISA_SVE2_SHA3 && TARGET_NON_STREAMING) +#define TARGET_SVE2_SHA3 (AARCH64_HAVE_ISA (SVE2_SHA3) && TARGET_NON_STREAMING) /* SVE2 SM4 instructions, enabled through +sve2-sm4. */ -#define TARGET_SVE2_SM4 (AARCH64_ISA_SVE2_SM4 && TARGET_NON_STREAMING) +#define TARGET_SVE2_SM4 (AARCH64_HAVE_ISA (SVE2_SM4) && TARGET_NON_STREAMING) /* SME instructions, enabled through +sme. Note that this does not imply anything about the state of PSTATE.SM. */ -#define TARGET_SME (AARCH64_ISA_SME) +#define TARGET_SME AARCH64_HAVE_ISA (SME) /* Same with streaming mode enabled. */ #define TARGET_STREAMING_SME (TARGET_STREAMING && TARGET_SME) /* The FEAT_SME_I16I64 extension to SME, enabled through +sme-i16i64. */ -#define TARGET_SME_I16I64 (AARCH64_ISA_SME_I16I64) +#define TARGET_SME_I16I64 AARCH64_HAVE_ISA (SME_I16I64) /* The FEAT_SME_F64F64 extension to SME, enabled through +sme-f64f64. */ -#define TARGET_SME_F64F64 (AARCH64_ISA_SME_F64F64) +#define TARGET_SME_F64F64 AARCH64_HAVE_ISA (SME_F64F64) /* SME2 instructions, enabled through +sme2. */ -#define TARGET_SME2 (AARCH64_ISA_SME2) +#define TARGET_SME2 AARCH64_HAVE_ISA (SME2) /* Same with streaming mode enabled. */ #define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2) /* ARMv8.3-A features. */ -#define TARGET_ARMV8_3 (AARCH64_ISA_V8_3A) +#define TARGET_ARMV8_3 AARCH64_HAVE_ISA (V8_3A) /* Javascript conversion instruction from Armv8.3-a. */ -#define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3A) +#define TARGET_JSCVT (TARGET_FLOAT && TARGET_ARMV8_3) /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) /* Floating-point rounding instructions from Armv8.5-a. */ -#define TARGET_FRINT (AARCH64_ISA_V8_5A && TARGET_FLOAT) +#define TARGET_FRINT (AARCH64_HAVE_ISA (V8_5A) && TARGET_FLOAT) /* TME instructions are enabled. */ -#define TARGET_TME (AARCH64_ISA_TME) +#define TARGET_TME AARCH64_HAVE_ISA (TME) /* Random number instructions from Armv8.5-a. */ -#define TARGET_RNG (AARCH64_ISA_RNG) +#define TARGET_RNG AARCH64_HAVE_ISA (RNG) /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag. */ -#define TARGET_MEMTAG (AARCH64_ISA_MEMTAG) +#define TARGET_MEMTAG AARCH64_HAVE_ISA (MEMTAG) /* I8MM instructions are enabled through +i8mm. */ -#define TARGET_I8MM (AARCH64_ISA_I8MM) -#define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM) +#define TARGET_I8MM AARCH64_HAVE_ISA (I8MM) +#define TARGET_SVE_I8MM (TARGET_SVE && TARGET_I8MM) /* F32MM instructions are enabled through +f32mm. */ -#define TARGET_SVE_F32MM (AARCH64_ISA_F32MM) +#define TARGET_SVE_F32MM AARCH64_HAVE_ISA (F32MM) /* F64MM instructions are enabled through +f64mm. */ -#define TARGET_SVE_F64MM (AARCH64_ISA_F64MM) +#define TARGET_SVE_F64MM AARCH64_HAVE_ISA (F64MM) /* BF16 instructions are enabled through +bf16. */ -#define TARGET_BF16_FP (AARCH64_ISA_BF16) -#define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD) -#define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16) +#define TARGET_BF16_FP AARCH64_HAVE_ISA (BF16) +#define TARGET_BF16_SIMD (TARGET_BF16_FP && TARGET_SIMD) +#define TARGET_SVE_BF16 (TARGET_BF16_FP && TARGET_SVE) /* PAUTH instructions are enabled through +pauth. */ -#define TARGET_PAUTH (AARCH64_ISA_PAUTH) +#define TARGET_PAUTH AARCH64_HAVE_ISA (PAUTH) /* BTI instructions exist from Armv8.5-a onwards. Their automatic use is enabled through -mbranch-protection by using NOP-space instructions, but this TARGET_ is used for defining BTI-related ACLE things. */ -#define TARGET_BTI (AARCH64_ISA_V8_5A) +#define TARGET_BTI AARCH64_HAVE_ISA (V8_5A) /* MOPS instructions are enabled through +mops. */ -#define TARGET_MOPS (AARCH64_ISA_MOPS) +#define TARGET_MOPS AARCH64_HAVE_ISA (MOPS) /* LS64 instructions are enabled through +ls64. */ -#define TARGET_LS64 (AARCH64_ISA_LS64) +#define TARGET_LS64 AARCH64_HAVE_ISA (LS64) /* CSSC instructions are enabled through +cssc. */ -#define TARGET_CSSC (AARCH64_ISA_CSSC) +#define TARGET_CSSC AARCH64_HAVE_ISA (CSSC) /* Make sure this is always defined so we don't have to check for ifdefs but rather use normal ifs. */ @@ -456,17 +403,17 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED #endif /* SB instruction is enabled through +sb. */ -#define TARGET_SB (AARCH64_ISA_SB) +#define TARGET_SB AARCH64_HAVE_ISA (SB) /* RCPC loads from Armv8.3-a. */ -#define TARGET_RCPC (AARCH64_ISA_RCPC) +#define TARGET_RCPC AARCH64_HAVE_ISA (RCPC) /* The RCPC2 extensions from Armv8.4-a that allow immediate offsets to LDAPR and sign-extending versions.*/ -#define TARGET_RCPC2 (AARCH64_ISA_RCPC8_4) +#define TARGET_RCPC2 ((AARCH64_HAVE_ISA (V8_4A) && TARGET_RCPC) || TARGET_RCPC3) /* RCPC3 (Release Consistency) extensions, optional from Armv8.2-a. */ -#define TARGET_RCPC3 (AARCH64_ISA_RCPC3) +#define TARGET_RCPC3 AARCH64_HAVE_ISA (RCPC3) /* Apply the workaround for Cortex-A53 erratum 835769. */ #define TARGET_FIX_ERR_A53_835769 \ @@ -488,22 +435,22 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) /* ARMv8.1-A Adv.SIMD support. */ -#define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) +#define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_HAVE_ISA (RDMA)) /* Armv9.4-A features. */ -#define TARGET_ARMV9_4 (AARCH64_ISA_V9_4A) +#define TARGET_ARMV9_4 AARCH64_HAVE_ISA (V9_4A) /* 128-bit System Registers and Instructions from Armv9.4-a are enabled through +d128. */ -#define TARGET_D128 (AARCH64_ISA_D128) +#define TARGET_D128 AARCH64_HAVE_ISA (D128) /* Armv8.9-A/9.4-A Translation Hardening Extension system registers are enabled through +the. */ -#define TARGET_THE (AARCH64_ISA_THE) +#define TARGET_THE AARCH64_HAVE_ISA (THE) /* Armv9.4-A Guarded Control Stack extension system registers are enabled through +gcs. */ -#define TARGET_GCS (AARCH64_ISA_GCS) +#define TARGET_GCS AARCH64_HAVE_ISA (GCS) /* Prefer different predicate registers for the output of a predicated operation over re-using an existing input predicate. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9de6235b1398f1ed77686f7a914960c662a88dc8..94ff0eefa77fbc1a9445768379f1638f77e38e9c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -477,7 +477,7 @@ (eq_attr "arch" "any") (and (eq_attr "arch" "rcpc8_4") - (match_test "AARCH64_ISA_RCPC8_4")) + (match_test "TARGET_RCPC2")) (and (eq_attr "arch" "fp") (match_test "TARGET_FLOAT")) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index f527b2cfeb817b96383eeaaa4e751a51f9be68a5..95fe8f070f4c3f5770e4424162bf13b712adedf3 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -30,7 +30,7 @@ (define_mode_iterator GPI [SI DI]) ;; Iterator for HI, SI, DI, some instructions can only work on these modes. -(define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI]) +(define_mode_iterator GPI_I16 [(HI "TARGET_FP_F16INST") SI DI]) ;; "Iterator" for just TI -- features like @pattern only work with iterators. (define_mode_iterator JUST_TI [TI]) @@ -55,7 +55,7 @@ (define_mode_iterator GPF [SF DF]) ;; Iterator for all scalar floating point modes (HF, SF, DF) -(define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF]) +(define_mode_iterator GPF_F16 [(HF "TARGET_FP_F16INST") SF DF]) ;; Iterator for all scalar floating point modes (HF, SF, DF) (define_mode_iterator GPF_HF [HF SF DF]) diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index b895f5dcb867abd67d24cf7beaec90523aef17e1..8f3aab2272c62d5dcc06dfd14fd00067e4db6b8e 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -518,7 +518,7 @@ }) (define_predicate "aarch64_rcpc_memory_operand" - (if_then_else (match_test "AARCH64_ISA_RCPC8_4") + (if_then_else (match_test "TARGET_RCPC2") (match_operand 0 "aarch64_9bit_offset_memory_operand") (match_operand 0 "aarch64_sync_memory_operand"))) From patchwork Thu Jul 11 12:15:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 1959300 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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constexpr aarch64_feature_flags get_flags_off (aarch64_feature_flags mask) { - return (0 + return (aarch64_feature_flags (0) #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) \ - | (feature_deps::IDENT ().enable & mask ? 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014)(35042699022); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2024 12:16:10.3435 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3872b897-8ac3-47e6-ae62-08dca1a33fe6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D02.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB5746 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org This class provides a constant-size bitmap that can be used as almost a drop-in replacement for bitmaps stored in integer types. The implementation is entirely within the header file and uses recursive templated operations to support effective optimisation and usage in constexpr expressions. This initial implementation hardcodes the choice of uint64_t elements for storage and initialisation, but this could instead be specified via a second template parameter. gcc/ChangeLog: * bbitmap.h: New file. diff --git a/gcc/bbitmap.h b/gcc/bbitmap.h new file mode 100644 index 0000000000000000000000000000000000000000..108ac1bf9e6042f5ae16988bc1688fe0045a3293 --- /dev/null +++ b/gcc/bbitmap.h @@ -0,0 +1,238 @@ +/* Functions to support fixed-length bitmaps. + Copyright (C) 2024 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 3, or (at your option) any later +version. + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#ifndef GCC_BBITMAP_H +#define GCC_BBITMAP_H + +/* Implementation of bounded (fixed length) bitmaps. + + This provides a drop-in replacement for bitmaps that have outgrown the + storage capacity of a single integer. + + Sets are stored as a fixed length array of uint64_t elements. The length of + this array is given as a template parameter. */ + +template +struct bbitmap_operators +{ + template + static constexpr Result binary(Operator op, const Arg &x, const Arg &y, + Rest ...rest) + { + return bbitmap_operators::template binary + (op, x, y, op (x.val[M - 1], y.val[M - 1]), rest...); + } + + template + static void compound(Operator op, Arg &x, const Arg &y) + { + bbitmap_operators::template compound (op, x, y); + x.val[M - 1] = op (x.val[M - 1], y.val[M - 1]); + } + + template + static constexpr Result bit_not(const Arg &x, Rest ...rest) + { + return bbitmap_operators::template bit_not + (x, ~(x.val[M - 1]), rest...); + } + + template + static constexpr bool non_zero(const Arg &x) + { + return (bool) x.val[M - 1] + || bbitmap_operators::template non_zero (x); + } + + template + static constexpr bool equal(const Arg &x, const Arg &y) + { + return x.val[M - 1] == y.val[M - 1] + && bbitmap_operators::template equal (x, y); + } + +#define SUB_INDEX(i) (i - (M - 1) * 64) +#define IN_SUB_RANGE(i) (SUB_INDEX (i) >= 0 && SUB_INDEX (i) < 64) + + template + static constexpr Result from_index(int index, Rest ...rest) + { + return bbitmap_operators::template from_index + (index, + (IN_SUB_RANGE (index) + ? (uint64_t (1) << (IN_SUB_RANGE (index) ? SUB_INDEX (index) : 0)) + : uint64_t (0)), + rest...); + } + +#undef IN_SUB_RANGE +#undef SUB_INDEX + +}; + +template<> +struct bbitmap_operators<0> +{ + template + static constexpr Result binary(Operator, const Arg, const Arg, + Rest ...rest) + { + return Result { rest... }; + } + + template + static void compound(Operator, Arg, const Arg) + { + return; + } + + template + static constexpr Result bit_not(const Arg, Rest ...rest) + { + return Result { rest... }; + } + + template + static constexpr bool non_zero(const Arg) + { + return false; + } + + template + static constexpr bool equal(const Arg, const Arg) + { + return true; + } + + template + static constexpr Result from_index(int, Rest ...rest) + { + return Result { rest... }; + } +}; + +template +constexpr T bbitmap_element_or(T x, T y) { return x | y;} + +template +constexpr T bbitmap_element_and(T x, T y) { return x & y;} + +template +constexpr T bbitmap_element_xor(T x, T y) { return x ^ y;} + + + +template +class GTY((user)) bbitmap +{ +public: + uint64_t val[N]; + + template + constexpr bbitmap(Rest ...rest) : val{(uint64_t) rest...} {} + + constexpr bbitmap operator|(const bbitmap other) const + { + return bbitmap_operators::template binary>(bbitmap_element_or, + *this, other); + } + + bbitmap operator|=(const bbitmap other) + { + bbitmap_operators::template compound (bbitmap_element_or, + *this, other); + return this; + } + + constexpr bbitmap operator&(const bbitmap other) const + { + return bbitmap_operators::template binary>(bbitmap_element_and, + *this, other); + } + + bbitmap operator&=(const bbitmap other) + { + bbitmap_operators::template compound (bbitmap_element_and, + *this, other); + return this; + } + + constexpr bbitmap operator^(const bbitmap other) const + { + return bbitmap_operators::template binary>(bbitmap_element_xor, + *this, other); + } + + bbitmap operator^=(const bbitmap other) + { + bbitmap_operators::template compound (bbitmap_element_xor, + *this, other); + return this; + } + + constexpr bbitmap operator~() const + { + return bbitmap_operators::template bit_not>(*this); + } + + constexpr bool operator!() const + { + return !(bbitmap_operators::template non_zero>(*this)); + } + + constexpr explicit operator bool() const + { + return bbitmap_operators::template non_zero>(*this); + } + + constexpr bool operator==(const bbitmap other) const + { + return bbitmap_operators::template equal>(*this, other); + } + + constexpr bool operator!=(const bbitmap other) const + { + return !(bbitmap_operators::template equal>(*this, other)); + } + + static constexpr bbitmap from_index (int index) + { + return bbitmap_operators::template from_index> (index); + } +}; + +template +void +gt_ggc_mx (bbitmap *) +{ +} + +template +void +gt_pch_nx (bbitmap *) +{ +} + +template +void +gt_pch_nx (bbitmap *, gt_pointer_operator, void *) +{ +} + +#endif From patchwork Thu Jul 11 12:16:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 1959302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; 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Most of the preparatory work was carried out in previous commits, so this patch itself is fairly small. gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc (aarch64_set_asm_isa_flags): Store a second uint64_t value. * config/aarch64/aarch64-opts.h (aarch64_feature_flags): Switch typedef to bbitmap<2>. * config/aarch64/aarch64.cc (aarch64_set_current_function): Extract isa mode from val[0]. * config/aarch64/aarch64.h (aarch64_get_asm_isa_flags): Load a second uint64_t value. (aarch64_get_isa_flags): Ditto. (aarch64_asm_isa_flags): Ditto. (aarch64_isa_flags): Ditto. (HANDLE): Use bbitmap<2>::from_index to initialise flags. (AARCH64_FL_ISA_MODES): Do arithmetic on integer type. (AARCH64_ISA_MODE): Extract value from bbitmap<2> array. * config/aarch64/aarch64.opt (aarch64_asm_isa_flags_1): New variable. (aarch64_isa_flags_1): Ditto. diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc index bd0770dd0d84005701afed35d4af356380a405e9..64b65b7ff9e4bf7c72bf0c5db6fa976a51fe9f32 100644 --- a/gcc/common/config/aarch64/aarch64-common.cc +++ b/gcc/common/config/aarch64/aarch64-common.cc @@ -67,15 +67,19 @@ static const struct default_options aarch_option_optimization_table[] = }; -/* Set OPTS->x_aarch64_asm_isa_flags_0 to FLAGS and update - OPTS->x_aarch64_isa_flags_0 accordingly. */ +/* Set OPTS->x_aarch64_asm_isa_flags_<0..n> to FLAGS and update + OPTS->x_aarch64_isa_flags_<0..n> accordingly. */ void aarch64_set_asm_isa_flags (gcc_options *opts, aarch64_feature_flags flags) { - opts->x_aarch64_asm_isa_flags_0 = flags; + opts->x_aarch64_asm_isa_flags_0 = flags.val[0]; + opts->x_aarch64_asm_isa_flags_1 = flags.val[1]; + if (opts->x_target_flags & MASK_GENERAL_REGS_ONLY) flags &= ~feature_deps::get_flags_off (AARCH64_FL_FP); - opts->x_aarch64_isa_flags_0 = flags; + + opts->x_aarch64_isa_flags_0 = flags.val[0]; + opts->x_aarch64_isa_flags_1 = flags.val[1]; } /* Implement TARGET_HANDLE_OPTION. diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index 2c36bfaad19b999238601d44709c280ef987046b..80ec1a05253da62b20eebb5e491f04c6da6851e7 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -23,14 +23,16 @@ #define GCC_AARCH64_OPTS_H #ifndef USED_FOR_TARGET -typedef uint64_t aarch64_isa_mode; +#include "bbitmap.h" -typedef uint64_t aarch64_feature_flags; +typedef uint64_t aarch64_isa_mode; constexpr unsigned int AARCH64_NUM_ISA_MODES = (0 #define DEF_AARCH64_ISA_MODE(IDENT) + 1 #include "aarch64-isa-modes.def" ); + +typedef bbitmap<2> aarch64_feature_flags; #endif /* The various cores that implement AArch64. */ diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 902de6bd269d7111186d58248d1d2e1614217fa2..8056c33795738b779bc14697803da3eee04fe330 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -23,17 +23,21 @@ #define GCC_AARCH64_H #define aarch64_get_asm_isa_flags(opts) \ - (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags_0)) + (aarch64_feature_flags ((opts)->x_aarch64_asm_isa_flags_0, \ + (opts)->x_aarch64_asm_isa_flags_1)) #define aarch64_get_isa_flags(opts) \ - (aarch64_feature_flags ((opts)->x_aarch64_isa_flags_0)) + (aarch64_feature_flags ((opts)->x_aarch64_isa_flags_0, \ + (opts)->x_aarch64_isa_flags_1)) /* Make these flags read-only so that all uses go via aarch64_set_asm_isa_flags. */ #ifdef GENERATOR_FILE #undef aarch64_asm_isa_flags -#define aarch64_asm_isa_flags (aarch64_feature_flags (aarch64_asm_isa_flags_0)) +#define aarch64_asm_isa_flags (aarch64_feature_flags (aarch64_asm_isa_flags_0,\ + aarch64_asm_isa_flags_1)) #undef aarch64_isa_flags -#define aarch64_isa_flags (aarch64_feature_flags (aarch64_isa_flags_0)) +#define aarch64_isa_flags (aarch64_feature_flags (aarch64_isa_flags_0, \ + aarch64_isa_flags_1)) #else #undef aarch64_asm_isa_flags #define aarch64_asm_isa_flags (aarch64_get_asm_isa_flags (&global_options)) @@ -167,8 +171,8 @@ enum class aarch64_feature : unsigned char { /* Define unique flags for each of the above. */ #define HANDLE(IDENT) \ - constexpr auto AARCH64_FL_##IDENT \ - = aarch64_feature_flags (1) << int (aarch64_feature::IDENT); + constexpr auto AARCH64_FL_##IDENT ATTRIBUTE_UNUSED \ + = aarch64_feature_flags::from_index (int (aarch64_feature::IDENT)); #define DEF_AARCH64_ISA_MODE(IDENT) HANDLE (IDENT) #define AARCH64_OPT_EXTENSION(A, IDENT, C, D, E, F) HANDLE (IDENT) #define AARCH64_ARCH(A, B, IDENT, D, E) HANDLE (IDENT) @@ -191,7 +195,7 @@ constexpr auto AARCH64_ISA_MODE_SM_STATE ATTRIBUTE_UNUSED /* The mask of all ISA modes. */ constexpr auto AARCH64_FL_ISA_MODES - = (aarch64_feature_flags (1) << AARCH64_NUM_ISA_MODES) - 1; + = aarch64_feature_flags ((1 << AARCH64_NUM_ISA_MODES) - 1); /* The default ISA mode, for functions with no attributes that specify something to the contrary. */ @@ -210,7 +214,7 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED #define AARCH64_HAVE_ISA(X) (bool (aarch64_isa_flags & AARCH64_FL_##X)) -#define AARCH64_ISA_MODE (aarch64_isa_mode) (aarch64_isa_flags & AARCH64_FL_ISA_MODES) +#define AARCH64_ISA_MODE ((aarch64_isa_flags & AARCH64_FL_ISA_MODES).val[0]) /* The current function is a normal non-streaming function. */ #define TARGET_NON_STREAMING AARCH64_HAVE_ISA (SM_OFF) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 229e438115c268f876c6d77e1fcc4faa2f7d231b..0d9e80d85b207e547d114e215096238eb17cc8bf 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -19121,7 +19121,7 @@ aarch64_set_current_function (tree fndecl) aarch64_pragma_target_parse. */ if (old_tree == new_tree && (!fndecl || aarch64_previous_fndecl) - && (aarch64_isa_mode) (isa_flags & AARCH64_FL_ISA_MODES) == new_isa_mode) + && (isa_flags & AARCH64_FL_ISA_MODES).val[0] == new_isa_mode) { gcc_assert (AARCH64_ISA_MODE == new_isa_mode); return; @@ -19136,11 +19136,11 @@ aarch64_set_current_function (tree fndecl) /* The ISA mode can vary based on function type attributes and function declaration attributes. Make sure that the target options correctly reflect these attributes. */ - if ((aarch64_isa_mode) (isa_flags & AARCH64_FL_ISA_MODES) != new_isa_mode) + if ((isa_flags & AARCH64_FL_ISA_MODES).val[0] != new_isa_mode) { auto base_flags = (aarch64_asm_isa_flags & ~AARCH64_FL_ISA_MODES); aarch64_set_asm_isa_flags (base_flags - | (aarch64_feature_flags) new_isa_mode); + | aarch64_feature_flags (new_isa_mode)); aarch64_override_options_internal (&global_options); new_tree = build_target_option_node (&global_options, diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 45aab49de27bdfa0fb3f67ec06c7dcf0ac242fb3..2f90f10352af75f70112d07894ab200f48b143f4 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -33,9 +33,15 @@ enum aarch64_arch selected_arch = aarch64_no_arch TargetVariable uint64_t aarch64_asm_isa_flags_0 = 0 +TargetVariable +uint64_t aarch64_asm_isa_flags_1 = 0 + TargetVariable uint64_t aarch64_isa_flags_0 = 0 +TargetVariable +uint64_t aarch64_isa_flags_1 = 0 + TargetVariable unsigned aarch_enable_bti = 2