From patchwork Thu Jul 11 08:29:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1959141 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=bWRY7AZS; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WKSZz3dnzz20MP for ; Thu, 11 Jul 2024 18:30:03 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9E2FD386180B for ; Thu, 11 Jul 2024 08:30:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 678963858D3C for ; Thu, 11 Jul 2024 08:29:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 678963858D3C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 678963858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720686564; cv=none; b=Fk0DFxirYr5rhqFKNdd0JAzASHc9OraIwGlr53G2eiepD7gLXytOV6rkHyg/jvv6cLlfKEAyjgqkh4b27pbHUYqBLw5tOlK2obltJj4bV/WN/fGddAPrB7nKR7oXMToSucC73vWZC01C8SOhlHFrydiaz5fp1jIXWLlELbdG+Ys= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720686564; c=relaxed/simple; bh=hfiiAuHff0s5HrOSGF0xhgdGimF9GcacQjnheYfOGYI=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=LKmawTcBclstp0UptyDahJ/dURZ+lBFq6450QKeMpyySBenbhhhrs9BbJw91xxfB8NX1N9shIAy6F0nHAP2PdZWLKPIksHY6CPSNjYfGPDIw303b9VbdLB7qwSxKXlNCwymUMcotxfVn+ma+KJ2Dhdq5bJkOZ5c284RLKngDxSs= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1720686557; x=1752222557; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=hfiiAuHff0s5HrOSGF0xhgdGimF9GcacQjnheYfOGYI=; b=bWRY7AZSxmxjV5ppcdzshALRMtIYeiyDadslopo8a22D8RD3MUMTdfPt AUahVFU+hBSWv7wPQniSxHE3kHmDfIp6VSW7q8G5XU19jWorThAJ9L6+P EK6wNy8wDWLnWY5TjsAYiptZfBAlvXSXGqI/no6HHMOLTm9fB+9XA7Lfn BLtdF2MhXhnYsDDu5crSx+8nq55klh8Cjcw7jYkBc2WyzqdC37kwLpARZ xyAE1L8c10Q11kqM9MoJ0+5TsWXWaLURGyM5IM2NoFTxx2uO+Qrm64zwn ivg++YHKSx8t3ICMZGy90NKXp6b+ILNR+9UfN+AZU0x/2LibaoKOFjNOQ w==; X-CSE-ConnectionGUID: OFhiqDvVR3OB0O/Oqkp7DA== X-CSE-MsgGUID: J4bG4FXYRLSViGVc3PkcXg== X-IronPort-AV: E=McAfee;i="6700,10204,11129"; a="43470899" X-IronPort-AV: E=Sophos;i="6.09,199,1716274800"; d="scan'208";a="43470899" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2024 01:29:16 -0700 X-CSE-ConnectionGUID: 2JWIzfxHSiWJthQ9te+ixg== X-CSE-MsgGUID: 4UThRwjfShSXm+ho5/mUPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,199,1716274800"; d="scan'208";a="48455116" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmviesa008.fm.intel.com with ESMTP; 11 Jul 2024 01:29:14 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A82741005667; Thu, 11 Jul 2024 16:29:13 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1] RISC-V: Add testcases for vector .SAT_SUB in zip benchmark Date: Thu, 11 Jul 2024 16:29:12 +0800 Message-Id: <20240711082912.761806-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li This patch would like to add the test cases for the vector .SAT_SUB in the zip benchmark. Aka: Form in zip benchmark: #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ { \ T2 a; \ T1 *p = x; \ do { \ a = *--p; \ *p = (T1)(a >= b ? a - b : 0); \ } while (--limit); \ } DEF_VEC_SAT_U_SUB_ZIP(uint8_t, uint16_t) vec_sat_u_sub_uint16_t_uint32_t_fmt_zip: ... vsetvli a4,zero,e32,m1,ta,ma vmv.v.x v6,a1 vsetvli zero,zero,e16,mf2,ta,ma vid.v v2 li a4,-1 vnclipu.wi v6,v6,0 // .SAT_TRUNC .L3: vle16.v v3,0(a3) vrsub.vx v5,v2,a6 mv a7,a4 addw a4,a4,t3 vrgather.vv v1,v3,v5 vssubu.vv v1,v1,v6 // .SAT_SUB vrgather.vv v3,v1,v5 vse16.v v3,0(a3) sub a3,a3,t1 bgtu t4,a4,.L3 Passed the rv64gcv tests. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: Add test data for .SAT_SUB in zip benchmark. * gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 18 +++++ .../rvv/autovec/binop/vec_sat_binary_vx.h | 22 +++++ .../riscv/rvv/autovec/binop/vec_sat_data.h | 81 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub_zip-run.c | 16 ++++ .../rvv/autovec/binop/vec_sat_u_sub_zip.c | 18 +++++ 5 files changed, 155 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 10459807b2c..416a1e49a47 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -322,6 +322,19 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \ +{ \ + T2 a; \ + T1 *p = x; \ + do { \ + a = *--p; \ + *p = (T1)(a >= b ? a - b : 0); \ + } while (--limit); \ +} +#define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2) + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -352,6 +365,11 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ + vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) +#define RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) \ + RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ + /******************************************************************************/ /* Saturation Sub Truncated (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h new file mode 100644 index 00000000000..d238c6392de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary_vx.h @@ -0,0 +1,22 @@ +#ifndef HAVE_DEFINED_VEC_SAT_BINARY_VX_H +#define HAVE_DEFINED_VEC_SAT_BINARY_VX_H + +int +main () +{ + unsigned i, k; + T d; + + for (i = 0; i < sizeof (DATA) / sizeof (DATA[0]); i++) + { + RUN_BINARY_VX (&d.x[N], d.b, N); + + for (k = 0; k < N; k++) + if (d.x[k] != d.expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h index 0146138a3c5..1db0f173c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h @@ -253,4 +253,85 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] = }, }; +#define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data +#define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \ + TEST_BINARY_DATA_NAME(T1, T2, NAME) + +#define TEST_ZIP_STRUCT_NAME(T1, T2) test_##T1##_##T2##_zip_s +#define TEST_ZIP_STRUCT_DECL(T1, T2) struct TEST_ZIP_STRUCT_NAME(T1, T2) +#define TEST_ZIP_STRUCT(T1, T2) \ + TEST_ZIP_STRUCT_DECL(T1, T2) \ + { \ + T1 x[N]; \ + T2 b; \ + T1 expect[N]; \ + }; + +TEST_ZIP_STRUCT (uint16_t, uint32_t) + +TEST_ZIP_STRUCT_DECL(uint16_t, uint32_t) \ + TEST_BINARY_DATA_NAME(uint16_t, uint32_t, zip)[] = +{ + { + { /* x. */ + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + 1, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 1, 2, 8, + 65535, 1, 2, 8, + 65535, 1, 2, 8, + 65535, 1, 2, 8, + }, + 65536, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + }, + 65535, /* b. */ + { /* expect. */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { /* x. */ + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + 65535, 16, 8, 1, + }, + 65500, /* b. */ + { /* expect. */ + 35, 0, 0, 0, + 35, 0, 0, 0, + 35, 0, 0, 0, + 35, 0, 0, 0, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c new file mode 100644 index 00000000000..456d99a8d5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip-run.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T1 uint16_t +#define T2 uint32_t + +DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) + +#define DATA TEST_BINARY_DATA_NAME_WRAP(T1, T2, zip) +#define T TEST_ZIP_STRUCT_DECL(T1, T2) +#define RUN_BINARY_VX(x, b, N) RUN_VEC_SAT_U_SUB_FMT_ZIP_WRAP(T1, T2, x, b, N) + +#include "vec_sat_binary_vx.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c new file mode 100644 index 00000000000..cd9ea0e1c76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_uint32_t_fmt_zip: +** ... +** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 +** ... +** vrgather\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */