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X-CSE-ConnectionGUID: qH7B1aBTT4u++cNBdTx4uw== X-CSE-MsgGUID: VcFeODjoR8ig86RkruU1+w== X-IronPort-AV: E=McAfee;i="6700,10204,11127"; a="29149811" X-IronPort-AV: E=Sophos;i="6.09,194,1716274800"; d="scan'208";a="29149811" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2024 01:38:32 -0700 X-CSE-ConnectionGUID: 0KW3DxwVQay1rrqggIlxPQ== X-CSE-MsgGUID: CcohU5lcTwuQN/eD8/0NpA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,194,1716274800"; d="scan'208";a="52109577" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa003.fm.intel.com with ESMTP; 09 Jul 2024 01:38:28 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 22C641007341; Tue, 9 Jul 2024 16:38:28 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] i386: Correct AVX10 CPUID emulation Date: Tue, 9 Jul 2024 16:38:28 +0800 Message-Id: <20240709083828.1050569-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org Hi all, AVX10 Documentaion has specified ecx value as 0 for AVX10 version and vector size under 0x24 subleaf. Although for ecx=1, the bits are all reserved for now, we still need to specify ecx as 0 to avoid dirty value in ecx. Bootstrapped on x86-64-pc-linux-gnu. Ok for trunk and backport to GCC14? Reference: Intel Advanced Vector Extensions 10 (Intel AVX10) Architecture Specification https://cdrdv2.intel.com/v1/dl/getContent/784267 It describes the Intel Advanced Vector Extensions 10 Instruction Set Architecture. Thx, Haochen gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Correct AVX10 CPUID emulation to specify ecx value. --- gcc/common/config/i386/cpuinfo.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 936039725ab..2ae77d335d2 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -998,10 +998,10 @@ get_available_features (struct __processor_model *cpu_model, } } - /* Get Advanced Features at level 0x24 (eax = 0x24). */ + /* Get Advanced Features at level 0x24 (eax = 0x24, ecx = 0). */ if (avx10_set && max_cpuid_level >= 0x24) { - __cpuid (0x24, eax, ebx, ecx, edx); + __cpuid_count (0x24, 0, eax, ebx, ecx, edx); version = ebx & 0xff; if (ebx & bit_AVX10_256) switch (version)