From patchwork Thu Jul 4 09:56:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 1956763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WFBrT4dNsz1xqb for ; Thu, 4 Jul 2024 19:56:57 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 21CFB384A4BC for ; Thu, 4 Jul 2024 09:56:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 545C03858C41 for ; Thu, 4 Jul 2024 09:56:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 545C03858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 545C03858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720086995; cv=none; b=DAWNm4+O+vg0qS8k6+q7ZIYmPTMs+3bHAtK9AeFhRf7cEkNey+hXy6p8NlSTF2OdjP1APAZUBkQ2Ik+oQ3JJIhd5GSQnjKykHi4vBqxaoagbpvHLri+FJERWo4hCxKZcY+MwITttwwtJImgAbMCa8VTS+DfORiF5arCpB1QIeCg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720086995; c=relaxed/simple; bh=BklTIJgxiffcRVC9vd+o5xEH4x5HdvmcihF16hHfO9s=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=TdA3VBzqQW/1AAhSxXNc0/Zd0LC4GzbQyzmdoFmYTPGVVZkUyqk2TS00JvojSMuNOHfOPItMdEgODIfQI9kI6aHymKjhJbjNV2kwIDl/5kX+Q9J+wtYrs+ZLVz5injI91PuSQSckVpBmAlojJ8xGldaFYEbHZf+pgyrIDBxLRG0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxK_DNcYZm2uUAAA--.2779S3; Thu, 04 Jul 2024 17:56:29 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxssTKcYZmlew6AA--.59854S2; Thu, 04 Jul 2024 17:56:28 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH 1/2] LoongArch: TFmode is not allowed to be stored in the float register. Date: Thu, 4 Jul 2024 17:56:23 +0800 Message-Id: <20240704095624.10023-1-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxssTKcYZmlew6AA--.59854S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW7WFWxWr18try7CrW3WFykZwc_yoW5Jr47pr y7uwnxtr48JFZxGrWqq345WFsxAr9rGrW2vaySqry0krZrXryUZF18Kr9FqF1qgay8KrWa qr4rC3Wav3W0v3gCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07jUsqXUUUUU= X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org PR target/115752 gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_hard_regno_mode_ok_uncached): Replace UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE. * config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr115752.c: New test. --- gcc/config/loongarch/loongarch.cc | 2 +- gcc/config/loongarch/loongarch.h | 7 ------- gcc/testsuite/gcc.target/loongarch/pr115752.c | 8 ++++++++ 3 files changed, 9 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/pr115752.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index e2ff2af89e2..803ed0575bd 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -6705,7 +6705,7 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode) if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT) - return size <= UNITS_PER_FPVALUE; + return size <= UNITS_PER_HWFPVALUE; /* Allow integer modes that fit into a single register. We need to put integers into FPRs when using instructions like CVT diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index b9323aba394..5efeae53be6 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -146,13 +146,6 @@ along with GCC; see the file COPYING3. If not see #define UNITS_PER_HWFPVALUE \ (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FP_REG) -/* The largest size of value that can be held in floating-point - registers. */ -#define UNITS_PER_FPVALUE \ - (TARGET_SOFT_FLOAT ? 0 \ - : TARGET_SINGLE_FLOAT ? UNITS_PER_FP_REG \ - : LA_LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) - /* The number of bytes in a double. */ #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) diff --git a/gcc/testsuite/gcc.target/loongarch/pr115752.c b/gcc/testsuite/gcc.target/loongarch/pr115752.c new file mode 100644 index 00000000000..df4bae524f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr115752.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ + +long double +test (long double xx) +{ + __asm ("" :: "f"(xx)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */ + return xx + 1; +} From patchwork Thu Jul 4 09:56:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 1956764 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4WFBrW6GFcz1xqb for ; Thu, 4 Jul 2024 19:56:59 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F479384A440 for ; Thu, 4 Jul 2024 09:56:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id D9B383858403 for ; Thu, 4 Jul 2024 09:56:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D9B383858403 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D9B383858403 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720086998; cv=none; b=oA2kzKB7o7WCqQvpUBmTmQRdg/f31S8BvNRt56eV08KANpHFNfVZgewrM0jf4Kug5eM76uDwn9dUndQnwb1lkh75GSAYrzXD6cCjpIHUeDxL+QNysAOV0pD5g7AqHgk0xp+OnPtGq6iZVugrXSc2fyjNaRqMYXMSbGhZSyQeSS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1720086998; c=relaxed/simple; bh=oYQyaiQ72xtcMES5oTz8ocyZQFg4EevYKInIZMa72RA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=V3OMMZcTTf0KBi1xPxUYOyZIeEuytavzL9LUgBwBGVJZxNK3lPfxxD8ZjliQtrqv2u34CIPKu45h5tvREGfSXeCjDzMUGcgrinbdoa2BQUYD19PGDtnhBhJhyICQqzI0FUPqLDm95lL8ae2+Un/eGcQ7ys2MuOvIztAScKGQX3U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8BxK_DPcYZm3+UAAA--.2781S3; Thu, 04 Jul 2024 17:56:31 +0800 (CST) Received: from loongson-pc.loongson.cn (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxssTKcYZmlew6AA--.59854S3; Thu, 04 Jul 2024 17:56:30 +0800 (CST) From: Lulu Cheng To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn, chenglulu@loongson.cn Subject: [PATCH 2/2] LoongArch: Remove unreachable codes. Date: Thu, 4 Jul 2024 17:56:24 +0800 Message-Id: <20240704095624.10023-2-chenglulu@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240704095624.10023-1-chenglulu@loongson.cn> References: <20240704095624.10023-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxssTKcYZmlew6AA--.59854S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3AF4ktw15JryxCF13ury5WrX_yoWfWF15pr W7uw43tr48JFn3KasYy3yUXw4DCF17GF1aqF9xJrZ2kwnxuw1DX34Fkr9avFy5u3yFgrW7 Zr4UX3WUuFWUGwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07UMpBfUUUUU= X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_split_move): Delete. (loongarch_hard_regno_mode_ok_uncached): Likewise. * config/loongarch/loongarch.md (move_doubleword_fpr): Likewise. (load_low): Likewise. (load_high): Likewise. (store_word): Likewise. (movgr2frh): Likewise. (movfrh2gr): Likewise. --- gcc/config/loongarch/loongarch.cc | 47 +++---------- gcc/config/loongarch/loongarch.md | 109 ------------------------------ 2 files changed, 8 insertions(+), 148 deletions(-) diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 803ed0575bd..ebd418ab115 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -4382,42 +4382,13 @@ loongarch_split_move_p (rtx dest, rtx src) void loongarch_split_move (rtx dest, rtx src) { - rtx low_dest; - gcc_checking_assert (loongarch_split_move_p (dest, src)); if (LSX_SUPPORTED_MODE_P (GET_MODE (dest))) loongarch_split_128bit_move (dest, src); else if (LASX_SUPPORTED_MODE_P (GET_MODE (dest))) loongarch_split_256bit_move (dest, src); - else if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) - { - if (!TARGET_64BIT && GET_MODE (dest) == DImode) - emit_insn (gen_move_doubleword_fprdi (dest, src)); - else if (!TARGET_64BIT && GET_MODE (dest) == DFmode) - emit_insn (gen_move_doubleword_fprdf (dest, src)); - else if (TARGET_64BIT && GET_MODE (dest) == TFmode) - emit_insn (gen_move_doubleword_fprtf (dest, src)); - else - gcc_unreachable (); - } else - { - /* The operation can be split into two normal moves. Decide in - which order to do them. */ - low_dest = loongarch_subword (dest, false); - if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) - { - loongarch_emit_move (loongarch_subword (dest, true), - loongarch_subword (src, true)); - loongarch_emit_move (low_dest, loongarch_subword (src, false)); - } - else - { - loongarch_emit_move (low_dest, loongarch_subword (src, false)); - loongarch_emit_move (loongarch_subword (dest, true), - loongarch_subword (src, true)); - } - } + gcc_unreachable (); } /* Check if adding an integer constant value for a specific mode can be @@ -6688,20 +6659,18 @@ loongarch_hard_regno_mode_ok_uncached (unsigned int regno, machine_mode mode) size = GET_MODE_SIZE (mode); mclass = GET_MODE_CLASS (mode); - if (GP_REG_P (regno) && !LSX_SUPPORTED_MODE_P (mode) + if (GP_REG_P (regno) + && !LSX_SUPPORTED_MODE_P (mode) && !LASX_SUPPORTED_MODE_P (mode)) return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; - /* For LSX, allow TImode and 128-bit vector modes in all FPR. */ - if (FP_REG_P (regno) && LSX_SUPPORTED_MODE_P (mode)) - return true; - - /* FIXED ME: For LASX, allow TImode and 256-bit vector modes in all FPR. */ - if (FP_REG_P (regno) && LASX_SUPPORTED_MODE_P (mode)) - return true; - if (FP_REG_P (regno)) { + /* Allow 128-bit or 256-bit vector modes in all FPR. */ + if (LSX_SUPPORTED_MODE_P (mode) + || LASX_SUPPORTED_MODE_P (mode)) + return true; + if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT || mclass == MODE_VECTOR_FLOAT) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 25c1d323ba0..21890a2d94b 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -400,9 +400,6 @@ (define_mode_iterator X [(SI "!TARGET_64BIT") (DI "TARGET_64BIT")]) ;; 64-bit modes for which we provide move patterns. (define_mode_iterator MOVE64 [DI DF]) -;; 128-bit modes for which we provide move patterns on 64-bit targets. -(define_mode_iterator MOVE128 [TI TF]) - ;; Iterator for sub-32-bit integer modes. (define_mode_iterator SHORT [QI HI]) @@ -421,12 +418,6 @@ (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") (define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT") (DI "TARGET_DOUBLE_FLOAT")]) -;; A mode for which moves involving FPRs may need to be split. -(define_mode_iterator SPLITF - [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") - (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT") - (TF "TARGET_64BIT && TARGET_DOUBLE_FLOAT")]) - ;; A mode for anything with 32 bits or more, and able to be loaded with ;; the same addressing mode as ld.w. (define_mode_iterator LD_AT_LEAST_32_BIT [GPR ANYF]) @@ -2421,41 +2412,6 @@ (define_insn "*movdf_softfloat" [(set_attr "move_type" "move,load,store") (set_attr "mode" "DF")]) -;; Emit a doubleword move in which exactly one of the operands is -;; a floating-point register. We can't just emit two normal moves -;; because of the constraints imposed by the FPU register model; -;; see loongarch_can_change_mode_class for details. Instead, we keep -;; the FPR whole and use special patterns to refer to each word of -;; the other operand. - -(define_expand "move_doubleword_fpr" - [(set (match_operand:SPLITF 0) - (match_operand:SPLITF 1))] - "" -{ - if (FP_REG_RTX_P (operands[0])) - { - rtx low = loongarch_subword (operands[1], 0); - rtx high = loongarch_subword (operands[1], 1); - emit_insn (gen_load_low (operands[0], low)); - if (!TARGET_64BIT) - emit_insn (gen_movgr2frh (operands[0], high, operands[0])); - else - emit_insn (gen_load_high (operands[0], high, operands[0])); - } - else - { - rtx low = loongarch_subword (operands[0], 0); - rtx high = loongarch_subword (operands[0], 1); - emit_insn (gen_store_word (low, operands[1], const0_rtx)); - if (!TARGET_64BIT) - emit_insn (gen_movfrh2gr (high, operands[1])); - else - emit_insn (gen_store_word (high, operands[1], const1_rtx)); - } - DONE; -}) - ;; Clear one FCC register (define_expand "movfcc" @@ -2742,49 +2698,6 @@ (define_insn "2" [(set_attr "type" "fcvt") (set_attr "mode" "")]) -;; Load the low word of operand 0 with operand 1. -(define_insn "load_low" - [(set (match_operand:SPLITF 0 "register_operand" "=f,f") - (unspec:SPLITF [(match_operand: 1 "general_operand" "rJ,m")] - UNSPEC_LOAD_LOW))] - "TARGET_HARD_FLOAT" -{ - operands[0] = loongarch_subword (operands[0], 0); - return loongarch_output_move (operands[0], operands[1]); -} - [(set_attr "move_type" "mgtf,fpload") - (set_attr "mode" "")]) - -;; Load the high word of operand 0 from operand 1, preserving the value -;; in the low word. -(define_insn "load_high" - [(set (match_operand:SPLITF 0 "register_operand" "=f,f") - (unspec:SPLITF [(match_operand: 1 "general_operand" "rJ,m") - (match_operand:SPLITF 2 "register_operand" "0,0")] - UNSPEC_LOAD_HIGH))] - "TARGET_HARD_FLOAT" -{ - operands[0] = loongarch_subword (operands[0], 1); - return loongarch_output_move (operands[0], operands[1]); -} - [(set_attr "move_type" "mgtf,fpload") - (set_attr "mode" "")]) - -;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the -;; high word and 0 to store the low word. -(define_insn "store_word" - [(set (match_operand: 0 "nonimmediate_operand" "=r,m") - (unspec: [(match_operand:SPLITF 1 "register_operand" "f,f") - (match_operand 2 "const_int_operand")] - UNSPEC_STORE_WORD))] - "TARGET_HARD_FLOAT" -{ - operands[1] = loongarch_subword (operands[1], INTVAL (operands[2])); - return loongarch_output_move (operands[0], operands[1]); -} - [(set_attr "move_type" "mftg,fpstore") - (set_attr "mode" "")]) - ;; Thread-Local Storage (define_insn "@got_load_tls_desc" @@ -2876,28 +2789,6 @@ (define_insn "@load_tls" (const_int 4) (const_int 2)))]) -;; Move operand 1 to the high word of operand 0 using movgr2frh.w, preserving the -;; value in the low word. -(define_insn "movgr2frh" - [(set (match_operand:SPLITF 0 "register_operand" "=f") - (unspec:SPLITF [(match_operand: 1 "reg_or_0_operand" "rJ") - (match_operand:SPLITF 2 "register_operand" "0")] - UNSPEC_MOVGR2FRH))] - "TARGET_DOUBLE_FLOAT" - "movgr2frh.w\t%z1,%0" - [(set_attr "move_type" "mgtf") - (set_attr "mode" "")]) - -;; Move high word of operand 1 to operand 0 using movfrh2gr.s. -(define_insn "movfrh2gr" - [(set (match_operand: 0 "register_operand" "=r") - (unspec: [(match_operand:SPLITF 1 "register_operand" "f")] - UNSPEC_MOVFRH2GR))] - "TARGET_DOUBLE_FLOAT" - "movfrh2gr.s\t%0,%1" - [(set_attr "move_type" "mftg") - (set_attr "mode" "")]) - ;; Expand in-line code to clear the instruction cache between operand[0] and ;; operand[1].