From patchwork Thu Jun 27 07:01:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feng Wang X-Patchwork-Id: 1953001 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W8qJd01B1z20X6 for ; Thu, 27 Jun 2024 17:02:40 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 38C123838A1B for ; Thu, 27 Jun 2024 07:02:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmja2lje4os43os4xodqa.icoremail.net (zg8tmja2lje4os43os4xodqa.icoremail.net [206.189.79.184]) by sourceware.org (Postfix) with ESMTP id 07335383938A for ; Thu, 27 Jun 2024 07:01:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 07335383938A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 07335383938A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=206.189.79.184 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719471706; cv=none; b=qnhrpq7f3QaN3coJkkYCvQ7bdg+U8NgmI2IjCFWg1xM0/yXASaDqgQmO+YE9vUX+LljMjqdoY1b5Xa8mdL9VFDGmrfU2akAdd3OzdeUTjI5r1VqKgOn7xwkKX2A4tIRKcMR5O1aJjbyZoMnCfRNgc+FC6C3oxnP1nLjnEleRmsg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1719471706; c=relaxed/simple; bh=02sdNBR3Aw4ljeB3FwbizY98qctWktRFFpe9bMg0Yrg=; h=From:To:Subject:Date:Message-Id; b=q24f3kPGKARJzKZ1AdCSZdaO+eW1ZnzP5EcpzNEZoazyhOhUWHehKsoYVoeYeN7qiIiI96KSfx/3oZ8rtAtbRhU2mYtSbFnOvPEk1a8QRI08jndGYYXvYdKcqR5H9VpiAYVnZXwM0Wu03zXH+VGACzmXV0ym7/aFSiGYZPs3h9c= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgC3ybtPDn1mHA0SAA--.62896S4; Thu, 27 Jun 2024 15:01:36 +0800 (CST) From: Feng Wang To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai, jinma.contrib@gmail.com, Feng Wang Subject: [PATCH 1/3 v2] RISC-V: Add vector type of BFloat16 format Date: Thu, 27 Jun 2024 07:01:19 +0000 Message-Id: <20240627070121.32461-1-wangfeng@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: TQJkCgC3ybtPDn1mHA0SAA--.62896S4 X-Coremail-Antispam: 1UD129KBjvAXoWftw4DWw47Ar4UAw17Xr13Jwb_yoWrGw1UGo WfXrsaka4kJw1Dua4Y9r1kt3409F40vwnrJry8C3W5Xrn7Jr4rZa12vayFyr18Ja9Ig3yU WF1ftr4ruFsxGrn8n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY07AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8 Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26r xl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVCm-wCF 04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r 18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vI r41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr 1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvE x4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUdHUDUUUUU= X-CM-SenderInfo: pzdqwwxhqjqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org v2: Rebase. The vector type of BFloat16 format is added in this patch, subsequent extensions to zvfbfmin and zvfwma need to be based on this patch. gcc/ChangeLog: * config/riscv/genrvv-type-indexer.cc (bfloat16_type): Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX. (bfloat16_wide_type): Ditto. (same_ratio_eew_bf16_type): Ditto. (main): Ditto. * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): (RVV_WHOLE_MODES): Add vector type for BFloat16. (RVV_FRACT_MODE): Ditto. (RVV_NF4_MODES): Ditto. (RVV_NF8_MODES): Ditto. (RVV_NF2_MODES): Ditto. * config/riscv/riscv-vector-builtins-types.def (vbfloat16mf4_t): (vbfloat16mf2_t): Add builtin vector type for BFloat16. (vbfloat16m1_t): Ditto. (vbfloat16m2_t): Ditto. (vbfloat16m4_t): Ditto. (vbfloat16m8_t): Ditto. (vbfloat16mf4x2_t): Ditto. (vbfloat16mf4x3_t): Ditto. (vbfloat16mf4x4_t): Ditto. (vbfloat16mf4x5_t): Ditto. (vbfloat16mf4x6_t): Ditto. (vbfloat16mf4x7_t): Ditto. (vbfloat16mf4x8_t): Ditto. (vbfloat16mf2x2_t): Ditto. (vbfloat16mf2x3_t): Ditto. (vbfloat16mf2x4_t): Ditto. (vbfloat16mf2x5_t): Ditto. (vbfloat16mf2x6_t): Ditto. (vbfloat16mf2x7_t): Ditto. (vbfloat16mf2x8_t): Ditto. (vbfloat16m1x2_t): Ditto. (vbfloat16m1x3_t): Ditto. (vbfloat16m1x4_t): Ditto. (vbfloat16m1x5_t): Ditto. (vbfloat16m1x6_t): Ditto. (vbfloat16m1x7_t): Ditto. (vbfloat16m1x8_t): Ditto. (vbfloat16m2x2_t): Ditto. (vbfloat16m2x3_t): Ditto. (vbfloat16m2x4_t): Ditto. (vbfloat16m4x2_t): Ditto. * config/riscv/riscv-vector-builtins.cc (check_required_extensions): Add required_ext checking for BFloat16. * config/riscv/riscv-vector-builtins.def (vbfloat16mf4_t): Add vector_type for BFloat16 in builtins.def. (vbfloat16mf4x2_t): Ditto. (vbfloat16mf4x3_t): Ditto. (vbfloat16mf4x4_t): Ditto. (vbfloat16mf4x5_t): Ditto. (vbfloat16mf4x6_t): Ditto. (vbfloat16mf4x7_t): Ditto. (vbfloat16mf4x8_t): Ditto. (vbfloat16mf2_t): Ditto. (vbfloat16mf2x2_t): Ditto. (vbfloat16mf2x3_t): Ditto. (vbfloat16mf2x4_t): Ditto. (vbfloat16mf2x5_t): Ditto. (vbfloat16mf2x6_t): Ditto. (vbfloat16mf2x7_t): Ditto. (vbfloat16mf2x8_t): Ditto. (vbfloat16m1_t): Ditto. (vbfloat16m1x2_t): Ditto. (vbfloat16m1x3_t): Ditto. (vbfloat16m1x4_t): Ditto. (vbfloat16m1x5_t): Ditto. (vbfloat16m1x6_t): Ditto. (vbfloat16m1x7_t): Ditto. (vbfloat16m1x8_t): Ditto. (vbfloat16m2_t): Ditto. (vbfloat16m2x2_t): Ditto. (vbfloat16m2x3_t): Ditto. (vbfloat16m2x4_t): Ditto. (vbfloat16m4_t): Ditto. (vbfloat16m4x2_t): Ditto. (vbfloat16m8_t): Ditto. (double_trunc_bfloat_scalar): Add scalar_type def for BFloat16. (double_trunc_bfloat_vector): Add vector_type def for BFloat16. * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_BF_16): Add required defination of BFloat16 ext. * config/riscv/riscv-vector-switch.def (ENTRY): Add vector_type information for BFloat16. (TUPLE_ENTRY): Add tuple vector_type information for BFloat16. --- gcc/config/riscv/genrvv-type-indexer.cc | 115 ++++++++++++++++++ gcc/config/riscv/riscv-modes.def | 30 ++++- .../riscv/riscv-vector-builtins-types.def | 50 ++++++++ gcc/config/riscv/riscv-vector-builtins.cc | 7 +- gcc/config/riscv/riscv-vector-builtins.def | 55 ++++++++- gcc/config/riscv/riscv-vector-builtins.h | 1 + gcc/config/riscv/riscv-vector-switch.def | 36 ++++++ 7 files changed, 291 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc index 27cbd14982c..8626ddeaaa8 100644 --- a/gcc/config/riscv/genrvv-type-indexer.cc +++ b/gcc/config/riscv/genrvv-type-indexer.cc @@ -117,6 +117,42 @@ inttype (unsigned sew, int lmul_log2, unsigned nf, bool unsigned_p) return mode.str (); } +std::string +bfloat16_type (int lmul_log2) +{ + if (!valid_type (16, lmul_log2, /*float_t*/ true)) + return "INVALID"; + + std::stringstream mode; + mode << "vbfloat16" << to_lmul (lmul_log2) << "_t"; + return mode.str (); +} + +std::string +bfloat16_wide_type (int lmul_log2) +{ + if (!valid_type (32, lmul_log2, /*float_t*/ true)) + return "INVALID"; + + std::stringstream mode; + mode << "vfloat32" << to_lmul (lmul_log2) << "_t"; + return mode.str (); +} + +std::string +bfloat16_type (int lmul_log2, unsigned nf) +{ + if (!valid_type (16, lmul_log2, nf, /*float_t*/ true)) + return "INVALID"; + + std::stringstream mode; + mode << "vbfloat16" << to_lmul (lmul_log2); + if (nf > 1) + mode << "x" << nf; + mode << "_t"; + return mode.str (); +} + std::string floattype (unsigned sew, int lmul_log2) { @@ -182,6 +218,15 @@ same_ratio_eew_type (unsigned sew, int lmul_log2, unsigned eew, bool unsigned_p, return inttype (eew, elmul_log2, unsigned_p); } +std::string +same_ratio_eew_bf16_type (unsigned sew, int lmul_log2) +{ + if (sew != 32) + return "INVALID"; + int elmul_log2 = lmul_log2 - 1; + return bfloat16_type (elmul_log2); +} + int main (int argc, const char **argv) { @@ -215,6 +260,8 @@ main (int argc, const char **argv) fprintf (fp, " /*DOUBLE_TRUNC_SIGNED*/ INVALID,\n"); fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED*/ INVALID,\n"); fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED_SCALAR*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ INVALID,\n"); fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ INVALID,\n"); fprintf (fp, " /*FLOAT*/ INVALID,\n"); fprintf (fp, " /*LMUL1*/ INVALID,\n"); @@ -294,6 +341,8 @@ main (int argc, const char **argv) same_ratio_eew_type (sew, lmul_log2, sew / 2, true, false) .c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ INVALID,\n"); fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ %s,\n", same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true) .c_str ()); @@ -341,6 +390,68 @@ main (int argc, const char **argv) inttype (sew, lmul_log2, 1, unsigned_p).c_str ()); fprintf (fp, ")\n"); } + // Build for vbfloat16 + for (int lmul_log2 : {-2, -1, 0, 1, 2, 3}) + for (unsigned nf : {1, 2, 3, 4, 5, 6, 7, 8}) + { + if (!valid_type (16, lmul_log2, nf, /*float_t*/ true)) + continue; + + fprintf (fp, "DEF_RVV_TYPE_INDEX (\n"); + fprintf (fp, " /*VECTOR*/ %s,\n", + bfloat16_type (lmul_log2, nf).c_str ()); + fprintf (fp, " /*MASK*/ %s,\n", maskmode (16, lmul_log2).c_str ()); + fprintf (fp, " /*SIGNED*/ %s,\n", + inttype (16, lmul_log2, /*unsigned_p*/ false).c_str ()); + fprintf (fp, " /*UNSIGNED*/ %s,\n", + inttype (16, lmul_log2, /*unsigned_p*/ true).c_str ()); + for (unsigned eew : {8, 16, 32, 64}) + fprintf ( + fp, " /*EEW%d_INDEX*/ %s,\n", eew, + same_ratio_eew_type (16, lmul_log2, eew, true, false).c_str ()); + fprintf (fp, " /*SHIFT*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC*/ %s,\n", + same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ()); + fprintf (fp, " /*QUAD_TRUNC*/ INVALID,\n"); + fprintf (fp, " /*OCT_TRUNC*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_SCALAR*/ %s,\n", + same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_SIGNED*/ %s,\n", + same_ratio_eew_type (16, lmul_log2, 8, false, false).c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED*/ %s,\n", + same_ratio_eew_type (16, lmul_log2, 8, true, false).c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED_SCALAR*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ %s,\n", + same_ratio_eew_type (16, lmul_log2, 8, false, true).c_str ()); + fprintf (fp, " /*FLOAT*/ INVALID,\n"); + fprintf (fp, " /*LMUL1*/ %s,\n", + bfloat16_type (/*lmul_log2*/ 0).c_str ()); + fprintf (fp, " /*WLMUL1*/ %s,\n", + bfloat16_wide_type (/*lmul_log2*/ 0).c_str ()); + for (unsigned eew : {8, 16, 32, 64}) + fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew); + + for (unsigned boolsize : BOOL_SIZE_LIST) + fprintf (fp, " /*BOOL%d_INTERPRET*/ INVALID,\n", boolsize); + + for (unsigned eew : EEW_SIZE_LIST) + fprintf (fp, " /*SIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew); + + for (unsigned eew : EEW_SIZE_LIST) + fprintf (fp, " /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew); + + for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6}) + { + unsigned multiple_of_lmul = 1 << lmul_log2_offset; + fprintf (fp, " /*X%d_VLMUL_EXT*/ %s,\n", multiple_of_lmul, + bfloat16_type (lmul_log2 + lmul_log2_offset).c_str ()); + } + fprintf (fp, " /*TUPLE_SUBPART*/ %s\n", + bfloat16_type (lmul_log2, 1U).c_str ()); + fprintf (fp, ")\n"); + } // Build for vfloat for (unsigned sew : {16, 32, 64}) for (int lmul_log2 : {-3, -2, -1, 0, 1, 2, 3}) @@ -378,6 +489,10 @@ main (int argc, const char **argv) same_ratio_eew_type (sew, lmul_log2, sew / 2, true, false) .c_str ()); fprintf (fp, " /*DOUBLE_TRUNC_UNSIGNED_SCALAR*/ INVALID,\n"); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT_SCALAR*/ %s,\n", + same_ratio_eew_bf16_type (sew, lmul_log2).c_str ()); + fprintf (fp, " /*DOUBLE_TRUNC_BFLOAT*/ %s,\n", + same_ratio_eew_bf16_type (sew, lmul_log2).c_str ()); fprintf (fp, " /*DOUBLE_TRUNC_FLOAT*/ %s,\n", same_ratio_eew_type (sew, lmul_log2, sew / 2, false, true) .c_str ()); diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index 6de4e440298..b0a78f72754 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -93,6 +93,7 @@ ADJUST_BYTESIZE (RVVMF64BI, riscv_v_adjust_bytesize (RVVMF64BImode, 1)); |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A | |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A | |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A | + |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|RVVMF4BF|N/A | There are the following data types for ELEN = 32. @@ -101,11 +102,13 @@ There are the following data types for ELEN = 32. |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|N/A |N/A | |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A | |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A | - |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | */ + |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | + |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|N/A |N/A | */ #define RVV_WHOLE_MODES(LMUL) \ VECTOR_MODE_WITH_PREFIX (RVVM, INT, QI, LMUL, 0); \ VECTOR_MODE_WITH_PREFIX (RVVM, INT, HI, LMUL, 0); \ + VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, BF, LMUL, 0); \ VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, HF, LMUL, 0); \ VECTOR_MODE_WITH_PREFIX (RVVM, INT, SI, LMUL, 0); \ VECTOR_MODE_WITH_PREFIX (RVVM, FLOAT, SF, LMUL, 0); \ @@ -120,6 +123,8 @@ There are the following data types for ELEN = 32. riscv_v_adjust_nunits (RVVM##LMUL##SImode, false, LMUL, 1)); \ ADJUST_NUNITS (RVVM##LMUL##DI, \ riscv_v_adjust_nunits (RVVM##LMUL##DImode, false, LMUL, 1)); \ + ADJUST_NUNITS (RVVM##LMUL##BF, \ + riscv_v_adjust_nunits (RVVM##LMUL##BFmode, false, LMUL, 1)); \ ADJUST_NUNITS (RVVM##LMUL##HF, \ riscv_v_adjust_nunits (RVVM##LMUL##HFmode, false, LMUL, 1)); \ ADJUST_NUNITS (RVVM##LMUL##SF, \ @@ -131,6 +136,7 @@ There are the following data types for ELEN = 32. ADJUST_ALIGNMENT (RVVM##LMUL##HI, 2); \ ADJUST_ALIGNMENT (RVVM##LMUL##SI, 4); \ ADJUST_ALIGNMENT (RVVM##LMUL##DI, 8); \ + ADJUST_ALIGNMENT (RVVM##LMUL##BF, 2); \ ADJUST_ALIGNMENT (RVVM##LMUL##HF, 2); \ ADJUST_ALIGNMENT (RVVM##LMUL##SF, 4); \ ADJUST_ALIGNMENT (RVVM##LMUL##DF, 8); @@ -153,6 +159,8 @@ RVV_FRACT_MODE (INT, QI, 4, 1) RVV_FRACT_MODE (INT, QI, 8, 1) RVV_FRACT_MODE (INT, HI, 2, 2) RVV_FRACT_MODE (INT, HI, 4, 2) +RVV_FRACT_MODE (FLOAT, BF, 2, 2) +RVV_FRACT_MODE (FLOAT, BF, 4, 2) RVV_FRACT_MODE (FLOAT, HF, 2, 2) RVV_FRACT_MODE (FLOAT, HF, 4, 2) RVV_FRACT_MODE (INT, SI, 2, 4) @@ -174,6 +182,9 @@ RVV_FRACT_MODE (FLOAT, SF, 2, 4) VECTOR_MODE_WITH_PREFIX (RVVMF4x, INT, HI, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVMF2x, INT, HI, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM1x, INT, HI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, BF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, BF, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, BF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVMF4x, FLOAT, HF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVMF2x, FLOAT, HF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM1x, FLOAT, HF, NF, 1); \ @@ -198,6 +209,12 @@ RVV_FRACT_MODE (FLOAT, SF, 2, 4) riscv_v_adjust_nunits (RVVMF2x##NF##HImode, true, 2, NF)); \ ADJUST_NUNITS (RVVM1x##NF##HI, \ riscv_v_adjust_nunits (RVVM1x##NF##HImode, false, 1, NF)); \ + ADJUST_NUNITS (RVVMF4x##NF##BF, \ + riscv_v_adjust_nunits (RVVMF4x##NF##BFmode, true, 4, NF)); \ + ADJUST_NUNITS (RVVMF2x##NF##BF, \ + riscv_v_adjust_nunits (RVVMF2x##NF##BFmode, true, 2, NF)); \ + ADJUST_NUNITS (RVVM1x##NF##BF, \ + riscv_v_adjust_nunits (RVVM1x##NF##BFmode, false, 1, NF)); \ ADJUST_NUNITS (RVVMF4x##NF##HF, \ riscv_v_adjust_nunits (RVVMF4x##NF##HFmode, true, 4, NF)); \ ADJUST_NUNITS (RVVMF2x##NF##HF, \ @@ -224,6 +241,9 @@ RVV_FRACT_MODE (FLOAT, SF, 2, 4) ADJUST_ALIGNMENT (RVVMF4x##NF##HI, 2); \ ADJUST_ALIGNMENT (RVVMF2x##NF##HI, 2); \ ADJUST_ALIGNMENT (RVVM1x##NF##HI, 2); \ + ADJUST_ALIGNMENT (RVVMF4x##NF##BF, 2); \ + ADJUST_ALIGNMENT (RVVMF2x##NF##BF, 2); \ + ADJUST_ALIGNMENT (RVVM1x##NF##BF, 2); \ ADJUST_ALIGNMENT (RVVMF4x##NF##HF, 2); \ ADJUST_ALIGNMENT (RVVMF2x##NF##HF, 2); \ ADJUST_ALIGNMENT (RVVM1x##NF##HF, 2); \ @@ -245,6 +265,7 @@ RVV_NF8_MODES (2) #define RVV_NF4_MODES(NF) \ VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, QI, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, HI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, BF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, HF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM2x, INT, SI, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM2x, FLOAT, SF, NF, 1); \ @@ -255,6 +276,8 @@ RVV_NF8_MODES (2) riscv_v_adjust_nunits (RVVM2x##NF##QImode, false, 2, NF)); \ ADJUST_NUNITS (RVVM2x##NF##HI, \ riscv_v_adjust_nunits (RVVM2x##NF##HImode, false, 2, NF)); \ + ADJUST_NUNITS (RVVM2x##NF##BF, \ + riscv_v_adjust_nunits (RVVM2x##NF##BFmode, false, 2, NF)); \ ADJUST_NUNITS (RVVM2x##NF##HF, \ riscv_v_adjust_nunits (RVVM2x##NF##HFmode, false, 2, NF)); \ ADJUST_NUNITS (RVVM2x##NF##SI, \ @@ -268,6 +291,7 @@ RVV_NF8_MODES (2) \ ADJUST_ALIGNMENT (RVVM2x##NF##QI, 1); \ ADJUST_ALIGNMENT (RVVM2x##NF##HI, 2); \ + ADJUST_ALIGNMENT (RVVM2x##NF##BF, 2); \ ADJUST_ALIGNMENT (RVVM2x##NF##HF, 2); \ ADJUST_ALIGNMENT (RVVM2x##NF##SI, 4); \ ADJUST_ALIGNMENT (RVVM2x##NF##SF, 4); \ @@ -281,6 +305,7 @@ RVV_NF4_MODES (4) #define RVV_NF2_MODES(NF) \ VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, QI, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, HI, NF, 1); \ + VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, BF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, HF, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM4x, INT, SI, NF, 1); \ VECTOR_MODE_WITH_PREFIX (RVVM4x, FLOAT, SF, NF, 1); \ @@ -291,6 +316,8 @@ RVV_NF4_MODES (4) riscv_v_adjust_nunits (RVVM4x##NF##QImode, false, 4, NF)); \ ADJUST_NUNITS (RVVM4x##NF##HI, \ riscv_v_adjust_nunits (RVVM4x##NF##HImode, false, 4, NF)); \ + ADJUST_NUNITS (RVVM4x##NF##BF, \ + riscv_v_adjust_nunits (RVVM4x##NF##BFmode, false, 4, NF)); \ ADJUST_NUNITS (RVVM4x##NF##HF, \ riscv_v_adjust_nunits (RVVM4x##NF##HFmode, false, 4, NF)); \ ADJUST_NUNITS (RVVM4x##NF##SI, \ @@ -304,6 +331,7 @@ RVV_NF4_MODES (4) \ ADJUST_ALIGNMENT (RVVM4x##NF##QI, 1); \ ADJUST_ALIGNMENT (RVVM4x##NF##HI, 2); \ + ADJUST_ALIGNMENT (RVVM4x##NF##BF, 2); \ ADJUST_ALIGNMENT (RVVM4x##NF##HF, 2); \ ADJUST_ALIGNMENT (RVVM4x##NF##SI, 4); \ ADJUST_ALIGNMENT (RVVM4x##NF##SF, 4); \ diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index 61019a56844..e7fca4cca79 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -397,6 +397,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_F_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_F_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_F_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_F_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_F_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_F_OPS (vbfloat16m8_t, RVV_REQUIRE_ELEN_BF_16) + DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) @@ -999,6 +1006,11 @@ DEF_RVV_X2_VLMUL_EXT_OPS (vuint32m4_t, 0) DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_X2_VLMUL_EXT_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_X2_VLMUL_EXT_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_X2_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) @@ -1040,6 +1052,10 @@ DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m1_t, 0) DEF_RVV_X4_VLMUL_EXT_OPS (vuint32m2_t, 0) DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) DEF_RVV_X4_VLMUL_EXT_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_X4_VLMUL_EXT_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_X4_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) @@ -1070,6 +1086,9 @@ DEF_RVV_X8_VLMUL_EXT_OPS (vuint16m1_t, 0) DEF_RVV_X8_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X8_VLMUL_EXT_OPS (vuint32m1_t, 0) DEF_RVV_X8_VLMUL_EXT_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_X8_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_X8_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_X8_VLMUL_EXT_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_X8_VLMUL_EXT_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) @@ -1089,6 +1108,8 @@ DEF_RVV_X16_VLMUL_EXT_OPS (vuint8mf2_t, 0) DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X16_VLMUL_EXT_OPS (vuint16mf2_t, 0) DEF_RVV_X16_VLMUL_EXT_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_X16_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_X16_VLMUL_EXT_OPS (vbfloat16mf2_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X16_VLMUL_EXT_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_X16_VLMUL_EXT_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) @@ -1099,6 +1120,7 @@ DEF_RVV_X32_VLMUL_EXT_OPS (vint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X32_VLMUL_EXT_OPS (vuint8mf4_t, 0) DEF_RVV_X32_VLMUL_EXT_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_X32_VLMUL_EXT_OPS (vbfloat16mf4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X32_VLMUL_EXT_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_X64_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) @@ -1112,6 +1134,7 @@ DEF_RVV_LMUL1_OPS (vuint8m1_t, 0) DEF_RVV_LMUL1_OPS (vuint16m1_t, 0) DEF_RVV_LMUL1_OPS (vuint32m1_t, 0) DEF_RVV_LMUL1_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_LMUL1_OPS (vbfloat16m1_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_LMUL1_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_LMUL1_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) DEF_RVV_LMUL1_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64) @@ -1124,6 +1147,7 @@ DEF_RVV_LMUL2_OPS (vuint8m2_t, 0) DEF_RVV_LMUL2_OPS (vuint16m2_t, 0) DEF_RVV_LMUL2_OPS (vuint32m2_t, 0) DEF_RVV_LMUL2_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_LMUL2_OPS (vbfloat16m2_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_LMUL2_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16) DEF_RVV_LMUL2_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32) DEF_RVV_LMUL2_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) @@ -1137,6 +1161,7 @@ DEF_RVV_LMUL4_OPS (vuint16m4_t, 0) DEF_RVV_LMUL4_OPS (vuint32m4_t, 0) DEF_RVV_LMUL4_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_LMUL4_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16) +DEF_RVV_LMUL4_OPS (vbfloat16m4_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_LMUL4_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32) DEF_RVV_LMUL4_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) @@ -1312,6 +1337,31 @@ DEF_RVV_TUPLE_OPS (vint64m2x4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_TUPLE_OPS (vuint64m2x4_t, RVV_REQUIRE_ELEN_64) DEF_RVV_TUPLE_OPS (vint64m4x2_t, RVV_REQUIRE_ELEN_64) DEF_RVV_TUPLE_OPS (vuint64m4x2_t, RVV_REQUIRE_ELEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x2_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x3_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x4_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x5_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x6_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x7_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf4x8_t, RVV_REQUIRE_ELEN_BF_16 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x3_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x4_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x5_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x6_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x7_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16mf2x8_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x3_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x4_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x5_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x6_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x7_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m1x8_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m2x2_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m2x3_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m2x4_t, RVV_REQUIRE_ELEN_BF_16) +DEF_RVV_TUPLE_OPS (vbfloat16m4x2_t, RVV_REQUIRE_ELEN_BF_16) DEF_RVV_TUPLE_OPS (vfloat16mf4x2_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_TUPLE_OPS (vfloat16mf4x3_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_TUPLE_OPS (vfloat16mf4x4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index c08d87a2680..720436dfbc9 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -2808,7 +2808,8 @@ static CONSTEXPR const function_type_info function_types[] = { VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \ EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, OCT_TRUNC, \ DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \ - DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ + DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \ + DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \ BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \ BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \ @@ -2845,6 +2846,8 @@ static CONSTEXPR const function_type_info function_types[] = { VECTOR_TYPE_##DOUBLE_TRUNC_SIGNED, \ VECTOR_TYPE_##DOUBLE_TRUNC_UNSIGNED, \ VECTOR_TYPE_##DOUBLE_TRUNC_UNSIGNED_SCALAR, \ + VECTOR_TYPE_##DOUBLE_TRUNC_BFLOAT_SCALAR, \ + VECTOR_TYPE_##DOUBLE_TRUNC_BFLOAT, \ VECTOR_TYPE_##DOUBLE_TRUNC_FLOAT, \ VECTOR_TYPE_##FLOAT, \ VECTOR_TYPE_##LMUL1, \ @@ -3284,6 +3287,8 @@ check_required_extensions (const function_instance &instance) uint64_t riscv_isa_flags = 0; + if (TARGET_VECTOR_ELEN_BF_16) + riscv_isa_flags |= RVV_REQUIRE_ELEN_BF_16; if (TARGET_VECTOR_ELEN_FP_16) riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16; if (TARGET_VECTOR_ELEN_FP_32) diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def index 784b54c81a4..97f329d11eb 100644 --- a/gcc/config/riscv/riscv-vector-builtins.def +++ b/gcc/config/riscv/riscv-vector-builtins.def @@ -72,7 +72,8 @@ along with GCC; see the file COPYING3. If not see VECTOR, MASK, SIGNED, UNSIGNED, EEW8_INDEX, EEW16_INDEX, EEW32_INDEX, \ EEW64_INDEX, SHIFT, DOUBLE_TRUNC, QUAD_TRUNC, OCT_TRUNC, \ DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED, \ - DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ + DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_BFLOAT_SCALAR, \ + DOUBLE_TRUNC_BFLOAT, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1, \ EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET, \ BOOL1_INTERPRET, BOOL2_INTERPRET, BOOL4_INTERPRET, BOOL8_INTERPRET, \ BOOL16_INTERPRET, BOOL32_INTERPRET, BOOL64_INTERPRET, \ @@ -436,6 +437,56 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, RVVM8DI, _i64m8, _i64, DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, RVVM8DI, _u64m8, _u64, _e64m8) +/* Enabled if TARGET_VECTOR_ELEN_BF_16 && (TARGET_ZVFBFMIN or TARGET_ZVFBFWMA). */ +/* LMUL = 1/4. */ +DEF_RVV_TYPE (vbfloat16mf4_t, 19, __rvv_bfloat16mf4_t, bfloat16, RVVMF4BF, _bf16mf4, + _bf16, _e16mf4) +/* Define tuple types for SEW = 16, LMUL = MF4. */ +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x2_t, 21, __rvv_bfloat16mf4x2_t, vbfloat16mf4_t, bfloat16, 2, _bf16mf4x2) +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x3_t, 21, __rvv_bfloat16mf4x3_t, vbfloat16mf4_t, bfloat16, 3, _bf16mf4x3) +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x4_t, 21, __rvv_bfloat16mf4x4_t, vbfloat16mf4_t, bfloat16, 4, _bf16mf4x4) +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x5_t, 21, __rvv_bfloat16mf4x5_t, vbfloat16mf4_t, bfloat16, 5, _bf16mf4x5) +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x6_t, 21, __rvv_bfloat16mf4x6_t, vbfloat16mf4_t, bfloat16, 6, _bf16mf4x6) +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x7_t, 21, __rvv_bfloat16mf4x7_t, vbfloat16mf4_t, bfloat16, 7, _bf16mf4x7) +DEF_RVV_TUPLE_TYPE (vbfloat16mf4x8_t, 21, __rvv_bfloat16mf4x8_t, vbfloat16mf4_t, bfloat16, 8, _bf16mf4x8) +/* LMUL = 1/2. */ +DEF_RVV_TYPE (vbfloat16mf2_t, 19, __rvv_bfloat16mf2_t, bfloat16, RVVMF2BF, _bf16mf2, + _bf16, _e16mf2) +/* Define tuple types for SEW = 16, LMUL = MF2. */ +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x2_t, 21, __rvv_bfloat16mf2x2_t, vbfloat16mf2_t, bfloat16, 2, _bf16mf2x2) +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x3_t, 21, __rvv_bfloat16mf2x3_t, vbfloat16mf2_t, bfloat16, 3, _bf16mf2x3) +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x4_t, 21, __rvv_bfloat16mf2x4_t, vbfloat16mf2_t, bfloat16, 4, _bf16mf2x4) +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x5_t, 21, __rvv_bfloat16mf2x5_t, vbfloat16mf2_t, bfloat16, 5, _bf16mf2x5) +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x6_t, 21, __rvv_bfloat16mf2x6_t, vbfloat16mf2_t, bfloat16, 6, _bf16mf2x6) +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x7_t, 21, __rvv_bfloat16mf2x7_t, vbfloat16mf2_t, bfloat16, 7, _bf16mf2x7) +DEF_RVV_TUPLE_TYPE (vbfloat16mf2x8_t, 21, __rvv_bfloat16mf2x8_t, vbfloat16mf2_t, bfloat16, 8, _bf16mf2x8) +/* LMUL = 1. */ +DEF_RVV_TYPE (vbfloat16m1_t, 18, __rvv_bfloat16m1_t, bfloat16, RVVM1BF, _bf16m1, + _bf16, _e16m1) +/* Define tuple types for SEW = 16, LMUL = M1. */ +DEF_RVV_TUPLE_TYPE (vbfloat16m1x2_t, 20, __rvv_bfloat16m1x2_t, vbfloat16m1_t, bfloat16, 2, _bf16m1x2) +DEF_RVV_TUPLE_TYPE (vbfloat16m1x3_t, 20, __rvv_bfloat16m1x3_t, vbfloat16m1_t, bfloat16, 3, _bf16m1x3) +DEF_RVV_TUPLE_TYPE (vbfloat16m1x4_t, 20, __rvv_bfloat16m1x4_t, vbfloat16m1_t, bfloat16, 4, _bf16m1x4) +DEF_RVV_TUPLE_TYPE (vbfloat16m1x5_t, 20, __rvv_bfloat16m1x5_t, vbfloat16m1_t, bfloat16, 5, _bf16m1x5) +DEF_RVV_TUPLE_TYPE (vbfloat16m1x6_t, 20, __rvv_bfloat16m1x6_t, vbfloat16m1_t, bfloat16, 6, _bf16m1x6) +DEF_RVV_TUPLE_TYPE (vbfloat16m1x7_t, 20, __rvv_bfloat16m1x7_t, vbfloat16m1_t, bfloat16, 7, _bf16m1x7) +DEF_RVV_TUPLE_TYPE (vbfloat16m1x8_t, 20, __rvv_bfloat16m1x8_t, vbfloat16m1_t, bfloat16, 8, _bf16m1x8) +/* LMUL = 2. */ +DEF_RVV_TYPE (vbfloat16m2_t, 18, __rvv_bfloat16m2_t, bfloat16, RVVM2BF, _bf16m2, + _bf16, _e16m2) +/* Define tuple types for SEW = 16, LMUL = M2. */ +DEF_RVV_TUPLE_TYPE (vbfloat16m2x2_t, 20, __rvv_bfloat16m2x2_t, vbfloat16m2_t, bfloat16, 2, _bf16m2x2) +DEF_RVV_TUPLE_TYPE (vbfloat16m2x3_t, 20, __rvv_bfloat16m2x3_t, vbfloat16m2_t, bfloat16, 3, _bf16m2x3) +DEF_RVV_TUPLE_TYPE (vbfloat16m2x4_t, 20, __rvv_bfloat16m2x4_t, vbfloat16m2_t, bfloat16, 4, _bf16m2x4) +/* LMUL = 4. */ +DEF_RVV_TYPE (vbfloat16m4_t, 18, __rvv_bfloat16m4_t, bfloat16, RVVM4BF, _bf16m4, + _bf16, _e16m4) +/* Define tuple types for SEW = 16, LMUL = M4. */ +DEF_RVV_TUPLE_TYPE (vbfloat16m4x2_t, 20, __rvv_bfloat16m4x2_t, vbfloat16m4_t, bfloat16, 2, _bf16m4x2) +/* LMUL = 8. */ +DEF_RVV_TYPE (vbfloat16m8_t, 18, __rvv_bfloat16m8_t, bfloat16, RVVM8BF, _bf16m8, + _bf16, _e16m8) + /* Enabled if TARGET_VECTOR_ELEN_FP_16 && (TARGET_ZVFH or TARGET_ZVFHMIN). */ /* LMUL = 1/4. */ DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, RVVMF4HF, _f16mf4, @@ -630,6 +681,8 @@ DEF_RVV_BASE_TYPE (double_trunc_scalar, get_scalar_type (type_idx)) DEF_RVV_BASE_TYPE (double_trunc_signed_vector, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (double_trunc_unsigned_vector, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (double_trunc_unsigned_scalar, get_scalar_type (type_idx)) +DEF_RVV_BASE_TYPE (double_trunc_bfloat_scalar, get_scalar_type (type_idx)) +DEF_RVV_BASE_TYPE (double_trunc_bfloat_vector, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (double_trunc_float_vector, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (float_vector, get_vector_type (type_idx)) DEF_RVV_BASE_TYPE (lmul1_vector, get_vector_type (type_idx)) diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 05d18ae1322..56dbe2cf0e2 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -109,6 +109,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; #define RVV_REQUIRE_FULL_V (1 << 4) /* Require Full 'V' extension. */ #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5) /* Require TARGET_MIN_VLEN >= 64. */ #define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32. */ +#define RVV_REQUIRE_ELEN_BF_16 (1 << 7) /* Require BF16. */ /* Enumerates the required extensions. */ enum required_ext diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def index 452283b7416..de72e415fe8 100644 --- a/gcc/config/riscv/riscv-vector-switch.def +++ b/gcc/config/riscv/riscv-vector-switch.def @@ -43,6 +43,7 @@ Encode SEW and LMUL into data types. |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A | |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A | |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A | + |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|RVVMF4BF|N/A | There are the following data types for ELEN = 32. @@ -52,6 +53,7 @@ There are the following data types for ELEN = 32. |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A | |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A | |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | + |BF |RVVM1BF|RVVM2BF|RVVM4BF|RVVM8BF|RVVMF2BF|N/A |N/A | Encode the ratio of SEW/LMUL into the mask types. There are the following mask types. @@ -93,6 +95,14 @@ ENTRY (RVVM1HI, true, LMUL_1, 16) ENTRY (RVVMF2HI, !TARGET_XTHEADVECTOR, LMUL_F2, 32) ENTRY (RVVMF4HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, LMUL_F4, 64) +/* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_BF_16. */ +ENTRY (RVVM8BF, TARGET_VECTOR_ELEN_BF_16, LMUL_8, 2) +ENTRY (RVVM4BF, TARGET_VECTOR_ELEN_BF_16, LMUL_4, 4) +ENTRY (RVVM2BF, TARGET_VECTOR_ELEN_BF_16, LMUL_2, 8) +ENTRY (RVVM1BF, TARGET_VECTOR_ELEN_BF_16, LMUL_1, 16) +ENTRY (RVVMF2BF, TARGET_VECTOR_ELEN_BF_16, LMUL_F2, 32) +ENTRY (RVVMF4BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, LMUL_F4, 64) + /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_16. */ ENTRY (RVVM8HF, TARGET_VECTOR_ELEN_FP_16, LMUL_8, 2) ENTRY (RVVM4HF, TARGET_VECTOR_ELEN_FP_16, LMUL_4, 4) @@ -198,6 +208,32 @@ TUPLE_ENTRY (RVVM1x2HI, true, RVVM1HI, 2, LMUL_1, 16) TUPLE_ENTRY (RVVMF2x2HI, !TARGET_XTHEADVECTOR, RVVMF2HI, 2, LMUL_F2, 32) TUPLE_ENTRY (RVVMF4x2HI, TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HI, 2, LMUL_F4, 64) +TUPLE_ENTRY (RVVM1x8BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 8, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x8BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 8, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x8BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 8, LMUL_F4, 64) +TUPLE_ENTRY (RVVM1x7BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 7, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x7BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 7, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x7BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 7, LMUL_F4, 64) +TUPLE_ENTRY (RVVM1x6BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 6, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x6BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 6, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x6BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 6, LMUL_F4, 64) +TUPLE_ENTRY (RVVM1x5BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 5, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x5BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 5, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x5BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 5, LMUL_F4, 64) +TUPLE_ENTRY (RVVM2x4BF, TARGET_VECTOR_ELEN_BF_16, RVVM2BF, 4, LMUL_2, 8) +TUPLE_ENTRY (RVVM1x4BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 4, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x4BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 4, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x4BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 4, LMUL_F4, 64) +TUPLE_ENTRY (RVVM2x3BF, TARGET_VECTOR_ELEN_BF_16, RVVM2BF, 3, LMUL_2, 8) +TUPLE_ENTRY (RVVM1x3BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 3, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x3BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 3, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x3BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 3, LMUL_F4, 64) +TUPLE_ENTRY (RVVM4x2BF, TARGET_VECTOR_ELEN_BF_16, RVVM4BF, 2, LMUL_4, 4) +TUPLE_ENTRY (RVVM2x2BF, TARGET_VECTOR_ELEN_BF_16, RVVM2BF, 2, LMUL_2, 8) +TUPLE_ENTRY (RVVM1x2BF, TARGET_VECTOR_ELEN_BF_16, RVVM1BF, 2, LMUL_1, 16) +TUPLE_ENTRY (RVVMF2x2BF, TARGET_VECTOR_ELEN_BF_16, RVVMF2BF, 2, LMUL_F2, 32) +TUPLE_ENTRY (RVVMF4x2BF, TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32, RVVMF4BF, 2, LMUL_F4, 64) + TUPLE_ENTRY (RVVM1x8HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 8, LMUL_1, 16) TUPLE_ENTRY (RVVMF2x8HF, TARGET_VECTOR_ELEN_FP_16 && !TARGET_XTHEADVECTOR, RVVMF2HF, 8, LMUL_F2, 32) TUPLE_ENTRY (RVVMF4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && !TARGET_XTHEADVECTOR, RVVMF4HF, 8, LMUL_F4, 64) From patchwork Thu Jun 27 07:01:20 2024 Content-Type: text/plain; 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Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic functions are added by this patch. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f): Add 'Zvfbfmin' intrinsic in bases. (class vfwcvtbf16_f): Ditto. (class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases. (BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'. * config/riscv/riscv-vector-builtins-bases.h: Add declaration for 'Zvfbfmin' and 'Zvfbfwma'. * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS): Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'. (vfncvtbf16_f): Ditto. (vfncvtbf16_f_frm): Ditto. (vfwcvtbf16_f): Ditto. (vfwmaccbf16): Ditto. (vfwmaccbf16_frm): Ditto. * config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p): Add vector intrinsic build judgment for BFloat16. (build_all): Ditto. (BASE_NAME_MAX_LEN): Adjust max length. * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS): Add new operand type for BFloat16. (vfloat32mf2_t): Ditto. (vfloat32m1_t): Ditto. (vfloat32m2_t): Ditto. (vfloat32m4_t): Ditto. (vfloat32m8_t): Ditto. * config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto. (validate_instance_type_required_extensions): Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'. * config/riscv/riscv-vector-builtins.h (enum required_ext): Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'. (reqired_ext_to_isa_name): Ditto. (required_extensions_specified): Ditto. (struct function_group_info): Add match case for 'Zvfbfmin' and 'Zvfbfwma'. * config/riscv/riscv.cc (riscv_validate_vector_type): Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'. --- .../riscv/riscv-vector-builtins-bases.cc | 69 +++++++++++++++++++ .../riscv/riscv-vector-builtins-bases.h | 7 ++ .../riscv/riscv-vector-builtins-functions.def | 15 ++++ .../riscv/riscv-vector-builtins-shapes.cc | 31 ++++++++- .../riscv/riscv-vector-builtins-types.def | 13 ++++ gcc/config/riscv/riscv-vector-builtins.cc | 67 ++++++++++++++++++ gcc/config/riscv/riscv-vector-builtins.h | 34 ++++++--- gcc/config/riscv/riscv.cc | 5 +- 8 files changed, 227 insertions(+), 14 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 6483faba39c..193392fbcc2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2417,6 +2417,60 @@ public: } }; +/* Implements vfncvtbf16_f. */ +template +class vfncvtbf16_f : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + + bool may_require_frm_p () const override { return true; } + + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_trunc_to_bf16 (e.vector_mode ())); + } +}; + +/* Implements vfwcvtbf16_f. */ +class vfwcvtbf16_f : public function_base +{ +public: + rtx expand (function_expander &e) const override + { + return e.use_exact_insn (code_for_pred_extend_bf16_to (e.vector_mode ())); + } +}; + +/* Implements vfwmaccbf16. */ +template +class vfwmaccbf16 : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override + { + return FRM_OP == HAS_FRM; + } + + bool may_require_frm_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_bf16_mul_scalar (e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_bf16_mul (e.vector_mode ())); + gcc_unreachable (); + } +}; + static CONSTEXPR const vsetvl vsetvl_obj; static CONSTEXPR const vsetvl vsetvlmax_obj; static CONSTEXPR const loadstore vle_obj; @@ -2734,6 +2788,14 @@ static CONSTEXPR const crypto_vv vsm4r_obj; static CONSTEXPR const vsm3me vsm3me_obj; static CONSTEXPR const vaeskf2_vsm3c vsm3c_obj; +/* Zvfbfmin */ +static CONSTEXPR const vfncvtbf16_f vfncvtbf16_f_obj; +static CONSTEXPR const vfncvtbf16_f vfncvtbf16_f_frm_obj; +static CONSTEXPR const vfwcvtbf16_f vfwcvtbf16_f_obj; +/* Zvfbfwma; */ +static CONSTEXPR const vfwmaccbf16 vfwmaccbf16_obj; +static CONSTEXPR const vfwmaccbf16 vfwmaccbf16_frm_obj; + /* Declare the function base NAME, pointing it to an instance of class _obj. */ #define BASE(NAME) \ @@ -3054,4 +3116,11 @@ BASE (vsm4k) BASE (vsm4r) BASE (vsm3me) BASE (vsm3c) +/* Zvfbfmin */ +BASE (vfncvtbf16_f) +BASE (vfncvtbf16_f_frm) +BASE (vfwcvtbf16_f) +/* Zvfbfwma */ +BASE (vfwmaccbf16) +BASE (vfwmaccbf16_frm) } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index 1f2c94d3541..af1cb1af50f 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -339,6 +339,13 @@ extern const function_base *const vsm4k; extern const function_base *const vsm4r; extern const function_base *const vsm3me; extern const function_base *const vsm3c; +/* Zvfbfmin*/ +extern const function_base *const vfncvtbf16_f; +extern const function_base *const vfncvtbf16_f_frm; +extern const function_base *const vfwcvtbf16_f; +/* Zvfbfwma */ +extern const function_base *const vfwmaccbf16; +extern const function_base *const vfwmaccbf16_frm; } } // end namespace riscv_vector diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index f742c98be8a..b69cf3cae29 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -747,4 +747,19 @@ DEF_RVV_FUNCTION (vsm4r, crypto_vv, none_tu_preds, u_vvs_crypto_sew32_lmul_x16_o DEF_RVV_FUNCTION (vsm3me, no_mask_policy, none_tu_preds, u_vvv_crypto_sew32_ops) DEF_RVV_FUNCTION (vsm3c, crypto_vi, none_tu_preds, u_vvv_size_crypto_sew32_ops) #undef REQUIRED_EXTENSIONS + +//Zvfbfmin +#define REQUIRED_EXTENSIONS ZVFBFMIN_EXT +DEF_RVV_FUNCTION (vfncvtbf16_f, narrow_alu, full_preds, f32_to_bf16_f_w_ops) +DEF_RVV_FUNCTION (vfncvtbf16_f_frm, narrow_alu_frm, full_preds, f32_to_bf16_f_w_ops) +DEF_RVV_FUNCTION (vfwcvtbf16_f, alu, full_preds, bf16_to_f32_f_v_ops) +#undef REQUIRED_EXTENSIONS + +/* Zvfbfwma */ +#define REQUIRED_EXTENSIONS ZVFBFWMA_EXT +DEF_RVV_FUNCTION (vfwmaccbf16, alu, full_preds, f32_wwvv_ops) +DEF_RVV_FUNCTION (vfwmaccbf16, alu, full_preds, f32_wwfv_ops) +DEF_RVV_FUNCTION (vfwmaccbf16_frm, alu_frm, full_preds, f32_wwvv_ops) +DEF_RVV_FUNCTION (vfwmaccbf16_frm, alu_frm, full_preds, f32_wwfv_ops) +#undef REQUIRED_EXTENSIONS #undef DEF_RVV_FUNCTION diff --git a/gcc/config/riscv/riscv-vector-builtins-shapes.cc b/gcc/config/riscv/riscv-vector-builtins-shapes.cc index a3ffa92e967..33395414aae 100644 --- a/gcc/config/riscv/riscv-vector-builtins-shapes.cc +++ b/gcc/config/riscv/riscv-vector-builtins-shapes.cc @@ -78,6 +78,30 @@ build_one (function_builder &b, const function_group_info &group, argument_types, group.required_extensions); } +/* Determine whether the intrinsic supports the currently + processed vector type */ +static bool +supports_vectype_p (const function_group_info &group, unsigned int vec_type_idx) +{ + int index = group.ops_infos.types[vec_type_idx].index; + if (index < VECTOR_TYPE_vbfloat16mf4_t || index > VECTOR_TYPE_vbfloat16m8_t) + return true; + /* Only judge for bf16 vector type */ + if (*group.shape == shapes::loadstore + || *group.shape == shapes::indexed_loadstore + || *group.shape == shapes::vundefined + || *group.shape == shapes::misc + || *group.shape == shapes::vset + || *group.shape == shapes::vget + || *group.shape == shapes::vcreate + || *group.shape == shapes::fault_load + || *group.shape == shapes::seg_loadstore + || *group.shape == shapes::seg_indexed_loadstore + || *group.shape == shapes::seg_fault_load) + return true; + return false; +} + /* Add a function instance for every operand && predicate && args combination in GROUP. Take the function base name from GROUP && operand suffix from operand_suffixes && mode suffix from type_suffixes && predication @@ -91,7 +115,10 @@ build_all (function_builder &b, const function_group_info &group) for (unsigned int vec_type_idx = 0; group.ops_infos.types[vec_type_idx].index != NUM_VECTOR_TYPES; ++vec_type_idx) - build_one (b, group, pred_idx, vec_type_idx); + { + if (supports_vectype_p (group, vec_type_idx)) + build_one (b, group, pred_idx, vec_type_idx); + } } /* Declare the function shape NAME, pointing it to an instance @@ -100,7 +127,7 @@ build_all (function_builder &b, const function_group_info &group) static CONSTEXPR const DEF##_def VAR##_obj; \ namespace shapes { const function_shape *const VAR = &VAR##_obj; } -#define BASE_NAME_MAX_LEN 16 +#define BASE_NAME_MAX_LEN 17 /* Base class for build. */ struct build_base : public function_shape diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def b/gcc/config/riscv/riscv-vector-builtins-types.def index e7fca4cca79..e85ca27bcf5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-types.def +++ b/gcc/config/riscv/riscv-vector-builtins-types.def @@ -133,6 +133,12 @@ along with GCC; see the file COPYING3. If not see #define DEF_RVV_WCONVERT_F_OPS(TYPE, REQUIRE) #endif +/* Use "DEF_RVV_F32_OPS" macro include all float32 vector type that will be + used in the bfloat16 intrinsic */ +#ifndef DEF_RVV_F32_OPS +#define DEF_RVV_F32_OPS(TYPE, REQUIRE) +#endif + /* Use "DEF_RVV_WI_OPS" macro include all signed integer can be widened which will be iterated and registered as intrinsic functions. */ #ifndef DEF_RVV_WI_OPS @@ -615,6 +621,12 @@ DEF_RVV_WCONVERT_F_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64) DEF_RVV_WCONVERT_F_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64) DEF_RVV_WCONVERT_F_OPS (vfloat64m8_t, RVV_REQUIRE_ELEN_FP_64) +DEF_RVV_F32_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64) +DEF_RVV_F32_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32) +DEF_RVV_F32_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32) +DEF_RVV_F32_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32) +DEF_RVV_F32_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32) + DEF_RVV_WI_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64) DEF_RVV_WI_OPS (vint8mf4_t, 0) DEF_RVV_WI_OPS (vint8mf2_t, 0) @@ -1481,3 +1493,4 @@ DEF_RVV_CRYPTO_SEW64_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64) #undef DEF_RVV_TUPLE_OPS #undef DEF_RVV_CRYPTO_SEW32_OPS #undef DEF_RVV_CRYPTO_SEW64_OPS +#undef DEF_RVV_F32_OPS diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 720436dfbc9..9b375127bbb 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -242,6 +242,12 @@ static const rvv_type_info wconvert_f_ops[] = { #include "riscv-vector-builtins-types.def" {NUM_VECTOR_TYPES, 0}}; +/* A list of all floating-point will be registered for intrinsic functions. */ +static const rvv_type_info f32_ops[] = { +#define DEF_RVV_F32_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, +#include "riscv-vector-builtins-types.def" + {NUM_VECTOR_TYPES, 0}}; + /* A list of all integer will be registered for intrinsic functions. */ static const rvv_type_info iu_ops[] = { #define DEF_RVV_I_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE}, @@ -757,6 +763,25 @@ static CONSTEXPR const rvv_arg_type_info trunc_f_v_args[] static CONSTEXPR const rvv_arg_type_info w_v_args[] = {rvv_arg_type_info (RVV_BASE_double_trunc_vector), rvv_arg_type_info_end}; +/* A list of args for vector_type func (vector_type) function. */ +static CONSTEXPR const rvv_arg_type_info bf_w_v_args[] + = {rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), + rvv_arg_type_info_end}; + +/* A list of args for vector_type func (vector_type) function. */ +static CONSTEXPR const rvv_arg_type_info bf_wwvv_args[] + = {rvv_arg_type_info (RVV_BASE_vector), + rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), + rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), + rvv_arg_type_info_end}; + +/* A list of args for vector_type func (vector_type) function. */ +static CONSTEXPR const rvv_arg_type_info bf_wwxv_args[] + = {rvv_arg_type_info (RVV_BASE_vector), + rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_scalar), + rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), + rvv_arg_type_info_end}; + /* A list of args for vector_type func (vector_type) function. */ static CONSTEXPR const rvv_arg_type_info m_args[] = {rvv_arg_type_info (RVV_BASE_mask), rvv_arg_type_info_end}; @@ -1749,6 +1774,38 @@ static CONSTEXPR const rvv_op_info f_to_nf_f_w_ops rvv_arg_type_info (RVV_BASE_double_trunc_float_vector), /* Return type */ v_args /* Args */}; +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info f32_to_bf16_f_w_ops + = {f32_ops, /* Types */ + OP_TYPE_f_w, /* Suffix */ + rvv_arg_type_info (RVV_BASE_double_trunc_bfloat_vector), /* Return type */ + v_args /* Args */}; + +/* A static operand information for vector_type func (vector_type) + * function registration. */ +static CONSTEXPR const rvv_op_info bf16_to_f32_f_v_ops + = {f32_ops, /* Types */ + OP_TYPE_f_v, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + bf_w_v_args /* Args */}; + +/* A static operand information for vector_type func (vector_type, double demote + * type, double demote type) function registration. */ +static CONSTEXPR const rvv_op_info f32_wwvv_ops + = {f32_ops, /* Types */ + OP_TYPE_vv, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + bf_wwvv_args /* Args */}; + +/* A static operand information for vector_type func (vector_type, double demote + * scalar_type, double demote type) function registration. */ +static CONSTEXPR const rvv_op_info f32_wwfv_ops + = {f32_ops, /* Types */ + OP_TYPE_vf, /* Suffix */ + rvv_arg_type_info (RVV_BASE_vector), /* Return type */ + bf_wwxv_args /* Args */}; + /* A static operand information for vector_type func (vector_type) * function registration. */ static CONSTEXPR const rvv_op_info all_v_ops @@ -4643,6 +4700,16 @@ validate_instance_type_required_extensions (const rvv_type_info type, { uint64_t exts = type.required_extensions; + if ((exts & RVV_REQUIRE_ELEN_BF_16) + && !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags)) + { + error_at (EXPR_LOCATION (exp), + "built-in function %qE requires the " + "zvfbfmin or zvfbfwma ISA extension", + exp); + return false; + } + if ((exts & RVV_REQUIRE_ELEN_FP_16) && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) { diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h index 56dbe2cf0e2..ef4148380c2 100644 --- a/gcc/config/riscv/riscv-vector-builtins.h +++ b/gcc/config/riscv/riscv-vector-builtins.h @@ -114,17 +114,19 @@ static const unsigned int CP_WRITE_CSR = 1U << 5; /* Enumerates the required extensions. */ enum required_ext { - VECTOR_EXT, /* Vector extension */ - ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ - ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ - ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ - ZVKG_EXT, /* Crypto vector Zvkg sub-ext */ - ZVKNED_EXT, /* Crypto vector Zvkned sub-ext */ + VECTOR_EXT, /* Vector extension */ + ZVBB_EXT, /* Cryto vector Zvbb sub-ext */ + ZVBB_OR_ZVKB_EXT, /* Cryto vector Zvbb or zvkb sub-ext */ + ZVBC_EXT, /* Crypto vector Zvbc sub-ext */ + ZVKG_EXT, /* Crypto vector Zvkg sub-ext */ + ZVKNED_EXT, /* Crypto vector Zvkned sub-ext */ ZVKNHA_OR_ZVKNHB_EXT, /* Crypto vector Zvknh[ab] sub-ext */ - ZVKNHB_EXT, /* Crypto vector Zvknhb sub-ext */ - ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */ - ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */ - XTHEADVECTOR_EXT, /* XTheadVector extension */ + ZVKNHB_EXT, /* Crypto vector Zvknhb sub-ext */ + ZVKSED_EXT, /* Crypto vector Zvksed sub-ext */ + ZVKSH_EXT, /* Crypto vector Zvksh sub-ext */ + XTHEADVECTOR_EXT, /* XTheadVector extension */ + ZVFBFMIN_EXT, /* Zvfbfmin externsion */ + ZVFBFWMA_EXT, /* Zvfbfwma extension */ /* Please update below to isa_name func when add or remove enum type(s). */ }; @@ -154,6 +156,10 @@ static inline const char * reqired_ext_to_isa_name (enum required_ext required) return "zvksh"; case XTHEADVECTOR_EXT: return "xthreadvector"; + case ZVFBFMIN_EXT: + return "zvfbfmin"; + case ZVFBFWMA_EXT: + return "zvfbfwma"; default: gcc_unreachable (); } @@ -187,6 +193,10 @@ static inline bool required_extensions_specified (enum required_ext required) return TARGET_ZVKSH; case XTHEADVECTOR_EXT: return TARGET_XTHEADVECTOR; + case ZVFBFMIN_EXT: + return TARGET_ZVFBFMIN; + case ZVFBFWMA_EXT: + return TARGET_ZVFBFWMA; default: gcc_unreachable (); } @@ -323,6 +333,10 @@ struct function_group_info return TARGET_ZVKSH; case XTHEADVECTOR_EXT: return TARGET_XTHEADVECTOR; + case ZVFBFMIN_EXT: + return TARGET_ZVFBFMIN; + case ZVFBFWMA_EXT: + return TARGET_ZVFBFWMA; default: gcc_unreachable (); } diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9bba5da016e..e596ff9a723 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6012,10 +6012,11 @@ riscv_validate_vector_type (const_tree type, const char *hint) bool float_type_p = riscv_vector_float_type_p (type); if (float_type_p && element_bitsize == 16 - && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags)) + && (!TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags) + && !TARGET_VECTOR_ELEN_BF_16_P (riscv_vector_elen_flags))) { error_at (input_location, - "%s %qT requires the zvfhmin or zvfh ISA extension", + "%s %qT requires the zvfhmin or zvfh or zvfbfmin ISA extension", hint, type); return; } From patchwork Thu Jun 27 07:01:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feng Wang X-Patchwork-Id: 1953000 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=server2.sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=patchwork.ozlabs.org) Received: from server2.sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4W8qJS2T0vz20Xm for ; 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a=rsa-sha256; d=sourceware.org; s=key; t=1719471721; c=relaxed/simple; bh=QEgODsgX0VkuhMR35GErbpPiIXnYoiLd+X2qtzyU6rk=; h=From:To:Subject:Date:Message-Id; b=uILpl89ZmWr8J8oNvkz/OP9zBIBbsBhbvdf6TJHU4YWVcp5FPE2/dZryudXlrNjVDaTeGNGZ8fC/yLnR90MexrU32yXIu+BUPFJXO/DbltSvtpvDhT7QAdG5joG+JA4gRxCH1SgYMTnvoOldj/UWBOpH3Hccvykad1iVACpVNiU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [10.12.130.31]) by app2 (Coremail) with SMTP id TQJkCgC3ybtPDn1mHA0SAA--.62896S6; Thu, 27 Jun 2024 15:01:49 +0800 (CST) From: Feng Wang To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, juzhe.zhong@rivai.ai, jinma.contrib@gmail.com, Feng Wang Subject: [PATCH 3/3 v2] RISC-V: Add md files for vector BFloat16 Date: Thu, 27 Jun 2024 07:01:21 +0000 Message-Id: <20240627070121.32461-3-wangfeng@eswincomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240627070121.32461-1-wangfeng@eswincomputing.com> References: <20240627070121.32461-1-wangfeng@eswincomputing.com> X-CM-TRANSID: TQJkCgC3ybtPDn1mHA0SAA--.62896S6 X-Coremail-Antispam: 1UD129KBjvAXoWDXw1rAF4UAF17uF43trWxtFb_yoWrCw1xCo WxWr4xCr1DAF1Fvasa9r4rJ34vyFZ5tr1kXr18tr1vyF98tr4vkw1agay3Z3W5X34fur18 AF1fCa4kJFWxJr95n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYA7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAIw28Icx kI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUb1v3UUUUUU== X-CM-SenderInfo: pzdqwwxhqjqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org v2:Rebase. Accroding to the BFloat16 spec, some vector iterators and new pattern are added in md files. gcc/ChangeLog: * config/riscv/riscv.md: Add new insn name for vector BFloat16. * config/riscv/vector-iterators.md: Add some iterators for vector BFloat16. * config/riscv/vector.md: Add some attribute for vector BFloat16. * config/riscv/vector-bfloat16.md: New file. Add insn pattern vector BFloat16. --- gcc/config/riscv/riscv.md | 13 ++- gcc/config/riscv/vector-bfloat16.md | 135 +++++++++++++++++++++ gcc/config/riscv/vector-iterators.md | 169 ++++++++++++++++++++++++++- gcc/config/riscv/vector.md | 103 ++++++++++++++-- 4 files changed, 405 insertions(+), 15 deletions(-) create mode 100644 gcc/config/riscv/vector-bfloat16.md diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ff37125e3f2..4d1ceb094e3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -200,6 +200,7 @@ RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI, RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI, RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI, + RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF, RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF, RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI, RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF, @@ -219,6 +220,11 @@ RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI, RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI, RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI, + RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,RVVM1x7BF,RVVMF2x7BF, + RVVMF4x7BF,RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,RVVM1x5BF, + RVVMF2x5BF,RVVMF4x5BF,RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF, + RVVMF4x4BF,RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF, + RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF, RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,RVVM1x7HF,RVVMF2x7HF, RVVMF4x7HF,RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,RVVM1x5HF, RVVMF2x5HF,RVVMF4x5HF,RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF, @@ -462,6 +468,10 @@ ;; vsm4r crypto vector SM4 Rounds instructions ;; vsm3me crypto vector SM3 Message Expansion instructions ;; vsm3c crypto vector SM3 Compression instructions +;; 18.Vector BF16 instrctions +;; vfncvtbf16 vector narrowing single floating-point to brain floating-point instruction +;; vfwcvtbf16 vector widening brain floating-point to single floating-point instruction +;; vfwmaccbf16 vector BF16 widening multiply-accumulate (define_attr "type" "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, @@ -483,7 +493,7 @@ vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down, vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll, vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz, - vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c" + vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -4321,6 +4331,7 @@ (include "generic-ooo.md") (include "vector.md") (include "vector-crypto.md") +(include "vector-bfloat16.md") (include "zicond.md") (include "sfb.md") (include "zc.md") diff --git a/gcc/config/riscv/vector-bfloat16.md b/gcc/config/riscv/vector-bfloat16.md new file mode 100644 index 00000000000..562aa8ee5ed --- /dev/null +++ b/gcc/config/riscv/vector-bfloat16.md @@ -0,0 +1,135 @@ +;; Machine description for RISC-V bfloat16 extensions. +;; Copyright (C) 2024 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_mode_iterator VWEXTF_ZVFBF [ + (RVVM8SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") + (RVVM4SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") + (RVVM2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") + (RVVM1SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32") + (RVVMF2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") +]) + +(define_mode_attr V_FP32TOBF16_TRUNC [ + (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF") (RVVM1SF "RVVMF2BF") (RVVMF2SF "RVVMF4BF") +]) + +(define_mode_attr VF32_SUBEL [ + (RVVM8SF "BF") (RVVM4SF "BF") (RVVM2SF "BF") (RVVM1SF "BF") (RVVMF2SF "BF")]) + +;; Zvfbfmin extension + +(define_insn "@pred_trunc_to_bf16" + [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr") + (if_then_else: + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK") + (match_operand 5 "const_int_operand" " i, i, i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (float_truncate: + (match_operand:VWEXTF_ZVFBF 3 "register_operand" " 0, 0, 0, 0, vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))] + "TARGET_ZVFBFMIN" + "vfncvtbf16.f.f.w\t%0,%3%p1" + [(set_attr "type" "vfncvtbf16") + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))]) + +(define_insn "@pred_extend_bf16_to_" + [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand" "=&vr, &vr") + (if_then_else:VWEXTF_ZVFBF + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 4 "vector_length_operand" " rK, rK") + (match_operand 5 "const_int_operand" " i, i") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (float_extend:VWEXTF_ZVFBF + (match_operand: 3 "register_operand" " vr, vr")) + (match_operand:VWEXTF_ZVFBF 2 "vector_merge_operand" " vu, 0")))] + "TARGET_ZVFBFMIN" + "vfwcvtbf16.f.f.v\t%0,%3%p1" + [(set_attr "type" "vfwcvtbf16") + (set_attr "mode" "")]) + + +(define_insn "@pred_widen_bf16_mul_" + [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand" "=&vr") + (if_then_else:VWEXTF_ZVFBF + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 5 "vector_length_operand" " rK") + (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") + (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (plus:VWEXTF_ZVFBF + (mult:VWEXTF_ZVFBF + (float_extend:VWEXTF_ZVFBF + (match_operand: 3 "register_operand" " vr")) + (float_extend:VWEXTF_ZVFBF + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTF_ZVFBF 2 "register_operand" " 0")) + (match_dup 2)))] + "TARGET_ZVFBFWMA" + "vfwmaccbf16.vv\t%0,%3,%4%p1" + [(set_attr "type" "vfwmaccbf16") + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) + +(define_insn "@pred_widen_bf16_mul__scalar" + [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand" "=&vr") + (if_then_else:VWEXTF_ZVFBF + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1") + (match_operand 5 "vector_length_operand" " rK") + (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") + (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM) + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (plus:VWEXTF_ZVFBF + (mult:VWEXTF_ZVFBF + (float_extend:VWEXTF_ZVFBF + (vec_duplicate: + (match_operand: 3 "register_operand" " f"))) + (float_extend:VWEXTF_ZVFBF + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTF_ZVFBF 2 "register_operand" " 0")) + (match_dup 2)))] + "TARGET_ZVFBFWMA" + "vfwmaccbf16.vf\t%0,%3,%4%p1" + [(set_attr "type" "vfwmaccbf16") + (set_attr "mode" "") + (set (attr "frm_mode") + (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 43137a2a379..f8c0cc06217 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -146,6 +146,15 @@ (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") ]) +(define_mode_iterator VF_ZVFBF16 [ + (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") +]) + (define_mode_iterator VF_ZVFHMIN [ (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") @@ -281,6 +290,10 @@ (define_mode_iterator VEEWEXT2 [ RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -323,6 +336,10 @@ RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") + (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") @@ -346,6 +363,11 @@ (RVVMF2HI "TARGET_64BIT") (RVVMF4HI "TARGET_MIN_VLEN > 32 && TARGET_64BIT") + (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2BF "TARGET_VECTOR_ELEN_FP_16") + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32 && TARGET_64BIT") + (RVVM2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT") @@ -768,6 +790,7 @@ (RVVMF4HI "TARGET_MIN_VLEN > 32") (RVVMF2SI "TARGET_MIN_VLEN > 32") (RVVM1DI "TARGET_VECTOR_ELEN_64") + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64") @@ -778,6 +801,7 @@ RVVMF2HI RVVM1SI (RVVM2DI "TARGET_VECTOR_ELEN_64") + (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") @@ -788,6 +812,7 @@ RVVM1HI RVVM2SI (RVVM4DI "TARGET_VECTOR_ELEN_64") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64") @@ -798,6 +823,7 @@ RVVM2HI RVVM4SI (RVVM8DI "TARGET_VECTOR_ELEN_64") + (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") @@ -807,6 +833,7 @@ RVVM2QI RVVM4HI RVVM8SI + (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") ]) @@ -814,6 +841,7 @@ (define_mode_iterator RATIO2 [ RVVM4QI RVVM8HI + (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") ]) @@ -865,6 +893,9 @@ RVVM8HI RVVM4HI RVVM2HI RVVM1HI + (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") @@ -885,6 +916,8 @@ RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") + (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") + (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32") (RVVMF2SI "TARGET_MIN_VLEN > 32") @@ -1142,6 +1175,13 @@ (RVVM1x6DI "TARGET_VECTOR_ELEN_64") (RVVM1x7DI "TARGET_VECTOR_ELEN_64") (RVVM1x8DI "TARGET_VECTOR_ELEN_64") + (RVVMF4x2BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x3BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x4BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x5BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x6BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x7BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") + (RVVMF4x8BF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_BF_16") (RVVMF4x2HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") (RVVMF4x3HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") (RVVMF4x4HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16") @@ -1190,6 +1230,13 @@ (RVVM2x2DI "TARGET_VECTOR_ELEN_64") (RVVM2x3DI "TARGET_VECTOR_ELEN_64") (RVVM2x4DI "TARGET_VECTOR_ELEN_64") + (RVVMF2x2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x3BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x5BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x6BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x7BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2x8BF "TARGET_VECTOR_ELEN_BF_16") (RVVMF2x2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2x3HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2x4HF "TARGET_VECTOR_ELEN_FP_16") @@ -1228,6 +1275,13 @@ RVVM2x3SI RVVM2x4SI (RVVM4x2DI "TARGET_VECTOR_ELEN_64") + (RVVM1x2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x3BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x5BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x6BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x7BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1x8BF "TARGET_VECTOR_ELEN_BF_16") (RVVM1x2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1x3HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1x4HF "TARGET_VECTOR_ELEN_FP_16") @@ -1253,6 +1307,9 @@ RVVM2x3HI RVVM2x4HI RVVM4x2SI + (RVVM2x2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2x3BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2x4BF "TARGET_VECTOR_ELEN_BF_16") (RVVM2x2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2x3HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2x4HF "TARGET_VECTOR_ELEN_FP_16") @@ -1264,6 +1321,7 @@ RVVM2x3QI RVVM2x4QI RVVM4x2HI + (RVVM4x2BF "TARGET_VECTOR_ELEN_BF_16") (RVVM4x2HF "TARGET_VECTOR_ELEN_FP_16") ]) @@ -1475,6 +1533,13 @@ (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT") + (RVVM8BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM4BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVM1BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16") + (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32") + (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32") @@ -1576,7 +1641,7 @@ (define_mode_iterator VLS_ZVFH [VLSI VLSF]) -(define_mode_iterator V [VI VF_ZVFHMIN]) +(define_mode_iterator V [VI VF_ZVFBF16 VF_ZVFHMIN]) (define_mode_iterator V_ZVFH [VI VF]) @@ -1588,7 +1653,7 @@ (define_mode_iterator V_VLSF [VF VLSF]) -(define_mode_iterator V_VLSF_ZVFHMIN [VF_ZVFHMIN VLSF_ZVFHMIN]) +(define_mode_iterator V_VLSF_ZVFHMIN [VF_ZVFBF16 VF_ZVFHMIN VLSF_ZVFHMIN]) (define_mode_iterator VT [V1T V2T V4T V8T V16T V32T]) @@ -1630,6 +1695,8 @@ (RVVM8HI "RVVM8HI") (RVVM4HI "RVVM4HI") (RVVM2HI "RVVM2HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVMF2HI") (RVVMF4HI "RVVMF4HI") + (RVVM8BF "RVVM8HI") (RVVM4BF "RVVM4HI") (RVVM2BF "RVVM2HI") (RVVM1BF "RVVM1HI") (RVVMF2BF "RVVMF2HI") (RVVMF4BF "RVVMF4HI") + (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI") (RVVM8SI "RVVM8SI") (RVVM4SI "RVVM4SI") (RVVM2SI "RVVM2SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVMF2SI") @@ -1821,6 +1888,8 @@ (RVVM8HI "RVVMF2BI") (RVVM4HI "RVVMF4BI") (RVVM2HI "RVVMF8BI") (RVVM1HI "RVVMF16BI") (RVVMF2HI "RVVMF32BI") (RVVMF4HI "RVVMF64BI") + (RVVM8BF "RVVMF2BI") (RVVM4BF "RVVMF4BI") (RVVM2BF "RVVMF8BI") (RVVM1BF "RVVMF16BI") (RVVMF2BF "RVVMF32BI") (RVVMF4BF "RVVMF64BI") + (RVVM8HF "RVVMF2BI") (RVVM4HF "RVVMF4BI") (RVVM2HF "RVVMF8BI") (RVVM1HF "RVVMF16BI") (RVVMF2HF "RVVMF32BI") (RVVMF4HF "RVVMF64BI") (RVVM8SI "RVVMF4BI") (RVVM4SI "RVVMF8BI") (RVVM2SI "RVVMF16BI") (RVVM1SI "RVVMF32BI") (RVVMF2SI "RVVMF64BI") @@ -1847,6 +1916,14 @@ (RVVM2x3HI "RVVMF8BI") (RVVM1x3HI "RVVMF16BI") (RVVMF2x3HI "RVVMF32BI") (RVVMF4x3HI "RVVMF64BI") (RVVM4x2HI "RVVMF4BI") (RVVM2x2HI "RVVMF8BI") (RVVM1x2HI "RVVMF16BI") (RVVMF2x2HI "RVVMF32BI") (RVVMF4x2HI "RVVMF64BI") + (RVVM1x8BF "RVVMF16BI") (RVVMF2x8BF "RVVMF32BI") (RVVMF4x8BF "RVVMF64BI") + (RVVM1x7BF "RVVMF16BI") (RVVMF2x7BF "RVVMF32BI") (RVVMF4x7BF "RVVMF64BI") + (RVVM1x6BF "RVVMF16BI") (RVVMF2x6BF "RVVMF32BI") (RVVMF4x6BF "RVVMF64BI") + (RVVM1x5BF "RVVMF16BI") (RVVMF2x5BF "RVVMF32BI") (RVVMF4x5BF "RVVMF64BI") + (RVVM2x4BF "RVVMF8BI") (RVVM1x4BF "RVVMF16BI") (RVVMF2x4BF "RVVMF32BI") (RVVMF4x4BF "RVVMF64BI") + (RVVM2x3BF "RVVMF8BI") (RVVM1x3BF "RVVMF16BI") (RVVMF2x3BF "RVVMF32BI") (RVVMF4x3BF "RVVMF64BI") + (RVVM4x2BF "RVVMF4BI") (RVVM2x2BF "RVVMF8BI") (RVVM1x2BF "RVVMF16BI") (RVVMF2x2BF "RVVMF32BI") (RVVMF4x2BF "RVVMF64BI") + (RVVM1x8HF "RVVMF16BI") (RVVMF2x8HF "RVVMF32BI") (RVVMF4x8HF "RVVMF64BI") (RVVM1x7HF "RVVMF16BI") (RVVMF2x7HF "RVVMF32BI") (RVVMF4x7HF "RVVMF64BI") (RVVM1x6HF "RVVMF16BI") (RVVMF2x6HF "RVVMF32BI") (RVVMF4x6HF "RVVMF64BI") @@ -1922,6 +1999,8 @@ (RVVM8HI "rvvmf2bi") (RVVM4HI "rvvmf4bi") (RVVM2HI "rvvmf8bi") (RVVM1HI "rvvmf16bi") (RVVMF2HI "rvvmf32bi") (RVVMF4HI "rvvmf64bi") + (RVVM8BF "rvvmf2bi") (RVVM4BF "rvvmf4bi") (RVVM2BF "rvvmf8bi") (RVVM1BF "rvvmf16bi") (RVVMF2BF "rvvmf32bi") (RVVMF4BF "rvvmf64bi") + (RVVM8HF "rvvmf2bi") (RVVM4HF "rvvmf4bi") (RVVM2HF "rvvmf8bi") (RVVM1HF "rvvmf16bi") (RVVMF2HF "rvvmf32bi") (RVVMF4HF "rvvmf64bi") (RVVM8SI "rvvmf4bi") (RVVM4SI "rvvmf8bi") (RVVM2SI "rvvmf16bi") (RVVM1SI "rvvmf32bi") (RVVMF2SI "rvvmf64bi") @@ -1948,6 +2027,14 @@ (RVVM2x3HI "rvvmf8bi") (RVVM1x3HI "rvvmf16bi") (RVVMF2x3HI "rvvmf32bi") (RVVMF4x3HI "rvvmf64bi") (RVVM4x2HI "rvvmf4bi") (RVVM2x2HI "rvvmf8bi") (RVVM1x2HI "rvvmf16bi") (RVVMF2x2HI "rvvmf32bi") (RVVMF4x2HI "rvvmf64bi") + (RVVM1x8BF "rvvmf16bi") (RVVMF2x8BF "rvvmf32bi") (RVVMF4x8BF "rvvmf64bi") + (RVVM1x7BF "rvvmf16bi") (RVVMF2x7BF "rvvmf32bi") (RVVMF4x7BF "rvvmf64bi") + (RVVM1x6BF "rvvmf16bi") (RVVMF2x6BF "rvvmf32bi") (RVVMF4x6BF "rvvmf64bi") + (RVVM1x5BF "rvvmf16bi") (RVVMF2x5BF "rvvmf32bi") (RVVMF4x5BF "rvvmf64bi") + (RVVM2x4BF "rvvmf8bi") (RVVM1x4BF "rvvmf16bi") (RVVMF2x4BF "rvvmf32bi") (RVVMF4x4BF "rvvmf64bi") + (RVVM2x3BF "rvvmf8bi") (RVVM1x3BF "rvvmf16bi") (RVVMF2x3BF "rvvmf32bi") (RVVMF4x3BF "rvvmf64bi") + (RVVM4x2BF "rvvmf4bi") (RVVM2x2BF "rvvmf8bi") (RVVM1x2BF "rvvmf16bi") (RVVMF2x2BF "rvvmf32bi") (RVVMF4x2BF "rvvmf64bi") + (RVVM1x8HF "rvvmf16bi") (RVVMF2x8HF "rvvmf32bi") (RVVMF4x8HF "rvvmf64bi") (RVVM1x7HF "rvvmf16bi") (RVVMF2x7HF "rvvmf32bi") (RVVMF4x7HF "rvvmf64bi") (RVVM1x6HF "rvvmf16bi") (RVVMF2x6HF "rvvmf32bi") (RVVMF4x6HF "rvvmf64bi") @@ -2023,6 +2110,8 @@ (RVVM8HI "HI") (RVVM4HI "HI") (RVVM2HI "HI") (RVVM1HI "HI") (RVVMF2HI "HI") (RVVMF4HI "HI") + (RVVM8BF "BF") (RVVM4BF "BF") (RVVM2BF "BF") (RVVM1BF "BF") (RVVMF2BF "BF") (RVVMF4BF "BF") + (RVVM8HF "HF") (RVVM4HF "HF") (RVVM2HF "HF") (RVVM1HF "HF") (RVVMF2HF "HF") (RVVMF4HF "HF") (RVVM8SI "SI") (RVVM4SI "SI") (RVVM2SI "SI") (RVVM1SI "SI") (RVVMF2SI "SI") @@ -2120,6 +2209,8 @@ (RVVM8HI "hi") (RVVM4HI "hi") (RVVM2HI "hi") (RVVM1HI "hi") (RVVMF2HI "hi") (RVVMF4HI "hi") + (RVVM8BF "bf") (RVVM4BF "bf") (RVVM2BF "bf") (RVVM1BF "bf") (RVVMF2BF "bf") (RVVMF4BF "bf") + (RVVM8HF "hf") (RVVM4HF "hf") (RVVM2HF "hf") (RVVM1HF "hf") (RVVMF2HF "hf") (RVVMF4HF "hf") (RVVM8SI "si") (RVVM4SI "si") (RVVM2SI "si") (RVVM1SI "si") (RVVMF2SI "si") @@ -2162,6 +2253,32 @@ (RVVM2x3HI "rvvm2hi") (RVVM1x3HI "rvvm1hi") (RVVMF2x3HI "rvvmf2hi") (RVVMF4x3HI "rvvmf4hi") (RVVM4x2HI "rvvm4hi") (RVVM2x2HI "rvvm2hi") (RVVM1x2HI "rvvm1hi") (RVVMF2x2HI "rvvmf2hi") (RVVMF4x2HI "rvvmf4hi") + (RVVM1x8BF "rvvm1bf") + (RVVMF2x8BF "rvvmf2bf") + (RVVMF4x8BF "rvvmf4bf") + (RVVM1x7BF "rvvm1bf") + (RVVMF2x7BF "rvvmf2bf") + (RVVMF4x7BF "rvvmf4bf") + (RVVM1x6BF "rvvm1bf") + (RVVMF2x6BF "rvvmf2bf") + (RVVMF4x6BF "rvvmf4bf") + (RVVM1x5BF "rvvm1bf") + (RVVMF2x5BF "rvvmf2bf") + (RVVMF4x5BF "rvvmf4bf") + (RVVM2x4BF "rvvm2bf") + (RVVM1x4BF "rvvm1bf") + (RVVMF2x4BF "rvvmf2bf") + (RVVMF4x4BF "rvvmf4bf") + (RVVM2x3BF "rvvm2bf") + (RVVM1x3BF "rvvm1bf") + (RVVMF2x3BF "rvvmf2bf") + (RVVMF4x3BF "rvvmf4bf") + (RVVM4x2BF "rvvm4bf") + (RVVM2x2BF "rvvm2bf") + (RVVM1x2BF "rvvm1bf") + (RVVMF2x2BF "rvvmf2bf") + (RVVMF4x2BF "rvvmf4bf") + (RVVM1x8HF "rvvm1hf") (RVVMF2x8HF "rvvmf2hf") (RVVMF4x8HF "rvvmf4hf") @@ -2298,6 +2415,14 @@ (RVVM2x3HI "3") (RVVM1x3HI "3") (RVVMF2x3HI "3") (RVVMF4x3HI "3") (RVVM4x2HI "2") (RVVM2x2HI "2") (RVVM1x2HI "2") (RVVMF2x2HI "2") (RVVMF4x2HI "2") + (RVVM1x8BF "8") (RVVMF2x8BF "8") (RVVMF4x8BF "8") + (RVVM1x7BF "7") (RVVMF2x7BF "7") (RVVMF4x7BF "7") + (RVVM1x6BF "6") (RVVMF2x6BF "6") (RVVMF4x6BF "6") + (RVVM1x5BF "5") (RVVMF2x5BF "5") (RVVMF4x5BF "5") + (RVVM2x4BF "4") (RVVM1x4BF "4") (RVVMF2x4BF "4") (RVVMF4x4BF "4") + (RVVM2x3BF "3") (RVVM1x3BF "3") (RVVMF2x3BF "3") (RVVMF4x3BF "3") + (RVVM4x2BF "2") (RVVM2x2BF "2") (RVVM1x2BF "2") (RVVMF2x2BF "2") (RVVMF4x2BF "2") + (RVVM1x8HF "8") (RVVMF2x8HF "8") (RVVMF4x8HF "8") (RVVM1x7HF "7") (RVVMF2x7HF "7") (RVVMF4x7HF "7") (RVVM1x6HF "6") (RVVMF2x6HF "6") (RVVMF4x6HF "6") @@ -2352,6 +2477,8 @@ (RVVM8HI "16") (RVVM4HI "16") (RVVM2HI "16") (RVVM1HI "16") (RVVMF2HI "16") (RVVMF4HI "16") + (RVVM8BF "16") (RVVM4BF "16") (RVVM2BF "16") (RVVM1BF "16") (RVVMF2BF "16") (RVVMF4BF "16") + (RVVM8HF "16") (RVVM4HF "16") (RVVM2HF "16") (RVVM1HF "16") (RVVMF2HF "16") (RVVMF4HF "16") (RVVM8SI "32") (RVVM4SI "32") (RVVM2SI "32") (RVVM1SI "32") (RVVMF2SI "32") @@ -2378,6 +2505,14 @@ (RVVM2x3HI "16") (RVVM1x3HI "16") (RVVMF2x3HI "16") (RVVMF4x3HI "16") (RVVM4x2HI "16") (RVVM2x2HI "16") (RVVM1x2HI "16") (RVVMF2x2HI "16") (RVVMF4x2HI "16") + (RVVM1x8BF "16") (RVVMF2x8BF "16") (RVVMF4x8BF "16") + (RVVM1x7BF "16") (RVVMF2x7BF "16") (RVVMF4x7BF "16") + (RVVM1x6BF "16") (RVVMF2x6BF "16") (RVVMF4x6BF "16") + (RVVM1x5BF "16") (RVVMF2x5BF "16") (RVVMF4x5BF "16") + (RVVM2x4BF "16") (RVVM1x4BF "16") (RVVMF2x4BF "16") (RVVMF4x4BF "16") + (RVVM2x3BF "16") (RVVM1x3BF "16") (RVVMF2x3BF "16") (RVVMF4x3BF "16") + (RVVM4x2BF "16") (RVVM2x2BF "16") (RVVM1x2BF "16") (RVVMF2x2BF "16") (RVVMF4x2BF "16") + (RVVM1x8HF "16") (RVVMF2x8HF "16") (RVVMF4x8HF "16") (RVVM1x7HF "16") (RVVMF2x7HF "16") (RVVMF4x7HF "16") (RVVM1x6HF "16") (RVVMF2x6HF "16") (RVVMF4x6HF "16") @@ -2444,6 +2579,8 @@ (define_mode_attr double_trunc_sew [ (RVVM8HI "8") (RVVM4HI "8") (RVVM2HI "8") (RVVM1HI "8") (RVVMF2HI "8") (RVVMF4HI "8") + (RVVM8BF "8") (RVVM4BF "8") (RVVM2BF "8") (RVVM1BF "8") (RVVMF2BF "8") (RVVMF4BF "8") + (RVVM8HF "8") (RVVM4HF "8") (RVVM2HF "8") (RVVM1HF "8") (RVVMF2HF "8") (RVVMF4HF "8") (RVVM8SI "16") (RVVM4SI "16") (RVVM2SI "16") (RVVM1SI "16") (RVVMF2SI "16") @@ -2476,6 +2613,8 @@ (RVVM4HI "32") (RVVM2HI "32") (RVVM1HI "32") (RVVMF2HI "32") (RVVMF4HI "32") + (RVVM4BF "32") (RVVM2BF "32") (RVVM1BF "32") (RVVMF2BF "32") (RVVMF4BF "32") + (RVVM4HF "32") (RVVM2HF "32") (RVVM1HF "32") (RVVMF2HF "32") (RVVMF4HF "32") (RVVM4SI "64") (RVVM2SI "64") (RVVM1SI "64") (RVVMF2SI "64") @@ -2810,6 +2949,8 @@ (define_mode_attr VINDEX_DOUBLE_TRUNC [ (RVVM8HI "RVVM4QI") (RVVM4HI "RVVM2QI") (RVVM2HI "RVVM1QI") (RVVM1HI "RVVMF2QI") (RVVMF2HI "RVVMF4QI") (RVVMF4HI "RVVMF8QI") + (RVVM8BF "RVVM4QI") (RVVM4BF "RVVM2QI") (RVVM2BF "RVVM1QI") (RVVM1BF "RVVMF2QI") (RVVMF2BF "RVVMF4QI") (RVVMF4BF "RVVMF8QI") + (RVVM8HF "RVVM4QI") (RVVM4HF "RVVM2QI") (RVVM2HF "RVVM1QI") (RVVM1HF "RVVMF2QI") (RVVMF2HF "RVVMF4QI") (RVVMF4HF "RVVMF8QI") (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI") @@ -2842,6 +2983,8 @@ (RVVM4HI "RVVM8SI") (RVVM2HI "RVVM4SI") (RVVM1HI "RVVM2SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVMF2SI") + (RVVM4BF "RVVM8SI") (RVVM2BF "RVVM4SI") (RVVM1BF "RVVM2SI") (RVVMF2BF "RVVM1SI") (RVVMF4BF "RVVMF2SI") + (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI") (RVVM4SI "RVVM8DI") (RVVM2SI "RVVM4DI") (RVVM1SI "RVVM2DI") (RVVMF2SI "RVVM1DI") @@ -2854,6 +2997,8 @@ (RVVM2HI "RVVM8DI") (RVVM1HI "RVVM4DI") (RVVMF2HI "RVVM2DI") (RVVMF4HI "RVVM1DI") + (RVVM2BF "RVVM8DI") (RVVM1BF "RVVM4DI") (RVVMF2BF "RVVM2DI") (RVVMF4BF "RVVM1DI") + (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI") (RVVMF4HF "RVVM1DI") ]) @@ -3358,6 +3503,10 @@ (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand") (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_eew16_stride_operand") + (RVVM8BF "vector_eew16_stride_operand") (RVVM4BF "vector_eew16_stride_operand") + (RVVM2BF "vector_eew16_stride_operand") (RVVM1BF "vector_eew16_stride_operand") + (RVVMF2BF "vector_eew16_stride_operand") (RVVMF4BF "vector_eew16_stride_operand") + (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF "vector_eew16_stride_operand") (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF "vector_eew16_stride_operand") (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF "vector_eew16_stride_operand") @@ -3387,6 +3536,10 @@ (RVVM2HI "rJ,rJ,rJ,c02,c02,c02") (RVVM1HI "rJ,rJ,rJ,c02,c02,c02") (RVVMF2HI "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HI "rJ,rJ,rJ,c02,c02,c02") + (RVVM8BF "rJ,rJ,rJ,c02,c02,c02") (RVVM4BF "rJ,rJ,rJ,c02,c02,c02") + (RVVM2BF "rJ,rJ,rJ,c02,c02,c02") (RVVM1BF "rJ,rJ,rJ,c02,c02,c02") + (RVVMF2BF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4BF "rJ,rJ,rJ,c02,c02,c02") + (RVVM8HF "rJ,rJ,rJ,c02,c02,c02") (RVVM4HF "rJ,rJ,rJ,c02,c02,c02") (RVVM2HF "rJ,rJ,rJ,c02,c02,c02") (RVVM1HF "rJ,rJ,rJ,c02,c02,c02") (RVVMF2HF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HF "rJ,rJ,rJ,c02,c02,c02") @@ -3416,6 +3569,10 @@ (RVVM2HI "rJ,c02") (RVVM1HI "rJ,c02") (RVVMF2HI "rJ,c02") (RVVMF4HI "rJ,c02") + (RVVM8BF "rJ,c02") (RVVM4BF "rJ,c02") + (RVVM2BF "rJ,c02") (RVVM1BF "rJ,c02") + (RVVMF2BF "rJ,c02") (RVVMF4BF "rJ,c02") + (RVVM8HF "rJ,c02") (RVVM4HF "rJ,c02") (RVVM2HF "rJ,c02") (RVVM1HF "rJ,c02") (RVVMF2HF "rJ,c02") (RVVMF4HF "rJ,c02") @@ -3444,6 +3601,10 @@ (RVVM2HI "immediate_operand") (RVVM1HI "immediate_operand") (RVVMF2HI "immediate_operand") (RVVMF4HI "immediate_operand") + (RVVM8BF "const_1_operand") (RVVM4BF "vector_gs_extension_operand") + (RVVM2BF "immediate_operand") (RVVM1BF "immediate_operand") + (RVVMF2BF "immediate_operand") (RVVMF4BF "immediate_operand") + (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_extension_operand") (RVVM2HF "immediate_operand") (RVVM1HF "immediate_operand") (RVVMF2HF "immediate_operand") (RVVMF4HF "immediate_operand") @@ -3470,6 +3631,10 @@ (RVVM2HI "const_1_or_2_operand") (RVVM1HI "const_1_or_2_operand") (RVVMF2HI "const_1_or_2_operand") (RVVMF4HI "const_1_or_2_operand") + (RVVM8BF "const_1_operand") (RVVM4BF "vector_gs_scale_operand_16_rv32") + (RVVM2BF "const_1_or_2_operand") (RVVM1BF "const_1_or_2_operand") + (RVVMF2BF "const_1_or_2_operand") (RVVMF4BF "const_1_or_2_operand") + (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_scale_operand_16_rv32") (RVVM2HF "const_1_or_2_operand") (RVVM1HF "const_1_or_2_operand") (RVVMF2HF "const_1_or_2_operand") (RVVMF4HF "const_1_or_2_operand") diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index fe18ee5b5f7..149e4ae319d 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -54,7 +54,8 @@ vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\ vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ - vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\ + vfncvtbf16,vfwcvtbf16,vfwmaccbf16") (const_string "true")] (const_string "false"))) @@ -78,7 +79,8 @@ vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\ vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\ vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ - vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c") + vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\ + vfncvtbf16,vfwcvtbf16,vfwmaccbf16") (const_string "true")] (const_string "false"))) @@ -119,6 +121,14 @@ RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\ RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\ RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\ + RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF,\ + RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,\ + RVVM1x7BF,RVVMF2x7BF,RVVMF4x7BF,\ + RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,\ + RVVM1x5BF,RVVMF2x5BF,RVVMF4x5BF,\ + RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF,RVVMF4x4BF,\ + RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF,\ + RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF,\ RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\ RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\ RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\ @@ -180,6 +190,12 @@ (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1") (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2") (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM8BF") (symbol_ref "riscv_vector::LMUL_8") + (eq_attr "mode" "RVVM4BF") (symbol_ref "riscv_vector::LMUL_4") + (eq_attr "mode" "RVVM2BF") (symbol_ref "riscv_vector::LMUL_2") + (eq_attr "mode" "RVVM1BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4BF") (symbol_ref "riscv_vector::LMUL_F4") (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8") (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4") (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2") @@ -261,6 +277,31 @@ (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1") (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2") (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM1x8BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x8BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x8BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM1x7BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x7BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x7BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM1x6BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x6BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x6BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM1x5BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x5BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x5BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM2x4BF") (symbol_ref "riscv_vector::LMUL_2") + (eq_attr "mode" "RVVM1x4BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x4BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x4BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM2x3BF") (symbol_ref "riscv_vector::LMUL_2") + (eq_attr "mode" "RVVM1x3BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x3BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x3BF") (symbol_ref "riscv_vector::LMUL_F4") + (eq_attr "mode" "RVVM4x2BF") (symbol_ref "riscv_vector::LMUL_4") + (eq_attr "mode" "RVVM2x2BF") (symbol_ref "riscv_vector::LMUL_2") + (eq_attr "mode" "RVVM1x2BF") (symbol_ref "riscv_vector::LMUL_1") + (eq_attr "mode" "RVVMF2x2BF") (symbol_ref "riscv_vector::LMUL_F2") + (eq_attr "mode" "RVVMF4x2BF") (symbol_ref "riscv_vector::LMUL_F4") (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1") (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2") (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4") @@ -446,7 +487,7 @@ vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,vror,vwsll,\ vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\ - vsm3me,vsm3c") + vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16") (const_int INVALID_ATTRIBUTE) (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\ vlsegdff,vssegtux,vlsegdox,vlsegdux") @@ -465,6 +506,12 @@ (eq_attr "mode" "RVVM1HI") (const_int 16) (eq_attr "mode" "RVVMF2HI") (const_int 32) (eq_attr "mode" "RVVMF4HI") (const_int 64) + (eq_attr "mode" "RVVM8BF") (const_int 2) + (eq_attr "mode" "RVVM4BF") (const_int 4) + (eq_attr "mode" "RVVM2BF") (const_int 8) + (eq_attr "mode" "RVVM1BF") (const_int 16) + (eq_attr "mode" "RVVMF2BF") (const_int 32) + (eq_attr "mode" "RVVMF4BF") (const_int 64) (eq_attr "mode" "RVVM8HF") (const_int 2) (eq_attr "mode" "RVVM4HF") (const_int 4) (eq_attr "mode" "RVVM2HF") (const_int 8) @@ -546,6 +593,31 @@ (eq_attr "mode" "RVVM1x2HI") (const_int 16) (eq_attr "mode" "RVVMF2x2HI") (const_int 32) (eq_attr "mode" "RVVMF4x2HI") (const_int 64) + (eq_attr "mode" "RVVM1x8BF") (const_int 16) + (eq_attr "mode" "RVVMF2x8BF") (const_int 32) + (eq_attr "mode" "RVVMF4x8BF") (const_int 64) + (eq_attr "mode" "RVVM1x7BF") (const_int 16) + (eq_attr "mode" "RVVMF2x7BF") (const_int 32) + (eq_attr "mode" "RVVMF4x7BF") (const_int 64) + (eq_attr "mode" "RVVM1x6BF") (const_int 16) + (eq_attr "mode" "RVVMF2x6BF") (const_int 32) + (eq_attr "mode" "RVVMF4x6BF") (const_int 64) + (eq_attr "mode" "RVVM1x5BF") (const_int 16) + (eq_attr "mode" "RVVMF2x5BF") (const_int 32) + (eq_attr "mode" "RVVMF4x5BF") (const_int 64) + (eq_attr "mode" "RVVM2x4BF") (const_int 8) + (eq_attr "mode" "RVVM1x4BF") (const_int 16) + (eq_attr "mode" "RVVMF2x4BF") (const_int 32) + (eq_attr "mode" "RVVMF4x4BF") (const_int 64) + (eq_attr "mode" "RVVM2x3BF") (const_int 8) + (eq_attr "mode" "RVVM1x3BF") (const_int 16) + (eq_attr "mode" "RVVMF2x3BF") (const_int 32) + (eq_attr "mode" "RVVMF4x3BF") (const_int 64) + (eq_attr "mode" "RVVM4x2BF") (const_int 4) + (eq_attr "mode" "RVVM2x2BF") (const_int 8) + (eq_attr "mode" "RVVM1x2BF") (const_int 16) + (eq_attr "mode" "RVVMF2x2BF") (const_int 32) + (eq_attr "mode" "RVVMF4x2BF") (const_int 64) (eq_attr "mode" "RVVM1x8HF") (const_int 16) (eq_attr "mode" "RVVMF2x8HF") (const_int 32) (eq_attr "mode" "RVVMF4x8HF") (const_int 64) @@ -723,7 +795,8 @@ vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\ vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\ - vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh") + vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh,\ + vfncvtbf16,vfwcvtbf16,vfwmaccbf16") (const_int 2) (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\ @@ -767,7 +840,8 @@ vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\ vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\ vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\ - vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c") + vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\ + vfncvtbf16,vfwcvtbf16") (const_int 4) ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. @@ -783,7 +857,7 @@ vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\ vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\ - vror,vwsll,vclmul,vclmulh") + vror,vwsll,vclmul,vclmulh,vfwmaccbf16") (const_int 5) (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd") @@ -800,7 +874,8 @@ vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\ vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\ vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\ - vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c") + vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\ + vfncvtbf16,vfwcvtbf16") (symbol_ref "riscv_vector::get_ta(operands[5])") ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. @@ -816,7 +891,8 @@ vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\ vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\ vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ - vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh") + vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh,\ + vfwmaccbf16") (symbol_ref "riscv_vector::get_ta(operands[6])") (eq_attr "type" "vimuladd,vfmuladd") @@ -830,7 +906,8 @@ (define_attr "ma" "" (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\ vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\ - vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8") + vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,\ + vfncvtbf16,vfwcvtbf16") (symbol_ref "riscv_vector::get_ma(operands[6])") ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast. @@ -846,7 +923,7 @@ vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\ vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\ viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\ - vror,vwsll,vclmul,vclmulh") + vror,vwsll,vclmul,vclmulh,vfwmaccbf16") (symbol_ref "riscv_vector::get_ma(operands[7])") (eq_attr "type" "vimuladd,vfmuladd") @@ -862,7 +939,8 @@ vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\ vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\ vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\ - vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8") + vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8,\ + vfncvtbf16,vfwcvtbf16") (const_int 7) (eq_attr "type" "vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\ vsm4r") @@ -880,7 +958,8 @@ vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\ vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\ vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\ - vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll") + vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll,\ + vfwmaccbf16") (const_int 8) (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox") (const_int 5)