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Mon, 24 Jun 2024 06:10:27 -0500 From: Thippeswamy Havalige To: , , , , , CC: , , , , "Thippeswamy Havalige" Subject: [PATCH] dt-bindings: PCI: xilinx-cpm: Fix ranges property to avoid overlapping of bridge register and 32-bit BAR addresses Date: Mon, 24 Jun 2024 16:40:22 +0530 Message-ID: <20240624111022.133780-1-thippesw@amd.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: thippesw@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F2:EE_|SA1PR12MB6727:EE_ X-MS-Office365-Filtering-Correlation-Id: dcd1af35-5295-4922-cb5c-08dc943e433f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|82310400023|36860700010|376011; X-Microsoft-Antispam-Message-Info: MPbWwqIBKt5yPrlknheAoxjqrJnC+yB2KdfDd+mLPDb0VkAqRXkTwQJwxTkpPf3kPmA1VeZKSMYUkDFL9VrV6XWXm53fSWFJms9c2DaINgCNT9bLcIszlQMNioAd92CjPRUn2Q/EB+2pxtgXFNIMuJFa8VETzeBeTgFj7WiIiP/qD4I4u8R+2X8RRDONAS/EimA8JDsqyam+Cu8IpHvYV7I+dbRZfD+XaD8zCIR+B+krjSBmQhaaAhcwhx6am85qVUMWVVQEtkkBoM2gyTKv2Yh/OefzyzoZjxrs5I61mBCNldefFxxPiEm522TwKBA+0CXJrKcw+f47x4JYqBYjz+TXoZxfPX5sswNrtdcfRtn6ZuX4SL6pewwKjSBln+vj+F0ga+8/POp7fy8xHQE/cYA2TWUubP22eP/vS82HdTShf27utPMmE3EjFZGGMTSodniMmPe3KfY0/9P/4gd/M/Uf2yEBcCjCmkeJkPw/Fi9QfA/GKkD2GEpw/2PjlUtLuzyD5yiagx7xoqknA6/PqNPKsZwyadQupvyAB7tu1PLrN5NOqCorXxxBuVBQ+4PwMwBZcembgzNcG6agwGE0GPbeuA7RGQ3+/Bf80quXfBhXxltMX8m7CM42NkyujNj5a47qLRrsws7LzPb7bppGvRuzRhEtrJF0hOClHEZjK8T0geNhaFtzFoX3Q2t2Ex/f1JLwO4JmH827LwuTzi1H9ZbY3R1tkcT5C8wC2NssInfmfA9hfkdxloHz0u8nqT/aI4n2WFFiGKKl6cTHtXs+S66E14kErGi8cbEre6Q9rk6qw0kqEGMwOeNpdZ7ajXZaA5W2HF0LJd9NCZhlNCmA5ZkbD3fFH4JfACEZx9KH29g2D1I+45D6tqZVGNqFYAG4XgZpDzmvltvUSeXC/BBmvOFyWpgcSX23oP1Q/88pdEygSuksgHmswvSylIAwmS3Gq1ZyJoHw7Geymg+81/whZ319sntHrY8BBFS9ry60pFh4qdPvLWx+Or2GYOVkOJDzuE6Yj7xV9YIoomrbfn535r1uJPLhTq+6K5Iyir0N4DBrcPhCq6zW+l+82EgyBu6pJe2i74t6L3GhQEwOzTQmwvP06cqVuvdxoWG9RIFI6g0h+zb8w8HwSnQn8etqrKUPmDaWZ+BqJ+1F+cgk8BP1svYVyTIk+IXHB4g5dzifs81AwX5sBrBk6PgIAKAIynV6biaxQllGvduyuQJaFhJ3MNK2cCW/lVAZh6sZYnPBNkLUB8lUcZAzUXzCDD8pE4BsOquX3z5Gr7v476Ia0fC7kNQEi+35pvqlf3O9vg+O5etmIWrlJaSxWpJJm9MO/CLPMrgc7nOS/KX/FuiJ/9MueJ3IsO4ixCiChLjbszOanbOTsnT9uDoePP85QENgIIUM80xKh+cmO/OWHf/yAv6TRQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230037)(1800799021)(82310400023)(36860700010)(376011);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Jun 2024 11:10:31.5342 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dcd1af35-5295-4922-cb5c-08dc943e433f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6727 The current configuration had non-prefetchable memory overlapping with bridge registers by 64KB from base address. This patch fixes the 'ranges' property in the device tree by adjusting the non-prefetchable memory addresses beyond the 64KB mark to prevent conflicts. Signed-off-by: Thippeswamy Havalige Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 4770ce02fcc3..989fb0fa2577 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -92,7 +92,7 @@ examples: <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; bus-range = <0x00 0xff>; - ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>, <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &its_gic 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>,