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Fri, 21 Jun 2024 14:46:35 +0000 (UTC) X-SNPS-Relay: synopsys.com From: Artemiy Volkov To: gcc-patches@gcc.gnu.org, zengxiao@eswincomputing.com, jlaw@ventanamicro.com Cc: Artemiy Volkov Subject: [PATCH] RISC-V: Fix unrecognizable pattern in riscv_expand_conditional_move() Date: Fri, 21 Jun 2024 07:46:12 -0700 Message-Id: <20240621144612.122744-1-artemiy@synopsys.com> X-Mailer: git-send-email 2.37.1 MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: MQfRu9bJSNBKvMoMb25bX1ym0VIDn70c X-Proofpoint-GUID: MQfRu9bJSNBKvMoMb25bX1ym0VIDn70c X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-21_06,2024-06-21_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_active_cloned_notspam policy=outbound_active_cloned score=0 impostorscore=0 bulkscore=0 phishscore=0 mlxlogscore=926 clxscore=1011 spamscore=0 suspectscore=0 adultscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406210107 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: Artemiy.Volkov@synopsys.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Presently, the code fragment: int x[5]; void d(int a, int b, int c) { for (int i = 0; i < 5; i++) x[i] = (a != b) ? c : a; } causes an ICE when compiled with -O2 -march=rv32i_zicond: test.c: In function 'd': test.c: error: unrecognizable insn: 11 | } | ^ (insn 8 5 9 2 (set (reg:SI 139 [ iftmp.0_2 ]) (if_then_else:SI (ne:SI (reg/v:SI 136 [ a ]) (reg/v:SI 137 [ b ])) (reg/v:SI 136 [ a ]) (reg/v:SI 138 [ c ]))) -1 (nil)) during RTL pass: vregs This happens because, as part of one of the optimizations in riscv_expand_conditional_move(), an if_then_else is generated with both comparands being register operands, resulting in an unmatchable insn since Zicond patterns require constant 0 as the second comparand. Fix this by adding a extra check before performing this optimization. The code snippet mentioned above is also included in this patch as a new Zicond testcase. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Add a CONST0_RTX check. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-ice-3.c: New test. Signed-off-by: Artemiy Volkov --- gcc/config/riscv/riscv.cc | 3 ++- gcc/testsuite/gcc.target/riscv/zicond-ice-3.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-3.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 029c80b21cf..6c58687b5e5 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4674,8 +4674,9 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) /* reg, reg */ else if (REG_P (cons) && REG_P (alt)) { - if ((code == EQ && rtx_equal_p (cons, op0)) + if (((code == EQ && rtx_equal_p (cons, op0)) || (code == NE && rtx_equal_p (alt, op0))) + && op1 == CONST0_RTX (mode)) { rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); if (!rtx_equal_p (cons, op0)) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c new file mode 100644 index 00000000000..ac6049c9ae5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */ + +int x[5]; + +void +d(int a, int b, int c) { + for (int i = 0; i < 5; i++) + x[i] = (a != b) ? c : a; +}