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Wed, 19 Jun 2024 10:20:45 -0700 (PDT) Received: from localhost.localdomain ([194.169.55.179]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c4c45cb92csm13196087a91.14.2024.06.19.10.20.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 19 Jun 2024 10:20:45 -0700 (PDT) From: YunQiang Su To: gcc-patches@gcc.gnu.org Cc: rguenther@suse.de, YunQiang Su Subject: [PATCH] MIPS: Implement vcond_mask optabs for MSA Date: Thu, 20 Jun 2024 01:20:36 +0800 Message-Id: <20240619172037.10654-1-syq@gcc.gnu.org> X-Mailer: git-send-email 2.39.3 (Apple Git-146) MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Currently, we have `mips_expand_vec_cond_expr`, which calculate cmp_res first. We can just add a new extra argument to ask it to use operands[3] as cmp_res instead of calculating from operands[4] and operands[5]. gcc * config/mips/mips.cc(mips_expand_vec_cond_expr): Add extra argument to info that opernads[3] is cmp_res already. * config/mips/mips-msa.md(vcond_mask): Define new expand. (vcondu): Use mips_expand_vec_cond_expr with 4th argument. (vcond): Ditto. --- gcc/config/mips/mips-msa.md | 17 +++++++++++++++-- gcc/config/mips/mips-protos.h | 2 +- gcc/config/mips/mips.cc | 18 ++++++++++++------ 3 files changed, 28 insertions(+), 9 deletions(-) diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 779157f2a0c..0081b688ce9 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -411,6 +411,19 @@ (define_expand "vec_set" DONE; }) +(define_expand "vcond_mask_" + [(match_operand:MSA 0 "register_operand") + (match_operand:MSA 1 "reg_or_m1_operand") + (match_operand:MSA 2 "reg_or_0_operand") + (match_operand:IMSA 3 "register_operand")] + "ISA_HAS_MSA + && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))" +{ + mips_expand_vec_cond_expr (mode, mode, operands, true); + DONE; +}) + + (define_expand "vcondu" [(match_operand:MSA 0 "register_operand") (match_operand:MSA 1 "reg_or_m1_operand") @@ -421,7 +434,7 @@ (define_expand "vcondu" "ISA_HAS_MSA && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))" { - mips_expand_vec_cond_expr (mode, mode, operands); + mips_expand_vec_cond_expr (mode, mode, operands, false); DONE; }) @@ -435,7 +448,7 @@ (define_expand "vcond" "ISA_HAS_MSA && (GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (mode))" { - mips_expand_vec_cond_expr (mode, mode, operands); + mips_expand_vec_cond_expr (mode, mode, operands, false); DONE; }) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index fcc0a0ae663..75f80984c03 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -385,7 +385,7 @@ extern mulsidi3_gen_fn mips_mulsidi3_gen_fn (enum rtx_code); #endif extern void mips_register_frame_header_opt (void); -extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *); +extern void mips_expand_vec_cond_expr (machine_mode, machine_mode, rtx *, bool); extern void mips_expand_vec_cmp_expr (rtx *); extern void mips_emit_speculation_barrier_function (void); diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index b7acf041903..b1219385096 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -22777,14 +22777,20 @@ mips_expand_vec_cmp_expr (rtx *operands) void mips_expand_vec_cond_expr (machine_mode mode, machine_mode vimode, - rtx *operands) + rtx *operands, bool mask) { - rtx cond = operands[3]; - rtx cmp_op0 = operands[4]; - rtx cmp_op1 = operands[5]; - rtx cmp_res = gen_reg_rtx (vimode); + rtx cmp_res; + if (mask) + cmp_res = operands[3]; + else + { + rtx cond = operands[3]; + rtx cmp_op0 = operands[4]; + rtx cmp_op1 = operands[5]; + cmp_res = gen_reg_rtx (vimode); - mips_expand_msa_cmp (cmp_res, GET_CODE (cond), cmp_op0, cmp_op1); + mips_expand_msa_cmp (cmp_res, GET_CODE (cond), cmp_op0, cmp_op1); + } /* We handle the following cases: 1) r = a CMP b ? -1 : 0