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X-CSE-ConnectionGUID: wySmCRz0TFupteHWpEAzMQ== X-CSE-MsgGUID: RC2vcQ3yQsOMBRjrU+sJbg== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453115" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453115" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:12 -0700 X-CSE-ConnectionGUID: Kiw1o03pTpaeQV3ibwi0VA== X-CSE-MsgGUID: LB+eO98QQw6Ts+afLQhSug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368330" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:10 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id ECAE01007372; Wed, 19 Jun 2024 21:17:08 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 1/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 3 Date: Wed, 19 Jun 2024 21:16:58 +0800 Message-Id: <20240619131705.3874097-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 3 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 3: #define DEF_VEC_SAT_U_SUB_FMT_3(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x > y ? x - y : 0; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 17 +++++ .../rvv/autovec/binop/vec_sat_u_sub-10.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-11.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-12.c | 20 +++++ .../riscv/rvv/autovec/binop/vec_sat_u_sub-9.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-10.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-11.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-12.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-9.c | 75 +++++++++++++++++++ 9 files changed, 396 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 443f88261ba..182cf2cf064 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -167,9 +167,26 @@ vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_3(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + out[i] = x > y ? x - y : 0; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) + #define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c new file mode 100644 index 00000000000..e1c4020b36d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_3: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_3(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c new file mode 100644 index 00000000000..cf744ade7c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_3: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_3(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c new file mode 100644 index 00000000000..c2d7e01ddf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_3: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_3(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c new file mode 100644 index 00000000000..5075a535dd1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_3: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_3(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c new file mode 100644 index 00000000000..d827c6be73b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-10.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c new file mode 100644 index 00000000000..1f99d0d7b21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-11.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c new file mode 100644 index 00000000000..a9ad03c3898 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-12.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c new file mode 100644 index 00000000000..d87d48b4e94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-9.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 + +DEF_VEC_SAT_U_SUB_FMT_3(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:16:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1949688 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=Lp0e9t+0; dkim-atps=neutral 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a="15453153" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453153" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:16 -0700 X-CSE-ConnectionGUID: gpCxtUKUTNKEf78BLZWJhA== X-CSE-MsgGUID: xQoqIwtXRqmmTI8K5u+9Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368366" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:14 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 30A441007372; Wed, 19 Jun 2024 21:17:13 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 2/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 4 Date: Wed, 19 Jun 2024 21:16:59 +0800 Message-Id: <20240619131705.3874097-2-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 4 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 4: #define DEF_VEC_SAT_U_SUB_FMT_4(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x >= y ? x - y : 0; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 16 ++++ .../rvv/autovec/binop/vec_sat_u_sub-13.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-14.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-15.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-16.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-13.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-14.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-15.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-16.c | 75 +++++++++++++++++++ 9 files changed, 395 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 182cf2cf064..a83f964df0c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -180,6 +180,19 @@ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_4(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + out[i] = x >= y ? x - y : 0; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -189,4 +202,7 @@ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c new file mode 100644 index 00000000000..d4d098f0623 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_4: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_4(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c new file mode 100644 index 00000000000..ba274f514dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_4: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_4(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c new file mode 100644 index 00000000000..5b666be33be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_4: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_4(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c new file mode 100644 index 00000000000..6830f06945c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_4: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_4(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c new file mode 100644 index 00000000000..b56115d55b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-13.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c new file mode 100644 index 00000000000..220007dc6fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-14.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c new file mode 100644 index 00000000000..5876148784c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-15.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c new file mode 100644 index 00000000000..468193932bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-16.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 + +DEF_VEC_SAT_U_SUB_FMT_4(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:17:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1949690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com 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3ysaB2DMT/6JN1hi2UPi7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453158" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453158" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:18 -0700 X-CSE-ConnectionGUID: r1TbcARGSUuUsxjDx791Yg== X-CSE-MsgGUID: GD/Gef0QSY+YIxD714oQeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368370" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:15 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id EE2B41007373; Wed, 19 Jun 2024 21:17:13 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 3/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 5 Date: Wed, 19 Jun 2024 21:17:00 +0800 Message-Id: <20240619131705.3874097-3-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 5 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 5: #define DEF_VEC_SAT_U_SUB_FMT_5(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x < y ? 0 : x - y; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 16 ++++ .../rvv/autovec/binop/vec_sat_u_sub-17.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-18.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-19.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-20.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-17.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-18.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-19.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-20.c | 75 +++++++++++++++++++ 9 files changed, 395 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index a83f964df0c..b25215c10cb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -193,6 +193,19 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_5(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + out[i] = x < y ? 0 : x - y; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -205,4 +218,7 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c new file mode 100644 index 00000000000..8d50f5ff26c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c new file mode 100644 index 00000000000..a431ded301c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c new file mode 100644 index 00000000000..acc7ef2d4f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c new file mode 100644 index 00000000000..d74c0972635 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_5: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_5(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c new file mode 100644 index 00000000000..12207ad7f52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-17.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c new file mode 100644 index 00000000000..9614f42417a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-18.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c new file mode 100644 index 00000000000..cbaf2b14279 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-19.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c new file mode 100644 index 00000000000..e1c59a977f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-20.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 + +DEF_VEC_SAT_U_SUB_FMT_5(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:17:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1949693 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com 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X3mWAFOhTN+3TbUrQebx6A== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453161" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453161" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:18 -0700 X-CSE-ConnectionGUID: 15t2cQopSYeQz+LNUGSqdQ== X-CSE-MsgGUID: zRuHvd50RXSk9CQpbye9kQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368376" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:15 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 93E991007377; Wed, 19 Jun 2024 21:17:14 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 4/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 6 Date: Wed, 19 Jun 2024 21:17:01 +0800 Message-Id: <20240619131705.3874097-4-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 6 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 6: #define DEF_VEC_SAT_U_SUB_FMT_6(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ out[i] = x <= y ? 0 : x - y; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 16 ++++ .../rvv/autovec/binop/vec_sat_u_sub-21.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-22.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-23.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-24.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-21.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-22.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-23.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-24.c | 75 +++++++++++++++++++ 9 files changed, 395 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index b25215c10cb..fd4d88e6f30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -206,6 +206,19 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_6(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + out[i] = x <= y ? 0 : x - y; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -221,4 +234,7 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c new file mode 100644 index 00000000000..9799a1eb0c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_6: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_6(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c new file mode 100644 index 00000000000..bb1eeb42cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_6: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_6(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c new file mode 100644 index 00000000000..642003cc118 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_6: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_6(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c new file mode 100644 index 00000000000..9bc95295738 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_6: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_6(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c new file mode 100644 index 00000000000..aec82f86376 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-21.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c new file mode 100644 index 00000000000..bd5c7d206b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-22.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c new file mode 100644 index 00000000000..f5a1d6bd930 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-23.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c new file mode 100644 index 00000000000..62c54a21e6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-24.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 + +DEF_VEC_SAT_U_SUB_FMT_6(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:17:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1949695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com 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snV9v+URSg6EGn/6peonjg== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453176" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453176" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:19 -0700 X-CSE-ConnectionGUID: 5d+sIbdwShShCy0l6CZ1HQ== X-CSE-MsgGUID: Ord+a6trTja5aLOmgKBYJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368383" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:16 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 33593100737C; Wed, 19 Jun 2024 21:17:15 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 5/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 7 Date: Wed, 19 Jun 2024 21:17:02 +0800 Message-Id: <20240619131705.3874097-5-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 7 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 7: #define DEF_VEC_SAT_U_SUB_FMT_7(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = ret & (T)(overflow - 1); \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 18 +++++ .../rvv/autovec/binop/vec_sat_u_sub-25.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-26.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-27.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-28.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-25.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-26.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-27.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-28.c | 75 +++++++++++++++++++ 9 files changed, 397 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index fd4d88e6f30..69fbc6b5258 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -219,6 +219,21 @@ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_7(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = ret & (T)(overflow - 1); \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -237,4 +252,7 @@ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c new file mode 100644 index 00000000000..760eb3140bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_7: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_7(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c new file mode 100644 index 00000000000..15881615812 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_7: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_7(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c new file mode 100644 index 00000000000..611923bdc06 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_7: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_7(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c new file mode 100644 index 00000000000..7fd0a1c2446 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_7: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_7(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c new file mode 100644 index 00000000000..b5bc00195a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-25.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c new file mode 100644 index 00000000000..4446e150493 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-26.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c new file mode 100644 index 00000000000..dd725a5c8ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-27.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c new file mode 100644 index 00000000000..6baf65bea18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-28.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 + +DEF_VEC_SAT_U_SUB_FMT_7(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:17:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1949689 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit 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/hx7Ha1CQgCaehJssBZURg== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453194" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453194" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:20 -0700 X-CSE-ConnectionGUID: adnqMwzdQWSteXwJM9eInA== X-CSE-MsgGUID: 68fUTnB/TceVLHzkf+hCIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368392" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:17 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 5D2FF10077C2; Wed, 19 Jun 2024 21:17:16 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 6/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 8 Date: Wed, 19 Jun 2024 21:17:03 +0800 Message-Id: <20240619131705.3874097-6-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 8 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 8: #define DEF_VEC_SAT_U_SUB_FMT_8(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = ret & (T)-(!overflow); \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 18 +++++ .../rvv/autovec/binop/vec_sat_u_sub-29.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-30.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-31.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-32.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-29.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-30.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-31.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-32.c | 75 +++++++++++++++++++ 9 files changed, 397 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 69fbc6b5258..302fc458708 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -234,6 +234,21 @@ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_8(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = ret & (T)-(!overflow); \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -255,4 +270,7 @@ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c new file mode 100644 index 00000000000..2af9357948a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_8: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_8(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c new file mode 100644 index 00000000000..7c2922be80d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_8: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_8(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c new file mode 100644 index 00000000000..4be50b94f27 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_8: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_8(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c new file mode 100644 index 00000000000..28f05dca93b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_8: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_8(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c new file mode 100644 index 00000000000..b828e95b8a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-29.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c new file mode 100644 index 00000000000..232f78d3544 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-30.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c new file mode 100644 index 00000000000..03355327c6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-31.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c new file mode 100644 index 00000000000..f8872ca521b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-32.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 + +DEF_VEC_SAT_U_SUB_FMT_8(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:17:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 1949691 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit 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5m/nT84qSPK0iGUkPtzv4A== X-IronPort-AV: E=McAfee;i="6700,10204,11107"; a="15453206" X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="15453206" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jun 2024 06:17:21 -0700 X-CSE-ConnectionGUID: eEPsFV+pRxmkPDu6dqCm5A== X-CSE-MsgGUID: XXBV43KUQKGqNqQCSjV47g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,250,1712646000"; d="scan'208";a="46368400" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa005.fm.intel.com with ESMTP; 19 Jun 2024 06:17:18 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 332C410077FE; Wed, 19 Jun 2024 21:17:17 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 7/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 9 Date: Wed, 19 Jun 2024 21:17:04 +0800 Message-Id: <20240619131705.3874097-7-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 9 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 9: #define DEF_VEC_SAT_U_SUB_FMT_9(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = overflow ? 0 : ret; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-33.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-34.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-35.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-36.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-33.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-34.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-35.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-36.c | 75 +++++++++++++++++++ 9 files changed, 398 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 302fc458708..e231d1e66aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -2,6 +2,7 @@ #define HAVE_VEC_SAT_ARITH #include +#include /******************************************************************************/ /* Saturation Add (unsigned and signed) */ @@ -249,6 +250,21 @@ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_9(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + bool overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = overflow ? 0 : ret; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -273,4 +289,7 @@ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c new file mode 100644 index 00000000000..3478bb6ebc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_9: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_9(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c new file mode 100644 index 00000000000..a5293953535 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_9: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_9(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c new file mode 100644 index 00000000000..69b2a60ea7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_9: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_9(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c new file mode 100644 index 00000000000..86c60cdbd44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_9: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_9(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c new file mode 100644 index 00000000000..e8f38813cab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-33.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c new file mode 100644 index 00000000000..346e1df39f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-34.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c new file mode 100644 index 00000000000..587a36a93f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-35.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c new file mode 100644 index 00000000000..84a71050e81 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-36.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 + +DEF_VEC_SAT_U_SUB_FMT_9(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" From patchwork Wed Jun 19 13:17:05 2024 Content-Type: text/plain; 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pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 112721007BBA; Wed, 19 Jun 2024 21:17:18 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li Subject: [PATCH v1 8/8] RISC-V: Add testcases for unsigned .SAT_SUB vector form 10 Date: Wed, 19 Jun 2024 21:17:05 +0800 Message-Id: <20240619131705.3874097-8-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240619131705.3874097-1-pan2.li@intel.com> References: <20240619131705.3874097-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_LOTSOFHASH, KAM_NUMSUBJECT, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org From: Pan Li After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the .SAT_SUB for vector mode, thus add more test case to cover that. Form 10: #define DEF_VEC_SAT_U_SUB_FMT_10(T) \ void __attribute__((noinline)) \ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ { \ unsigned i; \ for (i = 0; i < limit; i++) \ { \ T x = op_1[i]; \ T y = op_2[i]; \ T ret; \ bool overflow = __builtin_sub_overflow (x, y, &ret); \ out[i] = !overflow ? ret : 0; \ } \ } Passed the rv64gcv regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add test macro. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c: New test. * gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c: New test. Signed-off-by: Pan Li --- .../riscv/rvv/autovec/binop/vec_sat_arith.h | 18 +++++ .../rvv/autovec/binop/vec_sat_u_sub-37.c | 19 +++++ .../rvv/autovec/binop/vec_sat_u_sub-38.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-39.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-40.c | 20 +++++ .../rvv/autovec/binop/vec_sat_u_sub-run-37.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-38.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-39.c | 75 +++++++++++++++++++ .../rvv/autovec/binop/vec_sat_u_sub-run-40.c | 75 +++++++++++++++++++ 9 files changed, 397 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index e231d1e66aa..d5c81fbe5a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -265,6 +265,21 @@ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_10(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + bool overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = !overflow ? ret : 0; \ + } \ +} + #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) @@ -292,4 +307,7 @@ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c new file mode 100644 index 00000000000..d58da2abd76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint8_t_fmt_10: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_10(uint8_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c new file mode 100644 index 00000000000..a8ec4f6548c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint16_t_fmt_10: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma +** ... +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_10(uint16_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c new file mode 100644 index 00000000000..0bb1b46e319 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint32_t_fmt_10: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma +** ... +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_10(uint32_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c new file mode 100644 index 00000000000..d75c101a6be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_sub_uint64_t_fmt_10: +** ... +** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma +** ... +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\) +** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_SUB_FMT_10(uint64_t) + +/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c new file mode 100644 index 00000000000..ba5642aa204 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-37.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c new file mode 100644 index 00000000000..bdb1ca3bbb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-38.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c new file mode 100644 index 00000000000..10ec04f2ad3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-39.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +#include "vec_sat_binary.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c new file mode 100644 index 00000000000..f6a1277225a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-run-40.c @@ -0,0 +1,75 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 + +DEF_VEC_SAT_U_SUB_FMT_10(T) + +T test_data[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +#include "vec_sat_binary.h"