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Mon, 17 Jun 2024 23:49:38 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45HNnb6C017427 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 17 Jun 2024 23:49:37 GMT Received: from hu-apinski-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 17 Jun 2024 16:49:37 -0700 From: Andrew Pinski To: CC: Andrew Pinski Subject: [COMMITTED] aarch64: Add testcase for PR97405 Date: Mon, 17 Jun 2024 16:49:25 -0700 Message-ID: <20240617234925.4192451-1-quic_apinski@quicinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KaY8hUjskGmQRF8vXPorbt3wEpeIkOZD X-Proofpoint-GUID: KaY8hUjskGmQRF8vXPorbt3wEpeIkOZD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-17_14,2024-06-17_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 spamscore=0 phishscore=0 mlxlogscore=897 impostorscore=0 clxscore=1015 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406170184 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org This aarch64 sve specific code was fixed by r15-917-gc9842f99042454 which added a riscv specific testcase so adding an aarch64 one to test the fix does not regress is a good idea. Committed as obvious after testing the testcase for aarch64-linux-gnu. PR tree-optimization/97405 gcc/testsuite/ChangeLog: * gcc.target/aarch64/sve/pr97405-1.c: New test. Signed-off-by: Andrew Pinski --- gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c new file mode 100644 index 00000000000..5efa32c9928 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8.2-a+sve -O2" } +/* PR tree-optimization/97405 */ +#include "arm_sve.h" + +void +a (svuint8x3_t b, unsigned char *p, int c) { + if (c) + svst1_u8(svptrue_pat_b8(SV_VL16), p, svget3_u8(b, 1)); + else + svst1_u8(svwhilelt_b8(6, 6), p, svget3_u8(b, 1)); +} +