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[31.10.206.125]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57cb72da790sm6116966a12.35.2024.06.17.02.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 02:22:51 -0700 (PDT) From: Emanuele Ghidoli To: u-boot@lists.denx.de Cc: Emanuele Ghidoli , "Bryan Brattlof" , "Marcel Ziswiler" , Hari Nagalla , Apurva Nandan , Sean Anderson , Nishanth Menon , Roger Quadros , "Tom Rini" Subject: [PATCH v1] arm: mach-k3: j784s4: Fix MCU_CLKOUT0 parent clock mux Date: Mon, 17 Jun 2024 11:22:01 +0200 Message-Id: <20240617092201.30245-1-ghidoliemanuele@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean From: Emanuele Ghidoli MCU_CLKOUT0 output can be driven by two different clock inputs: one at 25 MHz and another at 50 MHz. Currently, the 25 MHz input clock is not selectable due to a duplication of the 50 MHz clock input in the mux configuration. This commit corrects the parent clock mux configuration, making the 25 MHz input clock selectable. Signed-off-by: Emanuele Ghidoli Reviewed-by: Bryan Brattlof --- arch/arm/mach-k3/r5/j784s4/clk-data.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index feaa13ee266b..793bcac93245 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -134,7 +134,7 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { static const char * const mcu_clkout_mux_out0_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", }; static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { @@ -338,7 +338,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 174, "mcu_clkout_mux_out0"), DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), - DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),