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(unknown [IPv6:240e:457:1020:5d9:6735:236f:3f8d:92b6]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 5D07266ED8; Thu, 13 Jun 2024 07:05:45 -0400 (EDT) From: Xi Ruoyao To: libc-alpha@sourceware.org Cc: caiyinyu@loongson.cn, Adhemerval Zanella , mengqinggang@loongson.cn, WANG Xuerui , luweining@loongson.cn, Xi Ruoyao , Jinyang He Subject: [PATCH] LoongArch: Ensure sp 16-byte aligned for tlsdesc Date: Thu, 13 Jun 2024 19:04:05 +0800 Message-ID: <20240613110404.531591-2-xry111@xry111.site> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 X-Spam-Status: No, score=-9.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LIKELY_SPAM_FROM, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org "ADDI sp, sp, 24" and "ADDI sp, sp, SZFCSREG" (SZFCSREG = 4) are misaligning the stack: the ABI mandates a 16-byte alignment. Fix it by changing the first one to "ADDI sp, sp, 32", and reuse the spare 4th slot for saving fcsr. Reported-by: Jinyang He Signed-off-by: Xi Ruoyao --- Tested on loongarch64-linux-gnu. sysdeps/loongarch/dl-tlsdesc.S | 10 ++++------ sysdeps/loongarch/sys/asm.h | 1 - 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/sysdeps/loongarch/dl-tlsdesc.S b/sysdeps/loongarch/dl-tlsdesc.S index 15d5fa1c42..346b80f2ec 100644 --- a/sysdeps/loongarch/dl-tlsdesc.S +++ b/sysdeps/loongarch/dl-tlsdesc.S @@ -100,7 +100,7 @@ _dl_tlsdesc_undefweak: _dl_tlsdesc_dynamic: /* Save just enough registers to support fast path, if we fall into slow path we will save additional registers. */ - ADDI sp, sp, -24 + ADDI sp, sp, -32 REG_S t0, sp, 0 REG_S t1, sp, 8 REG_S t2, sp, 16 @@ -141,7 +141,7 @@ Hign address dynamic_block1 <----- dtv5 */ REG_L t0, sp, 0 REG_L t1, sp, 8 REG_L t2, sp, 16 - ADDI sp, sp, 24 + ADDI sp, sp, 32 RET .Lslow: @@ -171,9 +171,8 @@ Hign address dynamic_block1 <----- dtv5 */ /* Save fcsr0 register. Only one physical fcsr0 register, fcsr1-fcsr3 are aliases of some fields in fcsr0. */ - ADDI sp, sp, -SZFCSREG movfcsr2gr t0, fcsr0 - st.w t0, sp, 0 + st.w t0, sp, FRAME_SIZE + 24 /* Use the spare slot above t2 */ /* Whether support LASX. */ la.global t0, _rtld_global_ro @@ -406,9 +405,8 @@ Hign address dynamic_block1 <----- dtv5 */ .Lfcsr: /* Restore fcsr0 register. */ - ld.w t0, sp, 0 + ld.w t0, sp, FRAME_SIZE + 24 movgr2fcsr fcsr0, t0 - ADDI sp, sp, SZFCSREG #endif /* #ifndef __loongarch_soft_float */ diff --git a/sysdeps/loongarch/sys/asm.h b/sysdeps/loongarch/sys/asm.h index 23c1d12914..51521a7eb4 100644 --- a/sysdeps/loongarch/sys/asm.h +++ b/sysdeps/loongarch/sys/asm.h @@ -25,7 +25,6 @@ /* Macros to handle different pointer/register sizes for 32/64-bit code. */ #define SZREG 8 #define SZFREG 8 -#define SZFCSREG 4 #define SZVREG 16 #define SZXREG 32 #define REG_L ld.d