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Thu, 13 Jun 2024 02:19:44 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4855220043; Thu, 13 Jun 2024 02:19:42 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E086B20040; Thu, 13 Jun 2024 02:19:40 +0000 (GMT) Received: from nilram.aus.stglabs.ibm.com (unknown [9.40.204.36]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 13 Jun 2024 02:19:40 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, linkw@gcc.gnu.org, dje.gcc@gmail.com, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V5 1/2] split complicate 64bit constant to memory Date: Thu, 13 Jun 2024 10:19:38 +0800 Message-ID: <20240613021940.4000707-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.45.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: __fKmcSW7v-uJKKXC2kqi7NC07_hmb2P X-Proofpoint-GUID: DISYmctYnnOG2_9pJh1D-_Ze5U8JsQty X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-12_12,2024-06-12_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 spamscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406130010 X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, Sometimes, a complicated constant is built via 3(or more) instructions. Generally speaking, it would not be as fast as loading it from the constant pool (as the discussions in PR63281): "ld" is one instruction. If consider "address/toc" adjust, we may count it as 2 instructions. And "pld" may need fewer cycles. As testing(SPEC2017), it could get better/stable runtime if set the threshold as "> 2" (compare with "> 3"). As known, because the constant is load from memory by this patch, so this functionality may affect the cache missing. While, IMHO, this patch would be still do the right thing. Compare with the previous version: This version 1. allow assigning complicate constant to r0 before RA, 2. allow more condition beside TARGET_ELF, 3. updated test cases, and remove 2 test cases as the orignal test point is not used any more. Boostrap & regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu Guo) PR target/63281 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Split constant to memory under -m64. gcc/testsuite/ChangeLog: * gcc.target/powerpc/const_anchors.c: Test final-rtl. * gcc.target/powerpc/pr106550_1.c (FORCE_CONST_INTO_REG): New macro. * gcc.target/powerpc/pr106550_1.c: Use macro FORCE_CONST_INTO_REG. * gcc.target/powerpc/pr87870.c: Update asm insn checking. * gcc.target/powerpc/pr93012.c: Likewise. * gcc.target/powerpc/parall_5insn_const.c: Removed. * gcc.target/powerpc/pr106550.c: Removed. * gcc.target/powerpc/pr63281.c: New test. --- gcc/config/rs6000/rs6000.cc | 15 +++++++++++ .../gcc.target/powerpc/const_anchors.c | 5 ++-- .../gcc.target/powerpc/parall_5insn_const.c | 27 ------------------- gcc/testsuite/gcc.target/powerpc/pr106550.c | 14 ---------- gcc/testsuite/gcc.target/powerpc/pr106550_1.c | 16 ++++++----- gcc/testsuite/gcc.target/powerpc/pr63281.c | 11 ++++++++ gcc/testsuite/gcc.target/powerpc/pr87870.c | 5 +++- gcc/testsuite/gcc.target/powerpc/pr93012.c | 6 ++++- 8 files changed, 47 insertions(+), 52 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c delete mode 100644 gcc/testsuite/gcc.target/powerpc/pr106550.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr63281.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e4dc629ddcc..bc9d6f5c34f 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10240,6 +10240,21 @@ rs6000_emit_set_const (rtx dest, rtx source) c = sext_hwi (c, 32); emit_move_insn (lo, GEN_INT (c)); } + + else if ((can_create_pseudo_p () || base_reg_operand (dest, mode)) + && TARGET_64BIT && num_insns_constant (source, mode) > 2) + { + rtx sym = force_const_mem (mode, source); + if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) + && use_toc_relative_ref (XEXP (sym, 0), mode)) + { + rtx toc = create_TOC_reference (XEXP (sym, 0), dest); + sym = gen_const_mem (mode, toc); + set_mem_alias_set (sym, get_TOC_alias_set ()); + } + + emit_move_insn (dest, sym); + } else rs6000_emit_set_long_const (dest, c); break; diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c index 542e2674b12..682e773d506 100644 --- a/gcc/testsuite/gcc.target/powerpc/const_anchors.c +++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c @@ -1,5 +1,5 @@ /* { dg-do compile { target has_arch_ppc64 } } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -fdump-rtl-final" } */ #define C1 0x2351847027482577ULL #define C2 0x2351847027482578ULL @@ -17,4 +17,5 @@ void __attribute__ ((noinline)) foo1 (long long *a, long long b) *a++ = C2; } -/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */ +/* { dg-final { scan-rtl-dump-times {\madddi3\M} 2 "final" } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c deleted file mode 100644 index e3a9a7264cf..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do run } */ -/* { dg-options "-O2 -mno-prefixed -save-temps" } */ -/* { dg-require-effective-target has_arch_ppc64 } */ - -/* { dg-final { scan-assembler-times {\mlis\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mori\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ - -void __attribute__ ((noinline)) foo (unsigned long long *a) -{ - /* 2 lis + 2 ori + 1 rldimi for each constant. */ - *a++ = 0x800aabcdc167fa16ULL; - *a++ = 0x7543a876867f616ULL; -} - -long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL}; -int -main () -{ - long long res[2]; - - foo (res); - if (__builtin_memcmp (res, A, sizeof (res)) != 0) - __builtin_abort (); - - return 0; -} diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550.c b/gcc/testsuite/gcc.target/powerpc/pr106550.c deleted file mode 100644 index 92b76ac8811..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr106550.c +++ /dev/null @@ -1,14 +0,0 @@ -/* PR target/106550 */ -/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ -/* { dg-require-effective-target has_arch_ppc64 } */ - -void -foo (unsigned long long *a) -{ - *a++ = 0x020805006106003; /* pli+pli+rldimi */ - *a++ = 0x2351847027482577;/* pli+pli+rldimi */ -} - -/* { dg-final { scan-assembler-times {\mpli\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ - diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550_1.c b/gcc/testsuite/gcc.target/powerpc/pr106550_1.c index 5ab40d71a56..aa98f31865e 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106550_1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106550_1.c @@ -4,17 +4,19 @@ /* { dg-options "-O2 -mdejagnu-cpu=power10 -fdisable-rtl-split1" } */ /* force the constant splitter run after RA: -fdisable-rtl-split1. */ +#define FORCE_CONST_INTO_REG(DEST, CST) \ + { \ + register long long d asm ("r0") = CST; \ + asm volatile ("std %1, %0" : : "m"(DEST), "r"(d)); \ + } + void foo (unsigned long long *a) { /* Test oris/ori is used where paddi does not work with 'r0'. */ - register long long d asm("r0") = 0x1245abcef9240dec; /* pli+sldi+oris+ori */ - long long n; - asm("cntlzd %0, %1" : "=r"(n) : "r"(d)); - *a++ = n; - - *a++ = 0x235a8470a7480000ULL; /* pli+sldi+oris */ - *a++ = 0x23a184700000b677ULL; /* pli+sldi+ori */ + FORCE_CONST_INTO_REG (*a++, 0x1245abcef9240dec); /* pli+sldi+oris+ori */ + FORCE_CONST_INTO_REG (*a++, 0x235a8470a7480000ULL); /* pli+sldi+oris */ + FORCE_CONST_INTO_REG (*a++, 0x23a184700000b677ULL); /* pli+sldi+ori */ } /* { dg-final { scan-assembler-times {\mpli\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c new file mode 100644 index 00000000000..9763a7181fc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -0,0 +1,11 @@ +/* Check loading constant from memory pool. */ +/* { dg-options "-O2 -mpowerpc64" } */ + +void +foo (unsigned long long *a) +{ + *a++ = 0x2351847027482577ULL; +} + +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/pr87870.c b/gcc/testsuite/gcc.target/powerpc/pr87870.c index d2108ac3386..09b2e8de901 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr87870.c +++ b/gcc/testsuite/gcc.target/powerpc/pr87870.c @@ -25,4 +25,7 @@ test3 (void) return ((__int128)0xdeadbeefcafebabe << 64) | 0xfacefeedbaaaaaad; } -/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* test3 is using "ld" to load the value to r3 and r4. So there are 2 'ld's + test0, test1 and test2 are using "li", then check 6 'li's. */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mli\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr93012.c b/gcc/testsuite/gcc.target/powerpc/pr93012.c index 4f764d0576f..660fb0dddfa 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr93012.c +++ b/gcc/testsuite/gcc.target/powerpc/pr93012.c @@ -10,4 +10,8 @@ unsigned long long mskh1() { return 0xffff9234ffff9234ULL; } unsigned long long mskl1() { return 0x2bcdffff2bcdffffULL; } unsigned long long mskse() { return 0xffff1234ffff1234ULL; } -/* { dg-final { scan-assembler-times {\mrldimi\M} 7 } } */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 7 { target has_arch_pwr10 } } } */ + +/* 4 complicated constants can be loaded from pool. */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 3 { target { ! has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mld\M} 4 { target { ! has_arch_pwr10 } } } } */ From patchwork Thu Jun 13 02:19:39 2024 Content-Type: text/plain; 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Thu, 13 Jun 2024 02:19:46 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E8F412004B; Thu, 13 Jun 2024 02:19:43 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9AE0A20040; Thu, 13 Jun 2024 02:19:42 +0000 (GMT) Received: from nilram.aus.stglabs.ibm.com (unknown [9.40.204.36]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 13 Jun 2024 02:19:42 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, linkw@gcc.gnu.org, dje.gcc@gmail.com, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V5 2/2] split complicate 64bit constant to memory for -m32 -mpowerpc64 Date: Thu, 13 Jun 2024 10:19:39 +0800 Message-ID: <20240613021940.4000707-2-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240613021940.4000707-1-guojiufu@linux.ibm.com> References: <20240613021940.4000707-1-guojiufu@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: FDwOTxCsClfuIrakPPhf03taK1-dvMfu X-Proofpoint-GUID: Wlc4jpxpEAgYuwdLXQKA9kggjp7O814M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-12_12,2024-06-12_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406130010 X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, For "-m32 -mpowerpc64", it is also ok to use just one instruciton (p?ld) to loading 64bit constant from memory. So, splitting the complicate 64bit constant to constant pool should also work under this case. Compare with previous version, this update the threshold for the insn number of the constant. Bootstrap and regtest pass on ppc64{,le}. Also no regression for "-m32 -mpowerpc64" variation on ppc64. Is this ok for trunk? BR, Jeff(Jiufu) Guo gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Split constant to pool for "-m32 -mpowerpc64". gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr63281.c: Allow checking -m32. --- gcc/config/rs6000/rs6000.cc | 21 ++++++++++++++++++++- gcc/testsuite/gcc.target/powerpc/pr63281.c | 4 ++-- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index bc9d6f5c34f..278b39ac9a3 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10242,7 +10242,8 @@ rs6000_emit_set_const (rtx dest, rtx source) } else if ((can_create_pseudo_p () || base_reg_operand (dest, mode)) - && TARGET_64BIT && num_insns_constant (source, mode) > 2) + && num_insns_constant (source, mode) + > (TARGET_32BIT && TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)) { rtx sym = force_const_mem (mode, source); if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) @@ -10252,6 +10253,24 @@ rs6000_emit_set_const (rtx dest, rtx source) sym = gen_const_mem (mode, toc); set_mem_alias_set (sym, get_TOC_alias_set ()); } + else if (TARGET_32BIT) + { + /* After RA, reuse 'DEST' reg. */ + rtx addr = can_create_pseudo_p () + ? gen_reg_rtx (Pmode) + : gen_rtx_REG (Pmode, REGNO (dest)); + rtx sym_ref = XEXP (sym, 0); + if (flag_pic) + emit_move_insn (addr, sym_ref); + else + { + emit_move_insn (addr, gen_rtx_HIGH (Pmode, sym_ref)); + emit_move_insn (addr, gen_rtx_LO_SUM (Pmode, addr, sym_ref)); + } + rtx mem = gen_rtx_MEM (mode, addr); + MEM_COPY_ATTRIBUTES (mem, sym); + sym = mem; + } emit_move_insn (dest, sym); } diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c index 9763a7181fc..d3d620d3bee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63281.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -1,4 +1,4 @@ -/* Check loading constant from memory pool. */ +/* Check loading constant from memory pool under -mpowerpc64 (include -m32). */ /* { dg-options "-O2 -mpowerpc64" } */ void @@ -7,5 +7,5 @@ foo (unsigned long long *a) *a++ = 0x2351847027482577ULL; } -/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { has_arch_ppc64 } } } } */