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Tue, 11 Jun 2024 08:37:31 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D9CC320049; Tue, 11 Jun 2024 08:37:28 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C71672004E; Tue, 11 Jun 2024 08:37:27 +0000 (GMT) Received: from nilram.aus.stglabs.ibm.com (unknown [9.40.204.36]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 11 Jun 2024 08:37:27 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, linkw@gcc.gnu.org, dje.gcc@gmail.com, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V4 1/2] split complicate 64bit constant to memory Date: Tue, 11 Jun 2024 16:37:25 +0800 Message-ID: <20240611083727.2642461-1-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.45.1 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5iSc8gMhoDNHX_-hGhWRed3VmWC2uwY2 X-Proofpoint-ORIG-GUID: cBjyzM6k3FIgjNLzo4Lt45ADMHRGC4fW X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 malwarescore=0 spamscore=0 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406110062 X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, Sometimes, a complicated constant is built via 3(or more) instructions. Generally speaking, it would not be as fast as loading it from the constant pool (as the discussions in PR63281): "ld" is one instruction. If consider "address/toc" adjust, we may count it as 2 instructions. And "pld" may need fewer cycles. As testing(SPEC2017), it could get better/stable runtime if set the threshold as "> 2" (compare with "> 3"). As known, because the constant is load from memory by this patch, so this functionality may affect the cache missing. Also there may be possible side effects on icach. While, IMHO, this patch would be still do the right thing. Compare with the previous version: https://gcc.gnu.org/pipermail/gcc-patches/2023-December/639493.html This version adds safe guard for 64bit, and adds one more test case. And a following patch is drafted to support this functionality for 32bit(-m32) with -mpowerpc64. Boostrap & regtest pass on ppc64{,le}. Is this ok for trunk? BR, Jeff (Jiufu Guo) PR target/63281 gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Update to split complicate constant to memory. gcc/testsuite/ChangeLog: * gcc.target/powerpc/const_anchors.c: Update to test final-rtl. * gcc.target/powerpc/parall_5insn_const.c: Update to keep original test point. * gcc.target/powerpc/pr106550.c: Likewise.. * gcc.target/powerpc/pr106550_1.c: Likewise. * gcc.target/powerpc/pr87870.c: Update according to latest behavior. * gcc.target/powerpc/pr93012.c: Likewise. * gcc.target/powerpc/pr63281.c: New test. --- gcc/config/rs6000/rs6000.cc | 15 +++++++++++++++ .../gcc.target/powerpc/const_anchors.c | 5 +++-- .../gcc.target/powerpc/parall_5insn_const.c | 11 +++++++++-- gcc/testsuite/gcc.target/powerpc/pr106550.c | 12 +++++++++--- gcc/testsuite/gcc.target/powerpc/pr106550_1.c | 18 ++++++++++-------- gcc/testsuite/gcc.target/powerpc/pr63281.c | 11 +++++++++++ gcc/testsuite/gcc.target/powerpc/pr87870.c | 5 ++++- gcc/testsuite/gcc.target/powerpc/pr93012.c | 6 +++++- 8 files changed, 66 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr63281.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index e4dc629ddcc..f448df289a0 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10240,6 +10240,21 @@ rs6000_emit_set_const (rtx dest, rtx source) c = sext_hwi (c, 32); emit_move_insn (lo, GEN_INT (c)); } + + else if (base_reg_operand (dest, mode) && TARGET_64BIT + && TARGET_ELF && num_insns_constant (source, mode) > 2) + { + rtx sym = force_const_mem (mode, source); + if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) + && use_toc_relative_ref (XEXP (sym, 0), mode)) + { + rtx toc = create_TOC_reference (XEXP (sym, 0), copy_rtx (dest)); + sym = gen_const_mem (mode, toc); + set_mem_alias_set (sym, get_TOC_alias_set ()); + } + + emit_move_insn (dest, sym); + } else rs6000_emit_set_long_const (dest, c); break; diff --git a/gcc/testsuite/gcc.target/powerpc/const_anchors.c b/gcc/testsuite/gcc.target/powerpc/const_anchors.c index 542e2674b12..f33c9a83f5e 100644 --- a/gcc/testsuite/gcc.target/powerpc/const_anchors.c +++ b/gcc/testsuite/gcc.target/powerpc/const_anchors.c @@ -1,5 +1,5 @@ /* { dg-do compile { target has_arch_ppc64 } } */ -/* { dg-options "-O2" } */ +/* { dg-options "-O2 -fdump-rtl-final" } */ #define C1 0x2351847027482577ULL #define C2 0x2351847027482578ULL @@ -17,4 +17,5 @@ void __attribute__ ((noinline)) foo1 (long long *a, long long b) *a++ = C2; } -/* { dg-final { scan-assembler-times {\maddi\M} 2 } } */ +/* Checking "final" instead checking "asm" output to avoid noise. */ +/* { dg-final { scan-rtl-dump-times {\madddi3\M} 2 "final" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c index e3a9a7264cf..ff745c730f3 100644 --- a/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c +++ b/gcc/testsuite/gcc.target/powerpc/parall_5insn_const.c @@ -6,11 +6,18 @@ /* { dg-final { scan-assembler-times {\mori\M} 4 } } */ /* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ +/* The below macro helps to avoid loading constant from memory. */ +#define CONST_AVOID_BASE_REG(DEST, CST) \ + { \ + register long long d asm ("r0") = CST; \ + asm volatile ("std %1, %0" : : "m"(DEST), "r"(d)); \ + } + void __attribute__ ((noinline)) foo (unsigned long long *a) { /* 2 lis + 2 ori + 1 rldimi for each constant. */ - *a++ = 0x800aabcdc167fa16ULL; - *a++ = 0x7543a876867f616ULL; + CONST_AVOID_BASE_REG(*a++, 0x800aabcdc167fa16ULL); + CONST_AVOID_BASE_REG(*a++, 0x7543a876867f616ULL); } long long A[] = {0x800aabcdc167fa16ULL, 0x7543a876867f616ULL}; diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550.c b/gcc/testsuite/gcc.target/powerpc/pr106550.c index 92b76ac8811..e5e38b4ea82 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106550.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106550.c @@ -2,13 +2,19 @@ /* { dg-options "-O2 -mdejagnu-cpu=power10" } */ /* { dg-require-effective-target has_arch_ppc64 } */ +/* The below macro helps to avoid loading constant from memory. */ +#define CONST_AVOID_BASE_REG(DEST, CST) \ + { \ + register long long d asm ("r0") = CST; \ + asm volatile ("std %1, %0" : : "m"(DEST), "r"(d)); \ + } + void foo (unsigned long long *a) { - *a++ = 0x020805006106003; /* pli+pli+rldimi */ - *a++ = 0x2351847027482577;/* pli+pli+rldimi */ + CONST_AVOID_BASE_REG (*a++, 0x020805006106003ULL); /* pli+pli+rldimi */ + CONST_AVOID_BASE_REG (*a++, 0x2351847027482577ULL); /* pli+pli+rldimi */ } /* { dg-final { scan-assembler-times {\mpli\M} 4 } } */ /* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */ - diff --git a/gcc/testsuite/gcc.target/powerpc/pr106550_1.c b/gcc/testsuite/gcc.target/powerpc/pr106550_1.c index 5ab40d71a56..66539ee7cf0 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr106550_1.c +++ b/gcc/testsuite/gcc.target/powerpc/pr106550_1.c @@ -4,17 +4,19 @@ /* { dg-options "-O2 -mdejagnu-cpu=power10 -fdisable-rtl-split1" } */ /* force the constant splitter run after RA: -fdisable-rtl-split1. */ +/* The below marco helps to avoid using paddi and avoid loading from memory. */ +#define CONST_AVOID_BASE_REG(DEST, CST) \ + { \ + register long long d asm ("r0") = CST; \ + asm volatile ("std %1, %0" : : "m"(DEST), "r"(d)); \ + } + void foo (unsigned long long *a) { - /* Test oris/ori is used where paddi does not work with 'r0'. */ - register long long d asm("r0") = 0x1245abcef9240dec; /* pli+sldi+oris+ori */ - long long n; - asm("cntlzd %0, %1" : "=r"(n) : "r"(d)); - *a++ = n; - - *a++ = 0x235a8470a7480000ULL; /* pli+sldi+oris */ - *a++ = 0x23a184700000b677ULL; /* pli+sldi+ori */ + CONST_AVOID_BASE_REG (*a++, 0x1245abcef9240dec); /* pli+sldi+oris+ori */ + CONST_AVOID_BASE_REG (*a++, 0x235a8470a7480000ULL); /* pli+sldi+oris */ + CONST_AVOID_BASE_REG (*a++, 0x23a184700000b677ULL); /* pli+sldi+ori */ } /* { dg-final { scan-assembler-times {\mpli\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c new file mode 100644 index 00000000000..9763a7181fc --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -0,0 +1,11 @@ +/* Check loading constant from memory pool. */ +/* { dg-options "-O2 -mpowerpc64" } */ + +void +foo (unsigned long long *a) +{ + *a++ = 0x2351847027482577ULL; +} + +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/pr87870.c b/gcc/testsuite/gcc.target/powerpc/pr87870.c index d2108ac3386..09b2e8de901 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr87870.c +++ b/gcc/testsuite/gcc.target/powerpc/pr87870.c @@ -25,4 +25,7 @@ test3 (void) return ((__int128)0xdeadbeefcafebabe << 64) | 0xfacefeedbaaaaaad; } -/* { dg-final { scan-assembler-not {\mld\M} } } */ +/* test3 is using "ld" to load the value to r3 and r4. So there are 2 'ld's + test0, test1 and test2 are using "li", then check 6 'li's. */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mli\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr93012.c b/gcc/testsuite/gcc.target/powerpc/pr93012.c index 4f764d0576f..660fb0dddfa 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr93012.c +++ b/gcc/testsuite/gcc.target/powerpc/pr93012.c @@ -10,4 +10,8 @@ unsigned long long mskh1() { return 0xffff9234ffff9234ULL; } unsigned long long mskl1() { return 0x2bcdffff2bcdffffULL; } unsigned long long mskse() { return 0xffff1234ffff1234ULL; } -/* { dg-final { scan-assembler-times {\mrldimi\M} 7 } } */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 7 { target has_arch_pwr10 } } } */ + +/* 4 complicated constants can be loaded from pool. */ +/* { dg-final { scan-assembler-times {\mrldimi\M} 3 { target { ! has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mld\M} 4 { target { ! has_arch_pwr10 } } } } */ From patchwork Tue Jun 11 08:37:26 2024 Content-Type: text/plain; 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Tue, 11 Jun 2024 08:37:32 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 36FD420040; Tue, 11 Jun 2024 08:37:30 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 248D52004E; Tue, 11 Jun 2024 08:37:29 +0000 (GMT) Received: from nilram.aus.stglabs.ibm.com (unknown [9.40.204.36]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 11 Jun 2024 08:37:28 +0000 (GMT) From: Jiufu Guo To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, linkw@gcc.gnu.org, dje.gcc@gmail.com, bergner@linux.ibm.com, guojiufu@linux.ibm.com Subject: [PATCH V4 2/2] split complicate 64bit to constant pool under -m32 -mpowerpc64 Date: Tue, 11 Jun 2024 16:37:26 +0800 Message-ID: <20240611083727.2642461-2-guojiufu@linux.ibm.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240611083727.2642461-1-guojiufu@linux.ibm.com> References: <20240611083727.2642461-1-guojiufu@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: _1DwD3iSaOpYaX1pm9_1iz2uGFql9TZc X-Proofpoint-ORIG-GUID: 9XumADP_fPh4_Pw30leWX5EvNsbAS-3i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_04,2024-06-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1011 malwarescore=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 priorityscore=1501 mlxscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406110062 X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Hi, For "-m32 -mpowerpc64", it is also ok to use just one instruciton (p?ld) to loading 64bit constant from memory. So, splitting the complicate 64bit constant to constant pool should also work under this case. Bootstrap and regtest pass on ppc64{,le}. Also no regression for "-m32 -mpowerpc64" variation on ppc64. Is this ok for trunk? BR, Jeff(Jiufu) Guo gcc/ChangeLog: * config/rs6000/rs6000.cc (rs6000_emit_set_const): Support splitting constant to pool for "-m32 -mpowerpc64". gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr63281.c: Update target checking. --- gcc/config/rs6000/rs6000.cc | 22 ++++++++++++++++++++-- gcc/testsuite/gcc.target/powerpc/pr63281.c | 4 ++-- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index f448df289a0..54514d16fea 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10241,8 +10241,8 @@ rs6000_emit_set_const (rtx dest, rtx source) emit_move_insn (lo, GEN_INT (c)); } - else if (base_reg_operand (dest, mode) && TARGET_64BIT - && TARGET_ELF && num_insns_constant (source, mode) > 2) + else if (base_reg_operand (dest, mode) && TARGET_ELF + && num_insns_constant (source, mode) > 2) { rtx sym = force_const_mem (mode, source); if (TARGET_TOC && SYMBOL_REF_P (XEXP (sym, 0)) @@ -10252,6 +10252,24 @@ rs6000_emit_set_const (rtx dest, rtx source) sym = gen_const_mem (mode, toc); set_mem_alias_set (sym, get_TOC_alias_set ()); } + else if (TARGET_32BIT) + { + /* After RA, reuse 'DEST' reg. */ + rtx addr = can_create_pseudo_p () + ? gen_reg_rtx (Pmode) + : gen_rtx_REG (Pmode, REGNO (dest)); + rtx sym_ref = XEXP (sym, 0); + if (flag_pic) + emit_move_insn (addr, sym_ref); + else + { + emit_insn (gen_elf_high (addr, sym_ref)); + emit_move_insn (addr, gen_rtx_LO_SUM (Pmode, addr, sym_ref)); + } + rtx mem = gen_rtx_MEM (mode, addr); + MEM_COPY_ATTRIBUTES (mem, sym); + sym = mem; + } emit_move_insn (dest, sym); } diff --git a/gcc/testsuite/gcc.target/powerpc/pr63281.c b/gcc/testsuite/gcc.target/powerpc/pr63281.c index 9763a7181fc..d3d620d3bee 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr63281.c +++ b/gcc/testsuite/gcc.target/powerpc/pr63281.c @@ -1,4 +1,4 @@ -/* Check loading constant from memory pool. */ +/* Check loading constant from memory pool under -mpowerpc64 (also ok for -m32). */ /* { dg-options "-O2 -mpowerpc64" } */ void @@ -7,5 +7,5 @@ foo (unsigned long long *a) *a++ = 0x2351847027482577ULL; } -/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { lp64 } } } } */ +/* { dg-final { scan-assembler-times {\mp?ld\M} 1 { target { has_arch_ppc64 } } } } */